coreboot-gerrit November 2016

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Patch set updated for coreboot: [WIP]nb/intel/sandybridge/raminit: Fix normalize_training
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17610 -gerrit commit 316618a1a96e114afb050a57b49de9fbdacd5ff4 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 16:00:01 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Fix normalize_training Remove cross rank/cross channel dependency. I guess this is a mistake that could lead to instabilities. UNTESTED! Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3f07632..6b352c2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3022,10 +3022,11 @@ int discover_timC_write(ramctr_timing *ctrl) void normalize_training(ramctr_timing * ctrl) { int channel, slotrank, lane; - int mat = 0; + int mat; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { int delta; + mat = 0; FOR_ALL_LANES mat = max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); printram("normalize %d, %d, %d: mat %d\n",

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Patch set updated for coreboot: [WIP]nb/intel/sandybridge/raminit: Add default values
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17609 -gerrit commit 03850a6845ba8737e5c82a53c067c67990772f42 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 15:40:49 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Add default values Add 100 Mhz reflock default values for Ivybridge. Some values are extracted from MRC, those marked as guessed needs to be verified. UNTESTED! Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_ivy.c | 51 +++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index f432362..baf3b24 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -292,10 +292,28 @@ static void dram_timing(ramctr_timing * ctrl) u8 val; u32 val32; - /* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure - * we cap it if we have faster DIMMs. + /* Maximum supported DDR3 frequency is 1400MHz (DDR3 2800). + * We cap it at 1200Mhz (DDR3 2400). * Then, align it to the closest JEDEC standard frequency */ - if (ctrl->tCK <= TCK_1066MHZ) { + if (ctrl->tCK <= TCK_1200MHZ) { + ctrl->tCK = TCK_1200MHZ; + ctrl->edge_offset[0] = 18; //XXX: guessed + ctrl->edge_offset[1] = 8; + ctrl->edge_offset[2] = 8; + ctrl->timC_offset[0] = 20; //XXX: guessed + ctrl->timC_offset[1] = 8; + ctrl->timC_offset[2] = 8; + ctrl->reg_320c_range_threshold = 10; + } else if (ctrl->tCK <= TCK_1100MHZ) { + ctrl->tCK = TCK_1100MHZ; + ctrl->edge_offset[0] = 17; //XXX: guessed + ctrl->edge_offset[1] = 7; + ctrl->edge_offset[2] = 7; + ctrl->timC_offset[0] = 19; //XXX: guessed + ctrl->timC_offset[1] = 7; + ctrl->timC_offset[2] = 7; + ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_1066MHZ) { ctrl->tCK = TCK_1066MHZ; ctrl->edge_offset[0] = 16; ctrl->edge_offset[1] = 7; @@ -304,6 +322,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 7; ctrl->timC_offset[2] = 7; ctrl->reg_320c_range_threshold = 13; + } else if (ctrl->tCK <= TCK_1000MHZ) { + ctrl->tCK = TCK_1000MHZ; + ctrl->edge_offset[0] = 15; //XXX: guessed + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 17; //XXX: guessed + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 13; } else if (ctrl->tCK <= TCK_933MHZ) { ctrl->tCK = TCK_933MHZ; ctrl->edge_offset[0] = 14; @@ -313,6 +340,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 6; ctrl->timC_offset[2] = 6; ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_900MHZ) { + ctrl->tCK = TCK_900MHZ; + ctrl->edge_offset[0] = 14; //XXX: guessed + ctrl->edge_offset[1] = 6; + ctrl->edge_offset[2] = 6; + ctrl->timC_offset[0] = 15; //XXX: guessed + ctrl->timC_offset[1] = 6; + ctrl->timC_offset[2] = 6; + ctrl->reg_320c_range_threshold = 12; } else if (ctrl->tCK <= TCK_800MHZ) { ctrl->tCK = TCK_800MHZ; ctrl->edge_offset[0] = 13; @@ -322,6 +358,15 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->timC_offset[1] = 5; ctrl->timC_offset[2] = 5; ctrl->reg_320c_range_threshold = 15; + } else if (ctrl->tCK <= TCK_700MHZ) { + ctrl->tCK = TCK_700MHZ; + ctrl->edge_offset[0] = 13; //XXX: guessed + ctrl->edge_offset[1] = 5; + ctrl->edge_offset[2] = 5; + ctrl->timC_offset[0] = 14; //XXX: guessed + ctrl->timC_offset[1] = 5; + ctrl->timC_offset[2] = 5; + ctrl->reg_320c_range_threshold = 16; } else if (ctrl->tCK <= TCK_666MHZ) { ctrl->tCK = TCK_666MHZ; ctrl->edge_offset[0] = 10;

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: Add debugging output
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17608 -gerrit commit 2b8d1ce81271889510961ce0e618324f6c897054 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 15:40:07 2016 +0100 nb/intel/sandybridge/raminit: Add debugging output Add debugging output to normalize_training. Tested on Lenovo T420. Change-Id: I1d787f7ead6cf35ee142a8848837840c91cb6967 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 82d10c5..3f07632 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3028,9 +3028,15 @@ void normalize_training(ramctr_timing * ctrl) int delta; FOR_ALL_LANES mat = max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); - delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; - ctrl->timings[channel][slotrank].val_4024 += delta; - ctrl->timings[channel][slotrank].val_4028 += delta; + printram("normalize %d, %d, %d: mat %d\n", + channel, slotrank, lane, mat); + + delta = (mat >> 6) - ctrl->timings[channel][slotrank].val_4028; + printram("normalize %d, %d, %d: delta %d\n", + channel, slotrank, lane, delta); + + ctrl->timings[channel][slotrank].val_4024 += delta; + ctrl->timings[channel][slotrank].val_4028 += delta; } FOR_ALL_POPULATED_CHANNELS {

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Patch set updated for coreboot: [WIP]nb/intel/sandybridge/raminit: Add 100Mhz refclock support
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17607 -gerrit commit ed0744b3cee41e5f6da77f799e7a16fdf54430a9 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Nov 24 19:40:23 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Add 100Mhz refclock support Add support for 100Mhz reference clock on ivybridge. Allows to use more frequencies than sandybridge. UNTESTED! Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_ivy.c | 43 +++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index fd45014..f432362 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -19,6 +19,8 @@ #include <console/usb.h> #include <cpu/x86/msr.h> #include <delay.h> +#include <arch/io.h> +#include <device/pci_ops.h> #include "raminit_native.h" #include "raminit_common.h" @@ -429,14 +431,20 @@ static void dram_timing(ramctr_timing * ctrl) static void dram_freq(ramctr_timing * ctrl) { + bool ref_100mhz_support; + u32 reg32; + if (ctrl->tCK > TCK_400MHZ) { printk (BIOS_ERR, "DRAM frequency is under lowest supported " "frequency (400 MHz). Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } - /* TODO: implement 100Mhz refclock */ - ctrl->base_freq = 133; + /* 100 Mhz reference clock supported */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + ref_100mhz_support = !!((reg32 >> 21) & 0x7); + printk(BIOS_DEBUG, "100Mhz reference clock support: %u\n", + ref_100mhz_support); while (1) { u8 val2; @@ -444,22 +452,49 @@ static void dram_freq(ramctr_timing * ctrl) /* Step 1 - Set target PCU frequency */ - if (ctrl->tCK <= TCK_1066MHZ) { + if (ctrl->tCK <= TCK_1200MHZ) { + ctrl->tCK = TCK_1200MHZ; + ctrl->base_freq = 100; + } else if (ctrl->tCK <= TCK_1100MHZ) { + ctrl->tCK = TCK_1100MHZ; + ctrl->base_freq = 100; + } else if (ctrl->tCK <= TCK_1066MHZ) { ctrl->tCK = TCK_1066MHZ; + ctrl->base_freq = 133; + } else if (ctrl->tCK <= TCK_1000MHZ) { + ctrl->tCK = TCK_1000MHZ; + ctrl->base_freq = 100; } else if (ctrl->tCK <= TCK_933MHZ) { ctrl->tCK = TCK_933MHZ; + ctrl->base_freq = 133; + } else if (ctrl->tCK <= TCK_900MHZ) { + ctrl->tCK = TCK_900MHZ; + ctrl->base_freq = 100; } else if (ctrl->tCK <= TCK_800MHZ) { ctrl->tCK = TCK_800MHZ; + ctrl->base_freq = 133; + } else if (ctrl->tCK <= TCK_700MHZ) { + ctrl->tCK = TCK_700MHZ; + ctrl->base_freq = 100; } else if (ctrl->tCK <= TCK_666MHZ) { ctrl->tCK = TCK_666MHZ; + ctrl->base_freq = 133; } else if (ctrl->tCK <= TCK_533MHZ) { ctrl->tCK = TCK_533MHZ; + ctrl->base_freq = 133; } else if (ctrl->tCK <= TCK_400MHZ) { ctrl->tCK = TCK_400MHZ; + ctrl->base_freq = 133; } else { die ("No lock frequency found"); } + if (!ref_100mhz_support && ctrl->base_freq == 100) { + /* Skip unsupported frequency. */ + ctrl->tCK++; + continue; + } + /* Frequency multiplier. */ u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); @@ -473,6 +508,8 @@ static void dram_freq(ramctr_timing * ctrl) /* Step 2 - Select frequency in the MCU */ reg1 = FRQ; + if (ctrl->base_freq == 100) + reg1 |= 0x100; /* Enable 100Mhz REF clock */ reg1 |= 0x80000000; // set running bit MCHBAR32(MC_BIOS_REQ) = reg1; int i=0;

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Patch set updated for coreboot: [WIP]nb/intel/sandybridge/raminit: Use Ivybridge specific values
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17606 -gerrit commit 14b9f79353f13afae096ddd544ed57f5bd0790c5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 11 18:55:54 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Use Ivybridge specific values Use Ivybridge specific values on Ivybridge instead of Sandybridge values. The values are extracted from MRC.bin. UNTESTED! Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.h | 3 + src/northbridge/intel/sandybridge/raminit_ivy.c | 341 +++++++++++++++------ src/northbridge/intel/sandybridge/raminit_sandy.c | 6 +- 3 files changed, 255 insertions(+), 95 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 816e90b..e7e1a6f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -79,6 +79,9 @@ typedef struct ramctr_timing_st { int mobile; int sandybridge; + /* DDR base_freq = 100 Mhz / 133 Mhz */ + u8 base_freq; + u16 cas_supported; /* tLatencies are in units of ns, scaled by x256 */ u32 tCK; diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index fe856c5..fd45014 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -23,117 +23,266 @@ #include "raminit_common.h" /* Frequency multiplier. */ -static u32 get_FRQ(u32 tCK) +static u32 get_FRQ(u32 tCK, u8 base_freq) { u32 FRQ; - FRQ = 256000 / (tCK * BASEFREQ); - if (FRQ > 8) - return 8; - if (FRQ < 3) - return 3; + + FRQ = 256000 / (tCK * base_freq); + + if (base_freq == 100) { + if (FRQ > 12) + return 12; + if (FRQ < 7) + return 7; + } else { + if (FRQ > 10) + return 10; + if (FRQ < 3) + return 3; + } + return FRQ; } -static u32 get_REFI(u32 tCK) +static u32 get_REFI(u32 tCK, u8 base_freq) { - /* Get REFI based on MCU frequency using the following rule: - * _________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | - */ - static const u32 frq_refi_map[] = - { 3120, 4160, 5200, 6240, 7280, 8320 }; - return frq_refi_map[get_FRQ(tCK) - 3]; + u32 refi; + + if (base_freq == 100) { + /* Get REFI based on MCU frequency using the following rule: + * tREFI = 7.8usec + * _________________________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * REFI : | 5460 | 6240 | 7020 | 7800 | 8580 | 9360 | + */ + static const u32 frq_xs_map[] = + { 5460, 6240, 7020, 7800, 8580, 9360 }; + refi = frq_xs_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get REFI based on MCU frequency using the following rule: + * tREFI = 7.8usec + * ________________________________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * REFI: | 3120 | 4160 | 5200 | 6240 | 7280 | 8320 | 9360 | 10400 | + */ + static const u32 frq_refi_map[] = + { 3120, 4160, 5200, 6240, 7280, 8320, 9360, 10400 }; + refi = frq_refi_map[get_FRQ(tCK, 133) - 3]; + } + + return refi; } -static u8 get_XSOffset(u32 tCK) +static u8 get_XSOffset(u32 tCK, u8 base_freq) { - /* Get XSOffset based on MCU frequency using the following rule: - * _________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | - */ - static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11 }; - return frq_xs_map[get_FRQ(tCK) - 3]; + u8 xsoffset; + + if (base_freq == 100) { + /* Get XSOffset based on MCU frequency using the following rule: + * tXS-offset: tXS = tRFC+10ns. + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * XSOffset : | 7 | 8 | 9 | 10 | 11 | 12 | + */ + static const u8 frq_xs_map[] = { 7, 8, 9, 10, 11, 12 }; + xsoffset = frq_xs_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get XSOffset based on MCU frequency using the following rule: + * ___________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * XSOffset : | 4 | 6 | 7 | 8 | 10 | 11 | 12 | 14 | + */ + static const u8 frq_xs_map[] = { 4, 6, 7, 8, 10, 11, 12, 14 }; + xsoffset = frq_xs_map[get_FRQ(tCK, 133) - 3]; + } + + return xsoffset; } -static u8 get_MOD(u32 tCK) +static u8 get_MOD(u32 tCK, u8 base_freq) { - /* Get MOD based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | - */ - static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16 }; - return frq_mod_map[get_FRQ(tCK) - 3]; + u8 mod; + + if (base_freq == 100) { + /* Get MOD based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * MOD : | 12 | 12 | 14 | 15 | 17 | 18 | + */ + + static const u8 frq_mod_map[] = { 12, 12, 14, 15, 17, 18 }; + mod = frq_mod_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get MOD based on MCU frequency using the following rule: + * _______________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * MOD : | 12 | 12 | 12 | 12 | 15 | 16 | 18 | 20 | + */ + + static const u8 frq_mod_map[] = { 12, 12, 12, 12, 15, 16, 18, 20 }; + mod = frq_mod_map[get_FRQ(tCK, 133) - 3]; + } + return mod; } -static u8 get_WLO(u32 tCK) +static u8 get_WLO(u32 tCK, u8 base_freq) { - /* Get WLO based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | - */ - static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8 }; - return frq_wlo_map[get_FRQ(tCK) - 3]; + u8 wlo; + + if (base_freq == 100) { + /* Get WLO based on MCU frequency using the following rule: + * Write leveling output delay + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * MOD : | 6 | 6 | 7 | 8 | 9 | 9 | + */ + + static const u8 frq_wlo_map[] = { 6, 6, 7, 8, 9, 9 }; + wlo = frq_wlo_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get WLO based on MCU frequency using the following rule: + * Write leveling output delay + * ________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * WLO : | 4 | 5 | 6 | 6 | 8 | 8 | 9 | 10 | + */ + static const u8 frq_wlo_map[] = { 4, 5, 6, 6, 8, 8, 9, 10 }; + wlo = frq_wlo_map[get_FRQ(tCK, 133) - 3]; + } + + return wlo; } -static u8 get_CKE(u32 tCK) +static u8 get_CKE(u32 tCK, u8 base_freq) { - /* Get CKE based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * CKE : | 3 | 3 | 4 | 4 | 5 | 6 | - */ - static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6 }; - return frq_cke_map[get_FRQ(tCK) - 3]; + u8 cke; + + if (base_freq == 100) { + /* Get CKE based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * MOD : | 4 | 4 | 5 | 5 | 6 | 6 | + */ + + static const u8 frq_cke_map[] = { 4, 4, 5, 5, 6, 6 }; + cke = frq_cke_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get CKE based on MCU frequency using the following rule: + * ________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * WLO : | 3 | 3 | 4 | 4 | 5 | 6 | 6 | 7 | + */ + static const u8 frq_cke_map[] = { 3, 3, 4, 4, 5, 6, 6, 7 }; + cke = frq_cke_map[get_FRQ(tCK, 133) - 3]; + } + + return cke; } -static u8 get_XPDLL(u32 tCK) +static u8 get_XPDLL(u32 tCK, u8 base_freq) { - /* Get XPDLL based on MCU frequency using the following rule: - * _____________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | - */ - static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26 }; - return frq_xpdll_map[get_FRQ(tCK) - 3]; + u8 xpdll; + + if (base_freq == 100) { + /* Get XPDLL based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * XPDLL : | 17 | 20 | 22 | 24 | 27 | 32 | + */ + + static const u8 frq_xpdll_map[] = { 17, 20, 22, 24, 27, 32 }; + xpdll = frq_xpdll_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get XPDLL based on MCU frequency using the following rule: + * _______________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * XPDLL : | 10 | 13 | 16 | 20 | 23 | 26 | 29 | 32 | + */ + static const u8 frq_xpdll_map[] = { 10, 13, 16, 20, 23, 26, 29, 32 }; + xpdll = frq_xpdll_map[get_FRQ(tCK, 133) - 3]; + } + + return xpdll; } -static u8 get_XP(u32 tCK) +static u8 get_XP(u32 tCK, u8 base_freq) { - /* Get XP based on MCU frequency using the following rule: - * _______________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * XP : | 3 | 4 | 4 | 5 | 6 | 7 | - */ - static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 }; - return frq_xp_map[get_FRQ(tCK) - 3]; + u8 xp; + + if (base_freq == 100) { + /* Get XP based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * XP : | 5 | 5 | 6 | 6 | 7 | 8 | + */ + + static const u8 frq_xp_map[] = { 5, 5, 6, 6, 7, 8 }; + xp = frq_xp_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get XP based on MCU frequency using the following rule: + * _______________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * XP : | 3 | 4 | 4 | 5 | 6 | 7 | 8 | 8 | + */ + static const u8 frq_xp_map[] = { 3, 4, 4, 5, 6, 7 , 8, 8 }; + xp = frq_xp_map[get_FRQ(tCK, 133) - 3]; + } + + return xp; } -static u8 get_AONPD(u32 tCK) +static u8 get_AONPD(u32 tCK, u8 base_freq) { - /* Get AONPD based on MCU frequency using the following rule: - * ________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | - */ - static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10 }; - return frq_aonpd_map[get_FRQ(tCK) - 3]; + u8 aonpd; + + if (base_freq == 100) { + /* Get AONPD based on MCU frequency using the following rule: + * _____________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * AONPD : | 6 | 8 | 8 | 9 | 10 | 11 | + */ + + static const u8 frq_aonpd_map[] = { 6, 8, 8, 9, 10, 11 }; + aonpd = frq_aonpd_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get AONPD based on MCU frequency using the following rule: + * _______________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * AONPD : | 4 | 5 | 6 | 8 | 8 | 10 | 11 | 12 | + */ + static const u8 frq_aonpd_map[] = { 4, 5, 6, 8, 8, 10, 11, 12 }; + aonpd = frq_aonpd_map[get_FRQ(tCK, 133) - 3]; + } + + return aonpd; } -static u32 get_COMP2(u32 tCK) +static u32 get_COMP2(u32 tCK, u8 base_freq) { - /* Get COMP2 based on MCU frequency using the following rule: - * ___________________________________________________________ - * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | - * COMP : | D6BEDCC | CE7C34C | CA57A4C | C6369CC | C42514C | C21410C | - */ - static const u32 frq_comp2_map[] = { 0xD6BEDCC, 0xCE7C34C, 0xCA57A4C, - 0xC6369CC, 0xC42514C, 0xC21410C - }; - return frq_comp2_map[get_FRQ(tCK) - 3]; + u32 comp2; + + if (base_freq == 100) { + /* Get COMP2 based on MCU frequency using the following rule: + * ______________________________________________________________ + * FRQ : | 7 | 8 | 9 | 10 | 11 | 12 | + * COMP : | CA8C264 | C6671E4 | C6671E4 | C446964 | C235924 | C235924 | + */ + + static const u32 frq_comp2_map[] = { 0xCA8C264, 0xC6671E4, 0xC6671E4, 0xC446964, 0xC235924, 0xC235924 }; + comp2 = frq_comp2_map[get_FRQ(tCK, 100) - 7]; + } else { + /* Get COMP2 based on MCU frequency using the following rule: + * ________________________________________________________________________________ + * FRQ : | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | + * COMP : | D6FF5E4 | CEBDB64 | CA8C264 | C6671E4 | C446964 | C235924 | C235924 | C235924 | + */ + static const u32 frq_comp2_map[] = { 0xD6FF5E4, 0xCEBDB64, 0xCA8C264, + 0xC6671E4, 0xC446964, 0xC235924, 0xC235924, 0xC235924 + }; + comp2 = frq_comp2_map[get_FRQ(tCK, 133) - 3]; + } + + return comp2; } static void dram_timing(ramctr_timing * ctrl) @@ -268,22 +417,27 @@ static void dram_timing(ramctr_timing * ctrl) ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); - ctrl->tREFI = get_REFI(ctrl->tCK); - ctrl->tMOD = get_MOD(ctrl->tCK); - ctrl->tXSOffset = get_XSOffset(ctrl->tCK); - ctrl->tWLO = get_WLO(ctrl->tCK); - ctrl->tCKE = get_CKE(ctrl->tCK); - ctrl->tXPDLL = get_XPDLL(ctrl->tCK); - ctrl->tXP = get_XP(ctrl->tCK); - ctrl->tAONPD = get_AONPD(ctrl->tCK); + ctrl->tREFI = get_REFI(ctrl->tCK, ctrl->base_freq); + ctrl->tMOD = get_MOD(ctrl->tCK, ctrl->base_freq); + ctrl->tXSOffset = get_XSOffset(ctrl->tCK, ctrl->base_freq); + ctrl->tWLO = get_WLO(ctrl->tCK, ctrl->base_freq); + ctrl->tCKE = get_CKE(ctrl->tCK, ctrl->base_freq); + ctrl->tXPDLL = get_XPDLL(ctrl->tCK, ctrl->base_freq); + ctrl->tXP = get_XP(ctrl->tCK, ctrl->base_freq); + ctrl->tAONPD = get_AONPD(ctrl->tCK, ctrl->base_freq); } static void dram_freq(ramctr_timing * ctrl) { if (ctrl->tCK > TCK_400MHZ) { - printk (BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). Increasing to 400 MHz as last resort"); + printk (BIOS_ERR, "DRAM frequency is under lowest supported " + "frequency (400 MHz). Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } + + /* TODO: implement 100Mhz refclock */ + ctrl->base_freq = 133; + while (1) { u8 val2; u32 reg1 = 0; @@ -307,7 +461,7 @@ static void dram_freq(ramctr_timing * ctrl) } /* Frequency multiplier. */ - u32 FRQ = get_FRQ(ctrl->tCK); + u32 FRQ = get_FRQ(ctrl->tCK, ctrl->base_freq); /* The PLL will never lock if the required frequency is * already set. Exit early to prevent a system hang. @@ -373,7 +527,7 @@ static void dram_ioregs(ramctr_timing * ctrl) printram("done\n"); // Set comp2 - comp2 = get_COMP2(ctrl->tCK); + comp2 = get_COMP2(ctrl->tCK, ctrl->base_freq); MCHBAR32(0x3714) = comp2; printram("COMP2 done\n"); @@ -398,7 +552,8 @@ int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, { int err; - printk(BIOS_DEBUG, "Starting RAM training (%d).\n", fast_boot); + printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", + fast_boot); if (!fast_boot) { /* Find fastest common supported parameters */ diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index 305e95a..fa83614 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -281,7 +281,8 @@ static void dram_timing(ramctr_timing * ctrl) static void dram_freq(ramctr_timing * ctrl) { if (ctrl->tCK > TCK_400MHZ) { - printk (BIOS_ERR, "DRAM frequency is under lowest supported frequency (400 MHz). Increasing to 400 MHz as last resort"); + printk (BIOS_ERR, "DRAM frequency is under lowest supported " + "frequency (400 MHz). Increasing to 400 MHz as last resort"); ctrl->tCK = TCK_400MHZ; } while (1) { @@ -398,7 +399,8 @@ int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, { int err; - printk(BIOS_DEBUG, "Starting RAM training (%d).\n", fast_boot); + printk(BIOS_DEBUG, "Starting SandyBridge RAM training (%d).\n", + fast_boot); if (!fast_boot) { /* Find fastest common supported parameters */

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New patch to review for coreboot: common Ite EC driver: Enable PWM smoothing via devicetree
by Arthur Heymans 26 Nov '16

26 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17614 -gerrit commit 5fc163831c6bd27d4edf47ee05a265b7f6643f99 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Nov 26 14:43:18 2016 +0100 common Ite EC driver: Enable PWM smoothing via devicetree The devicetree parameter already existed without being used in the code. Change-Id: I99dd8bc7a9b2f3509a115a130062d462a62e33fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/superio/ite/common/env_ctrl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 4ce6ccc..b3312e6 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -152,6 +152,8 @@ static void fan_smartconfig(const u16 base, const u8 fan, pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + if (conf->smoothing) + pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan), conf->tmp_off);

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Patch set updated for coreboot: nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation
by Nico Huber 26 Nov '16

26 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17612 -gerrit commit 650fe5db27a6bb32c03a42f9c19fb381a184d671 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Nov 26 02:03:25 2016 +0100 nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation Fix-up for 696abfc nb/intel/x4x: Fix and deflate `dimm_config` in raminit It didn't fix the channel-number shifting issue as intended. Change-Id: I2784b0cb655bfe823bf5fa48b722623dfca1ddc3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/x4x/raminit.c | 3 ++- src/northbridge/intel/x4x/x4x.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 0867c31..122cab5 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -153,7 +153,8 @@ static void sdram_read_spds(struct sysinfo *s) else die("Dual-rank x16 not supported\n"); } - s->dimm_config[chan] |= dimm_config << (i - chan) * 2; + s->dimm_config[chan] |= + dimm_config << (i % DIMMS_PER_CHANNEL) * 2; } printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index b349369..e4eb8dd 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -144,6 +144,7 @@ #define TOTAL_CHANNELS 2 #define TOTAL_DIMMS 4 +#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) #define RAW_CARD_UNPOPULATED 0xff #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) @@ -162,7 +163,7 @@ #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) #define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ - for (idx = (ch); idx < (ch) + 2; ++idx) + for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) #define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED))

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New patch to review for coreboot: mb/gigabyte/ga-945gcm-s2l: Configure SuperIO EC
by Arthur Heymans 26 Nov '16

26 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17613 -gerrit commit 90d4b132dc53878f21c808bb2bc731628c845e43 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Nov 26 12:44:09 2016 +0100 mb/gigabyte/ga-945gcm-s2l: Configure SuperIO EC Change-Id: Id7c2b656f500c14f39d4492667ea461b9ca353b0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index a993848..655065a 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -108,6 +108,31 @@ chip northbridge/intel/i945 device pci 1f.0 on # LPC bridge ioapic_irq 2 INTA 0x10 chip superio/ite/it8718f # Super I/O + register "TMPIN1" = "THERMAL_RESISTOR" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_DIODE" + register "ec.vin_mask" = "VIN_ALL" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "30" + register "FAN1.smart.tmp_start" = "35" + register "FAN1.smart.tmp_full" = "75" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10" + + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "30" + register "FAN2.smart.tmp_start" = "35" + register "FAN2.smart.tmp_full" = "75" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10" + device pnp 2e.0 off end # Floppy device pnp 2e.1 on # COM1 io 0x60 = 0x3f8

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Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Tie in configuration for SuperIO EC
by Arthur Heymans 26 Nov '16

26 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17602 -gerrit commit ef3ed63d479617ea1259b4502bd5f605257500ea Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Nov 25 22:10:19 2016 +1100 mb/gigabyte/ga-g41m-es2l: Tie in configuration for SuperIO EC Change-Id: Ifba821a7e355a0d6689f21c7f307e3901903a3fd Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index bd80742..60004d2 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -82,6 +82,31 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.0 on # ISA bridge subsystemid 0x1458 0x5001 chip superio/ite/it8718f # Super I/O + register "TMPIN1" = "THERMAL_RESISTOR" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_DIODE" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10" + + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10" + device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6

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Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Tie in configuration for SuperIO EC
by Damien Zammit 26 Nov '16

26 Nov '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17602 -gerrit commit 42400585725fa716430772a42d845eb0a77b05cd Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Nov 25 22:10:19 2016 +1100 mb/gigabyte/ga-g41m-es2l: Tie in configuration for SuperIO EC Change-Id: Ifba821a7e355a0d6689f21c7f307e3901903a3fd Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index bd80742..da5686a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -82,6 +82,31 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.0 on # ISA bridge subsystemid 0x1458 0x5001 chip superio/ite/it8718f # Super I/O + register "TMPIN1" = "THERMAL_RESISTOR" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_DIODE" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10" + + register "FAN3.mode" = "FAN_SMART_AUTOMATIC" + register "FAN3.smart.tmpin" = "3" + register "FAN3.smart.tmp_off" = "25" + register "FAN3.smart.tmp_start" = "30" + register "FAN3.smart.tmp_full" = "65" + register "FAN3.smart.tmp_delta" = "3" + register "FAN3.smart.smoothing" = "1" + register "FAN3.smart.pwm_start" = "0" + register "FAN3.smart.slope" = "10" + device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6

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coreboot-gerrit November 2016