coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/intel/gm45: Fix panel-power-sequence clock divisor
by Nico Huber 27 Nov '16

27 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17619 -gerrit commit 9bae887904ffd7cfce885e53b02cdb1ef014c9a7 Author: Nico Huber <nico.h(a)gmx.de> Date: Sun Nov 27 14:43:12 2016 +0100 nb/intel/gm45: Fix panel-power-sequence clock divisor We kept this value at it's default on the native graphics init path. Maybe the Video BIOS path, too, I don't know if the VBIOS sets it. The panel power sequencer uses the core display clock (CDCLK). It's based on the HPLLVCO and a frequency selection we made during raminit. The value written is the (actual divisor/2)-1 for a 100us timer. v2: Fix unaligned mmio access inherited from Linux. v3: Use MCHBAR8() instead. Also, the unaligned access might have worked after all. Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/gm45/gm45.h | 2 ++ src/northbridge/intel/gm45/gma.c | 22 ++++++++++++++++++++-- src/northbridge/intel/gm45/raminit.c | 2 +- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ae1863b..b9d2cb7 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -260,6 +260,8 @@ enum { #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define HPLLVCO_MCHBAR 0x0c0f + #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ #define PMSTS_WARM_RESET (1 << 1) #define PMSTS_BOTH_SELFREFRESH (1 << 0) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..3e9f508 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -611,6 +611,24 @@ static u8 vga_connected(u8 *mmio) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + const u16 cdclk_sel = + pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { + case VCO_2666: + case VCO_4000: + case VCO_5333: + return cdclk_sel ? 333333333 : 222222222; + case VCO_3200: + return cdclk_sel ? 320000000 : 228571429; + default: + printk(BIOS_WARNING, + "Unknown VCO frequency, using default cdclk.\n"); + return 222222222; + } +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -635,8 +653,8 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(PP_DIVISOR); - reg32 &= ~0x1f; + reg32 = (get_cdclk(dev) / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PP_DIVISOR, reg32); } diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index daddbab..0435cdd 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -749,7 +749,7 @@ static void set_system_memory_frequency(const timings_t *const timings) int raminit_read_vco_index(void) { - switch (MCHBAR8(0x0c0f) & 0x7) { + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: return 0; case VCO_3200:

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Patch set updated for coreboot: nb/intel/gm45: Fix panel-power-sequence clock divisor
by Nico Huber 27 Nov '16

27 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17619 -gerrit commit 2ef255ffdfc44d844353613c2e1ad0f253c8df6d Author: Nico Huber <nico.h(a)gmx.de> Date: Sun Nov 27 14:43:12 2016 +0100 nb/intel/gm45: Fix panel-power-sequence clock divisor We kept this value at it's default on the native graphics init path. Maybe the Video BIOS path, too, I don't know if the VBIOS sets it. The panel power sequencer uses the core display clock (CDCLK). It's based on the HPLLVCO and a frequency selection we made during raminit. The value written is the (actual divisor/2)-1 for a 100us timer. v2: Fix unaligned mmio access inherited from Linux. Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/gm45/gm45.h | 2 ++ src/northbridge/intel/gm45/gma.c | 22 ++++++++++++++++++++-- src/northbridge/intel/gm45/raminit.c | 2 +- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ae1863b..b9d2cb7 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -260,6 +260,8 @@ enum { #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define HPLLVCO_MCHBAR 0x0c0f + #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ #define PMSTS_WARM_RESET (1 << 1) #define PMSTS_BOTH_SELFREFRESH (1 << 0) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..07c7156 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -611,6 +611,24 @@ static u8 vga_connected(u8 *mmio) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + const u16 cdclk_sel = + pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + switch (gtt_read((MCHBAR_MIRROR_BASE + HPLLVCO_MCHBAR) & ~3) & 0x7) { + case VCO_2666: + case VCO_4000: + case VCO_5333: + return cdclk_sel ? 333333333 : 222222222; + case VCO_3200: + return cdclk_sel ? 320000000 : 228571429; + default: + printk(BIOS_WARNING, + "Unknown VCO frequency, using default cdclk.\n"); + return 222222222; + } +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -635,8 +653,8 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(PP_DIVISOR); - reg32 &= ~0x1f; + reg32 = (get_cdclk(dev) / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PP_DIVISOR, reg32); } diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index daddbab..0435cdd 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -749,7 +749,7 @@ static void set_system_memory_frequency(const timings_t *const timings) int raminit_read_vco_index(void) { - switch (MCHBAR8(0x0c0f) & 0x7) { + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: return 0; case VCO_3200:

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New patch to review for coreboot: nb/intel/gm45: Fix panel-power-sequence clock divisor
by Nico Huber 27 Nov '16

27 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17619 -gerrit commit fc900d5395ccd91213575f00046ac7c521289532 Author: Nico Huber <nico.h(a)gmx.de> Date: Sun Nov 27 14:43:12 2016 +0100 nb/intel/gm45: Fix panel-power-sequence clock divisor We kept this value at it's default on the native graphics init path. Maybe the Video BIOS path, too, I don't know if the VBIOS sets it. The panel power sequencer uses the core display clock (CDCLK). It's based on the HPLLVCO and a frequency selection we made during raminit. The value written is the (actual divisor/2)-1 for a 100us timer. Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/gm45/gm45.h | 2 ++ src/northbridge/intel/gm45/gma.c | 22 ++++++++++++++++++++-- src/northbridge/intel/gm45/raminit.c | 2 +- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ae1863b..b9d2cb7 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -260,6 +260,8 @@ enum { #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define HPLLVCO_MCHBAR 0x0c0f + #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ #define PMSTS_WARM_RESET (1 << 1) #define PMSTS_BOTH_SELFREFRESH (1 << 0) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..de57285 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -611,6 +611,24 @@ static u8 vga_connected(u8 *mmio) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + const u16 cdclk_sel = + pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + switch (gtt_read(MCHBAR_MIRROR_BASE + HPLLVCO_MCHBAR) & 0x7) { + case VCO_2666: + case VCO_4000: + case VCO_5333: + return cdclk_sel ? 333333333 : 222222222; + case VCO_3200: + return cdclk_sel ? 320000000 : 228571429; + default: + printk(BIOS_WARNING, + "Unknown VCO frequency, using default cdclk.\n"); + return 222222222; + } +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -635,8 +653,8 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { - reg32 = gtt_read(PP_DIVISOR); - reg32 &= ~0x1f; + reg32 = (get_cdclk(dev) / 20000 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PP_DIVISOR, reg32); } diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index daddbab..0435cdd 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -749,7 +749,7 @@ static void set_system_memory_frequency(const timings_t *const timings) int raminit_read_vco_index(void) { - switch (MCHBAR8(0x0c0f) & 0x7) { + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: return 0; case VCO_3200:

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Patch set updated for coreboot: nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation
by Nico Huber 27 Nov '16

27 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17612 -gerrit commit e4faf41486773533cba47447d0db511748a8df04 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Nov 26 02:03:25 2016 +0100 nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation Fix-up for 696abfc nb/intel/x4x: Fix and deflate `dimm_config` in raminit It didn't fix the channel-number shifting issue as intended. The channel index is either 0 or 1. DIMMs are counted from 0 to 3 where 0..1 covers channel 0, and 2..3 covers channel 1. Since we have two DIMMs per channel, we have to multiply the channel index by 2 (or shift it left by 1) to get the index of the first DIMM in the channel. Finally, to get the offset of a DIMM in the channel we take its index modulo 2 (again, the number of DIMMs per channel). Change-Id: I2784b0cb655bfe823bf5fa48b722623dfca1ddc3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/x4x/raminit.c | 3 ++- src/northbridge/intel/x4x/x4x.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 0867c31..122cab5 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -153,7 +153,8 @@ static void sdram_read_spds(struct sysinfo *s) else die("Dual-rank x16 not supported\n"); } - s->dimm_config[chan] |= dimm_config << (i - chan) * 2; + s->dimm_config[chan] |= + dimm_config << (i % DIMMS_PER_CHANNEL) * 2; } printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index b349369..e4eb8dd 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -144,6 +144,7 @@ #define TOTAL_CHANNELS 2 #define TOTAL_DIMMS 4 +#define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS) #define RAW_CARD_UNPOPULATED 0xff #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) @@ -162,7 +163,7 @@ #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) #define FOR_EACH_DIMM_IN_CHANNEL(ch, idx) \ - for (idx = (ch); idx < (ch) + 2; ++idx) + for (idx = (ch) << 1; idx < ((ch) << 1) + DIMMS_PER_CHANNEL; ++idx) #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) #define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED))

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New patch to review for coreboot: mainboard/google/snappy: Add digitizer device to devicetree
by Wisley Chen 27 Nov '16

27 Nov '16

Wisley Chen (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17618 -gerrit commit b2984e161129ffd03244bd975c9318449f34409d Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Sun Nov 27 16:31:22 2016 +0800 mainboard/google/snappy: Add digitizer device to devicetree BUG=chrome-os-partner:59034 BRANCH=none TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ib99ae5357274ad0824d0989888dfddcb32ace7e2 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- src/mainboard/google/reef/variants/snappy/devicetree.cb | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 00df9bd..b024682 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -155,7 +155,18 @@ chip soc/intel/apollolake device i2c 15 on end end end # - I2C 4 - device pci 17.1 on end # - I2C 5 + device pci 17.1 on + chip drivers/i2c/wacom + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_DT_DESC, + .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 5 device pci 17.2 on end # - I2C 6 device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0

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Patch set updated for coreboot: nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency
by Arthur Heymans 27 Nov '16

27 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17597 -gerrit commit 9966815b14269e03f8ab5a2a02720bc1fd0bdc07 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Nov 24 13:23:05 2016 +0100 nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency This allows to set the backlight PWM frequency and the duty cycle in the devicetree instead of using a plain BLC_PWM_CTL value. The previous default PWM frequency was 1006Hz but is now 1000Hz for simplicity. 1000Hz is a good default since it typically works well on LED backlit displays. A LED backlit display with a too slow PWM causes highly annoying flicker, assuming the PWM directly drives the backlight. CCFL displays want a lower pwm frequency in the 50-200Hz range. Driving a CCFL panel with a too high PWM frequency causes the IC to misbehave: unevenly lit backlight and/or high frequency tone. Since driving a LED backlit display too slow is worse than driving a CCFL backlit display too fast, a fast default is kept. Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/chip.h | 2 ++ src/northbridge/intel/gm45/gma.c | 35 ++++++++++++++++++++++++++++++++--- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 836d6bb..2307d53 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,6 +26,8 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; + u32 pwm_freq; + u32 duty_cycle; /* * Maximum PCI mmio size in MiB. diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..054bf05 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -611,6 +611,30 @@ static u8 vga_connected(u8 *mmio) return 1; } +/* + * In principle the display core clock is + * (PP_DIVISOR[31:16] + 1) * 2 / 100 * MHz. + * Since PP_DIVISOR[31:16] is not touched it will be at its default value + * of 0x270f, hence the default display core clock is 200MHz. + * This is done in order to avoid potential overflows. + */ + +#define DEFAULT_CORE_CLOCK 200000000 + +static u32 freq_to_blc_pwm_ctl(u16 pwm_freq, u16 duty_perc) +{ + u32 blc_mod; + + blc_mod = DEFAULT_CORE_CLOCK / (128 * pwm_freq); + + if (duty_perc <= 100) + return (blc_mod << 16) | (blc_mod * duty_perc / 100); + else + return (blc_mod << 16) | blc_mod; +} + +#define DEFAULT_PWM_FREQ 1000 + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -643,10 +667,15 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); + reg32 = 100; + if (conf->duty_cycle != 0) + reg32 = conf->duty_cycle; + if (conf->pwm_freq == 0) + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(DEFAULT_PWM_FREQ, + reg32)); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(conf->pwm_freq, + reg32)); } static void gma_func0_init(struct device *dev)

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New patch to review for coreboot: mb/ga-945gcm-s2l: Fix resume from suspend
by Arthur Heymans 26 Nov '16

26 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17617 -gerrit commit dbee353963357a6fb9914c9370ef6bac35de4141 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Nov 26 16:46:56 2016 +0100 mb/ga-945gcm-s2l: Fix resume from suspend High bios is still corrupted after suspend, i.e. it's not possible to use cbmem, or nvramtool after suspend. Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index b41becc..db16137 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_ITE_IT8718F select HAVE_OPTION_TABLE

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New patch to review for coreboot: [WIP]nb/intel/sandybridge/raminit: Fix odt stretch
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17616 -gerrit commit 3afe5ea39df258ee20a4f30ac136a4cba8ae574a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Nov 26 11:37:45 2016 +0100 [WIP]nb/intel/sandybridge/raminit: Fix odt stretch Move odt stretch into own function. Apply workaround on SandyBridge C-stepping CPU only. Apply odt stretch on all other CPU types. Don't depend on empty DIMM detection, as in case one slot is empty ref_card_offset is zero. Based on intel MRC code. Tested on Lenvovo T420. Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 90 +++++++++------------- 1 file changed, 36 insertions(+), 54 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 1ecf5db..b17d420 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -188,10 +188,40 @@ void dram_xover(ramctr_timing * ctrl) } } -void dram_timing_regs(ramctr_timing * ctrl) +static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - u32 reg, addr, val32, cpu, stretch; struct cpuid_result cpures; + u32 reg, addr, cpu, stretch; + + /* ODT stretch: Delay ODT signal by stretch value. + * Useful for multi DIMM setups on the same channel. */ + cpures = cpuid(1); + cpu = cpures.eax; + if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { + stretch = ctrl->ref_card_offset[channel]; + if (stretch == 2) + stretch = 3; + addr = 0x400 * channel + 0x401c; + reg = MCHBAR32(addr) & 0xffffc3ff; + reg |= (stretch << 12); + reg |= (stretch << 10); + MCHBAR32(addr) = reg; + printram("OTHP Workaround [%x] = %x\n", addr, reg); + } else { + stretch = ctrl->ref_card_offset[channel]; + // OTHP + addr = 0x400 * channel + 0x400c; + reg = MCHBAR32(addr) & 0xfff0ffff; + reg |= (stretch << 16); + reg |= (stretch << 18); + MCHBAR32(addr) = reg; + printram("OTHP [%x] = %x\n", addr, reg); + } +} + +void dram_timing_regs(ramctr_timing *ctrl) +{ + u32 reg, addr, val32; int channel; FOR_ALL_CHANNELS { @@ -231,52 +261,7 @@ void dram_timing_regs(ramctr_timing * ctrl) MCHBAR32(addr) |= 0x00020000; - // ODT stretch - reg = 0; - - cpures = cpuid(1); - cpu = cpures.eax; - if (IS_IVY_CPU(cpu) - || (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) { - stretch = 2; - addr = 0x400 * channel + 0x400c; - printram("ODT stretch [%x] = %x\n", - 0x400 * channel + 0x400c, reg); - reg = MCHBAR32(addr); - - if (((ctrl->rankmap[channel] & 3) == 0) - || (ctrl->rankmap[channel] & 0xc) == 0) { - - // Rank 0 - operate on rank 2 - reg = (reg & ~0xc0000) | (stretch << 18); - - // Rank 2 - operate on rank 0 - reg = (reg & ~0x30000) | (stretch << 16); - - printram("ODT stretch [%x] = %x\n", addr, reg); - MCHBAR32(addr) = reg; - } - - } else if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { - stretch = 3; - addr = 0x400 * channel + 0x401c; - reg = MCHBAR32(addr); - - if (((ctrl->rankmap[channel] & 3) == 0) - || (ctrl->rankmap[channel] & 0xc) == 0) { - - // Rank 0 - operate on rank 2 - reg = (reg & ~0x3000) | (stretch << 12); - - // Rank 2 - operate on rank 0 - reg = (reg & ~0xc00) | (stretch << 10); - - printram("ODT stretch [%x] = %x\n", addr, reg); - MCHBAR32(addr) = reg; - } - } else { - stretch = 0; - } + dram_odt_stretch(ctrl, channel); // REFI reg = 0; @@ -3154,7 +3139,7 @@ void prepare_training(ramctr_timing * ctrl) void set_4008c(ramctr_timing * ctrl) { int channel, slotrank; - u32 reg; + FOR_ALL_POPULATED_CHANNELS { u32 b20, b4_8_12; int min_320c = 10000; @@ -3175,11 +3160,8 @@ void set_4008c(ramctr_timing * ctrl) else b4_8_12 = 0x2220; - reg = read32(DEFAULT_MCHBAR + 0x400c + (channel << 10)); - write32(DEFAULT_MCHBAR + 0x400c + (channel << 10), - (reg & 0xFFF0FFFF) - | (ctrl->ref_card_offset[channel] << 16) - | (ctrl->ref_card_offset[channel] << 18)); + dram_odt_stretch(ctrl, channel); + write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10), 0x0a000000 | (b20 << 20)

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New patch to review for coreboot: nb/intel/sandybridge/raminit: Always run quick_ram_check
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17615 -gerrit commit 55b4f413da0c87d065255c074e45c5db8c81cf6d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Nov 26 10:11:14 2016 +0100 nb/intel/sandybridge/raminit: Always run quick_ram_check quick_ram_check doesn't change contents of memory. Run it in S3 resume, too. Tested on Lenovo T420. Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 956234b..7560b7e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -425,8 +425,8 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume) /* Zone config */ dram_zones(&ctrl, 0); - if (!fast_boot) - quick_ram_check(); + /* Non intrusive, fast ram check */ + quick_ram_check(); intel_early_me_status(); intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: Reduce log level
by Patrick Rudolph 26 Nov '16

26 Nov '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17611 -gerrit commit dcf44de20d59566d2280aa150ea1de8ebb683da4 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Fri Nov 25 16:36:52 2016 +0100 nb/intel/sandybridge/raminit: Reduce log level Remove verbose logging from loops. Print detailed summary at end of loop instead. Use the same scheme already present in some functions. Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_common.c | 32 ++++++---------------- 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6b352c2..1ecf5db 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1222,9 +1222,6 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, FOR_ALL_LANES { statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); - printram("Astat: %d, %d, %d: %x, %x\n", - channel, slotrank, lane, timA, - statistics[lane][timA]); } } FOR_ALL_LANES { @@ -1233,10 +1230,8 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - printram("Aend: %d, %d, %d: %x\n", channel, slotrank, - lane, upperA[lane]); + printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, lane, rn.start, rn.middle, rn.end); } } @@ -1613,9 +1608,6 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) statistics[lane][timC] = read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel); - printram("Cstat: %d, %d, %d, %x, %x\n", - channel, slotrank, lane, timC, - statistics[lane][timC]); } } FOR_ALL_LANES { @@ -1627,8 +1619,8 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) channel, slotrank, lane); return MAKE_ERR; } - printram("Cval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timC); + printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1846,9 +1838,6 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); - printram("Bstat: %d, %d, %d: %x, %x\n", - channel, slotrank, lane, timB, - statistics[lane][timB]); } } FOR_ALL_LANES { @@ -1872,8 +1861,8 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) channel, slotrank, lane); return MAKE_ERR; } - printram("Bval: %d, %d, %d: %x\n", channel, slotrank, - lane, ctrl->timings[channel][slotrank].lanes[lane].timB); + printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -2217,7 +2206,6 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank] = saved_rt; - printram("3lanes: %x\n", lanes_ok); return lanes_ok != ((1 << NUM_LANES) - 1); } @@ -2354,9 +2342,6 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) FOR_ALL_POPULATED_RANKS { stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); - printram("3stat: %d, %d, %d: %x\n", - channel, slotrank, c320c, - stat[slotrank][c320c + 127]); } } FOR_ALL_POPULATED_RANKS { @@ -2364,9 +2349,8 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) get_longest_zero_run(stat[slotrank], 255); ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; - printram("3val %d, %d: %d\n", channel, - slotrank, - ctrl->timings[channel][slotrank].val_320c); + printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", + channel, slotrank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { FOR_ALL_POPULATED_RANKS { ctrl->timings[channel][slotrank] =

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coreboot-gerrit November 2016