coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch merged into coreboot/master: sb/broadcom/bcm5785/reset.c: Use tab for indents
by gerrit＠coreboot.org 28 Nov '16

28 Nov '16

the following patch was just integrated into master: commit f100700a149d1a1d4c87f63e50b8f4d89a8c2650 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Nov 23 19:00:14 2016 +0100 sb/broadcom/bcm5785/reset.c: Use tab for indents Change-Id: If4350da1c9a7af5228be01a063486433860781e0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17583 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17583 for details. -gerrit

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Patch merged into coreboot/master: sb/ricoh/rl5c476/rl5c476.c: Use tab for indents
by gerrit＠coreboot.org 28 Nov '16

28 Nov '16

the following patch was just integrated into master: commit 2220f0d7c79b2f22ccdc93e8fa643e8928c1ff3c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Nov 23 18:54:34 2016 +0100 sb/ricoh/rl5c476/rl5c476.c: Use tab for indents Change-Id: I3967d1ff0623037efa66927843e0c47f408832d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17582 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17582 for details. -gerrit

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Patch merged into coreboot/master: util/crossgcc: fix using -D
by gerrit＠coreboot.org 28 Nov '16

28 Nov '16

the following patch was just integrated into master: commit 1b593e5ad76bb66298c6f39b2cfb6fdf1f784c38 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Nov 25 15:27:41 2016 +0100 util/crossgcc: fix using -D Otherwise errors similar to "touch: cannot touch '${TARGETDIR}/.GMP.6.1.0.success': No such file or directory" might occur. Change-Id: I4f24c93a25b7d567d3ce14a0415d20fd0778c9c8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/17603 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17603 for details. -gerrit

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Patch set updated for coreboot: soc/broadwell/igd.c: limit max CD clock to 450MHz
by Matt DeVillier 28 Nov '16

28 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17456 -gerrit commit b6fb9fe2640f2d9f7e32b0124adfeee20f3aef93 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Wed Nov 16 23:37:43 2016 -0600 soc/broadwell/igd.c: limit max CD clock to 450MHz limit the max CD clock frequency to 450MHz for ULT SoCs, as higher values result in HDMI audio speedup, failure to pass HD audio bitstreams, and other related issues under Windows (8/8.1/10). The Linux i915 driver renegotiates the cdclk to 337.5Mhz for Broadwell ULT regardless, so isn't affected by the value set in firmware. Change-Id: Ibf253f7ab3ba340b4ab6fd97225155ffb112d74d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/soc/intel/broadwell/igd.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index ccb1e93..db4f126 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -407,24 +407,18 @@ static void igd_cdclk_init_broadwell(struct device *dev) gtt_write(0x138124, 0x80000018); /* Poll GT driver mailbox for run/busy clear */ - if (!gtt_poll(0x138124, (1 << 31), (0 << 31))) - cdclk = GT_CDCLK_450; + gtt_poll(0x138124, (1 << 31), (0 << 31)); if (gtt_read(0x42014) & 0x1000000) { /* If CD clock is fixed then set to 450MHz */ cdclk = GT_CDCLK_450; } else { - /* Program CD clock to highest supported freq */ + /* Limit ULT to 450Mhz, as Windows drivers can't handle higher + speed, and Linux drivers will negotiate down to 337.5Mhz anyway */ if (cpu_is_ult()) - cdclk = GT_CDCLK_540; - else - cdclk = GT_CDCLK_675; + cdclk = GT_CDCLK_450; } - /* CD clock frequency 675MHz not supported on ULT */ - if (cpu_is_ult() && cdclk == GT_CDCLK_675) - cdclk = GT_CDCLK_540; - /* Set variables based on CD Clock setting */ switch (cdclk) { case GT_CDCLK_337:

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Patch set updated for coreboot: nb/x4x: Fix raminit reset
by Arthur Heymans 27 Nov '16

27 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17624 -gerrit commit 077cb9859bfd6ec79d8bee8da4c85c57d382f0e8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Nov 27 22:29:01 2016 +0100 nb/x4x: Fix raminit reset All the other Intel raminits reset when bit7 of pmcon2 is set to 1. NOT TESTED. Change-Id: Ic014533aef7e75742ff7685020d9777dbdd1369f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..9638ad7 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -260,8 +260,9 @@ static void checkreset_ddr2(struct sysinfo *s) u8 reset = 0; pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + /* Do we want to reset at S4-assertion-width violation (1 << 2)? */ + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1;

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New patch to review for coreboot: nb/x4x: Fix raminit reboot
by Arthur Heymans 27 Nov '16

27 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17624 -gerrit commit 12d92e3f469fb1217350bbd4373ddc636d77c7dd Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Nov 27 22:29:01 2016 +0100 nb/x4x: Fix raminit reboot All the other Intel raminits reboot when bit7 of pmcon2 is set to 1. NOT TESTED. Change-Id: Ic014533aef7e75742ff7685020d9777dbdd1369f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..9638ad7 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -260,8 +260,9 @@ static void checkreset_ddr2(struct sysinfo *s) u8 reset = 0; pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + /* Do we want to reset at S4-assertion-width violation (1 << 2)? */ + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1;

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New patch to review for coreboot: nb/intel/i945/gma: Declare count variable outside 'for' loop
by Paul Menzel 27 Nov '16

27 Nov '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17623 -gerrit commit 2150ab51f9e5ebd1f657e95ea3a11b7678c15be0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Nov 27 22:17:44 2016 +0100 nb/intel/i945/gma: Declare count variable outside 'for' loop Building an image for the Lenovo X60 on Debian 8.5 (jessie) with GCC 4.9.2, compilation fails with the error below. ``` $ gcc --version gcc (Debian 4.9.2-10) 4.9.2 […] $ make # lenovo/x60 with native graphics initialization […] CC ramstage/northbridge/intel/i945/gma.o src/northbridge/intel/i945/gma.c: In function 'probe_edid': src/northbridge/intel/i945/gma.c:570:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode for (int i = 0; i < 8; i++) { ^ src/northbridge/intel/i945/gma.c:570:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code Makefile:316: recipe for target 'build/ramstage/northbridge/intel/i945/gma.o' failed make: *** [build/ramstage/northbridge/intel/i945/gma.o] Error 1 ``` Fix this by declaring the count variable outside the 'for' loop. Change-Id: Icf69337ee46c86bafc4e1320fd99f8f8f5155bfe Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/gma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e3ff478..b9a37e4 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -563,11 +563,12 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, /* if vga is not connected it should have a correct header */ static int probe_edid(u8 *pmmio, u8 slave) { + int i; u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(pmmio + GMBUS0, slave, 0x50, vga_edid, 128); intel_gmbus_stop(pmmio + GMBUS0); - for (int i = 0; i < 8; i++) { + for (i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "No display connected on slave %d\n", slave);

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New patch to review for coreboot: Remove boards google/falco and google/peppy
by Matt DeVillier 27 Nov '16

27 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17622 -gerrit commit 0c9329a3469ff7d1d7ed70c6dbae5d024468ffd1 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sun Nov 27 02:21:07 2016 -0600 Remove boards google/falco and google/peppy No need for these boards to exist separately once included as variants under google/slippy Change-Id: I52a476ceaadf50487d6fe21e796d7844f946d8b3 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- .../google/falco/Elpida_EDJ4216EFBG.spd.hex | 17 -- .../google/falco/Hynix_HMT425S6AFR6A.spd.hex | 17 -- src/mainboard/google/falco/Kconfig | 61 ----- src/mainboard/google/falco/Kconfig.name | 2 - src/mainboard/google/falco/Makefile.inc | 49 ---- .../google/falco/Micron_4KTF25664HZ.spd.hex | 17 -- .../google/falco/Samsung_M471B5674QH0.spd.hex | 17 -- src/mainboard/google/falco/acpi/ec.asl | 20 -- .../google/falco/acpi/haswell_pci_irqs.asl | 82 ------- src/mainboard/google/falco/acpi/mainboard.asl | 139 ----------- src/mainboard/google/falco/acpi/platform.asl | 82 ------- src/mainboard/google/falco/acpi/superio.asl | 25 -- src/mainboard/google/falco/acpi/thermal.asl | 132 ---------- src/mainboard/google/falco/acpi_tables.c | 84 ------- src/mainboard/google/falco/board_info.txt | 7 - src/mainboard/google/falco/chromeos.c | 52 ---- src/mainboard/google/falco/chromeos.fmd | 38 --- src/mainboard/google/falco/cmos.layout | 110 --------- src/mainboard/google/falco/devicetree.cb | 122 --------- src/mainboard/google/falco/dsdt.asl | 61 ----- src/mainboard/google/falco/ec.c | 47 ---- src/mainboard/google/falco/ec.h | 57 ----- src/mainboard/google/falco/fadt.c | 152 ------------ src/mainboard/google/falco/gma.c | 246 ------------------- src/mainboard/google/falco/gpio.h | 120 --------- src/mainboard/google/falco/hda_verb.c | 97 -------- src/mainboard/google/falco/i915io.c | 125 ---------- src/mainboard/google/falco/mainboard.c | 97 -------- src/mainboard/google/falco/mainboard.h | 21 -- src/mainboard/google/falco/onboard.h | 36 --- src/mainboard/google/falco/romstage.c | 174 ------------- src/mainboard/google/falco/smihandler.c | 149 ----------- src/mainboard/google/falco/thermal.h | 33 --- .../google/peppy/Elpida_EDJ4216EFBG.spd.hex | 17 -- .../google/peppy/Hynix_HMT425S6AFR6A.spd.hex | 17 -- src/mainboard/google/peppy/Kconfig | 63 ----- src/mainboard/google/peppy/Kconfig.name | 2 - src/mainboard/google/peppy/Makefile.inc | 48 ---- .../google/peppy/Micron_4KTF25664HZ.spd.hex | 17 -- src/mainboard/google/peppy/acpi/ec.asl | 20 -- .../google/peppy/acpi/haswell_pci_irqs.asl | 82 ------- src/mainboard/google/peppy/acpi/mainboard.asl | 105 -------- src/mainboard/google/peppy/acpi/platform.asl | 82 ------- src/mainboard/google/peppy/acpi/superio.asl | 25 -- src/mainboard/google/peppy/acpi/thermal.asl | 174 ------------- src/mainboard/google/peppy/acpi_tables.c | 93 ------- src/mainboard/google/peppy/board_info.txt | 7 - src/mainboard/google/peppy/chromeos.c | 52 ---- src/mainboard/google/peppy/chromeos.fmd | 38 --- src/mainboard/google/peppy/cmos.layout | 110 --------- src/mainboard/google/peppy/devicetree.cb | 126 ---------- src/mainboard/google/peppy/dsdt.asl | 59 ----- src/mainboard/google/peppy/ec.c | 47 ---- src/mainboard/google/peppy/ec.h | 55 ----- src/mainboard/google/peppy/fadt.c | 152 ------------ src/mainboard/google/peppy/gma.c | 272 --------------------- src/mainboard/google/peppy/gpio.h | 120 --------- src/mainboard/google/peppy/hda_verb.c | 101 -------- src/mainboard/google/peppy/i915io.c | 139 ----------- src/mainboard/google/peppy/mainboard.c | 97 -------- src/mainboard/google/peppy/mainboard.h | 21 -- src/mainboard/google/peppy/onboard.h | 39 --- src/mainboard/google/peppy/romstage.c | 183 -------------- src/mainboard/google/peppy/smihandler.c | 146 ----------- src/mainboard/google/peppy/thermal.h | 34 --- 65 files changed, 5031 deletions(-) diff --git a/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex deleted file mode 100644 index eb41f0b..0000000 --- a/src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Elpida EDJ4216EFBG-GN-F -92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE -45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 -00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/falco/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/falco/Hynix_HMT425S6AFR6A.spd.hex deleted file mode 100644 index 7b09327..0000000 --- a/src/mainboard/google/falco/Hynix_HMT425S6AFR6A.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Hynix HMT425S6AFR6A-PBA -92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB -48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 -20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig deleted file mode 100644 index 14adcac..0000000 --- a/src/mainboard/google/falco/Kconfig +++ /dev/null @@ -1,61 +0,0 @@ -if BOARD_GOOGLE_FALCO - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_HASWELL - select NORTHBRIDGE_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT - select INTEL_LYNXPOINT_LP - select BOARD_ROMSIZE_KB_8192 - select EC_GOOGLE_CHROMEEC - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT - select INTEL_INT15 - -config CHROMEOS - select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC - select LID_SWITCH - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/falco - -config MAINBOARD_PART_NUMBER - string - default "Falco" - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config GBB_HWID - string - depends on CHROMEOS - default "X86 FALCO TEST 0289" -endif diff --git a/src/mainboard/google/falco/Kconfig.name b/src/mainboard/google/falco/Kconfig.name deleted file mode 100644 index 2cb5ad8..0000000 --- a/src/mainboard/google/falco/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_FALCO - bool "Falco" diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc deleted file mode 100644 index 34de87a..0000000 --- a/src/mainboard/google/falco/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c - -romstage-y += chromeos.c -ramstage-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000) -SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001) -SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID=010) -SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID=011) -SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID=100) -SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101) -SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110) -SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111) - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/falco/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/falco/Micron_4KTF25664HZ.spd.hex deleted file mode 100644 index cbe9e4f..0000000 --- a/src/mainboard/google/falco/Micron_4KTF25664HZ.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Micron 4KTF25664HZ-1G6E1 -92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 -34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 -31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex b/src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex deleted file mode 100644 index c2a23cd..0000000 --- a/src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Samsung M471B5674QH0-YK0 (K4B4G1646Q) -92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 11 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 -4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/falco/acpi/ec.asl b/src/mainboard/google/falco/acpi/ec.asl deleted file mode 100644 index bb42072..0000000 --- a/src/mainboard/google/falco/acpi/ec.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/falco/ec.h> - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl b/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9..0000000 --- a/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/falco/acpi/mainboard.asl b/src/mainboard/google/falco/acpi/mainboard.asl deleted file mode 100644 index 2fcee23..0000000 --- a/src/mainboard/google/falco/acpi/mainboard.asl +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/falco/onboard.h> - -Scope (\_SB) -{ - Device (LID0) - { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - } - - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } - - Device (TPAD) - { - Name (_ADR, 0x0) - Name (_UID, 1) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) - - Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - - VendorShort (ADDR) - { - BOARD_TRACKPAD_I2C_ADDR - } - }) - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) - } - } - } - - Device (TSCR) - { - Name (_ADR, 0x0) - Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) - - Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ - } - - VendorShort (ADDR) - { - BOARD_TOUCHSCREEN_I2C_ADDR - } - }) - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) - } - } - } -} - -Scope (\_SB.PCI0.I2C0) -{ - Device (CYPA) - { - Name (_HID, "CYPA0000") - Name (_DDN, "Cypress Touchpad") - Name (_UID, 1) - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - }) - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } -} diff --git a/src/mainboard/google/falco/acpi/platform.asl b/src/mainboard/google/falco/acpi/platform.asl deleted file mode 100644 index 1bd054d..0000000 --- a/src/mainboard/google/falco/acpi/platform.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) - Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) - } - - /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) - Notify (\_SB.LID0, 0x80) - } - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/falco/acpi/superio.asl b/src/mainboard/google/falco/acpi/superio.asl deleted file mode 100644 index 2c9412a..0000000 --- a/src/mainboard/google/falco/acpi/superio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/falco/ec.h> - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/falco/acpi/thermal.asl b/src/mainboard/google/falco/acpi/thermal.asl deleted file mode 100644 index 36b0e21..0000000 --- a/src/mainboard/google/falco/acpi/thermal.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -Scope (\_TZ) -{ - // Handler for throttle requests on this platform - // 0 = Stop throttling - // 1 = Start throttling - Method (THRT, 1, Serialized) - { - If (LEqual (Arg0, 0)) { - /* Disable Power Limit */ - \_SB.PCI0.MCHC.CTLD () - } Else { - /* Enable Power Limit */ - \_SB.PCI0.MCHC.CTLE (\F0PW) - } - } - - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - Method (TCHK, 0, Serialized) - { - // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) - - // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { - Return (CTOK(0)) - } - - // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { - Return (CTOK(0)) - } - - // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { - Return (CTOK(0)) - } - - // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { - Return (CTOK(0)) - } - - // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) - - // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) - Return (Local0) - } - - Method (_TMP, 0, Serialized) - { - // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) - - // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) - - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) - - // Wait 1 second for EC to re-poll - Sleep (1000) - - // Re-read temperature from EC - Store (TCHK (), Local0) - - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) - } - - Return (Local0) - } - } -} diff --git a/src/mainboard/google/falco/acpi_tables.c b/src/mainboard/google/falco/acpi_tables.c deleted file mode 100644 index 97b246f..0000000 --- a/src/mainboard/google/falco/acpi_tables.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h> - -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tmps = TEMPERATURE_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->f0pw = EC_THROTTLE_POWER_LIMIT; - gnvs->flvl = 1; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 1; - - -#if CONFIG_CHROMEOS - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/google/falco/board_info.txt b/src/mainboard/google/falco/board_info.txt deleted file mode 100644 index e56fe14..0000000 --- a/src/mainboard/google/falco/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: HP -Board name: Chromebook 14 -Category: laptop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c deleted file mode 100644 index 22ec074..0000000 --- a/src/mainboard/google/falco/chromeos.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {58, ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - return get_gpio(58); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/falco/chromeos.fmd b/src/mainboard/google/falco/chromeos.fmd deleted file mode 100644 index 0c05ce9..0000000 --- a/src/mainboard/google/falco/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x6f000 - COREBOOT(CBFS)@0x70000 0x180000 - } - } - } -} diff --git a/src/mainboard/google/falco/cmos.layout b/src/mainboard/google/falco/cmos.layout deleted file mode 100644 index b575e02..0000000 --- a/src/mainboard/google/falco/cmos.layout +++ /dev/null @@ -1,110 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb deleted file mode 100644 index 8cdb032..0000000 --- a/src/mainboard/google/falco/devicetree.cb +++ /dev/null @@ -1,122 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) - register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) - register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl deleted file mode 100644 index f4a4627..0000000 --- a/src/mainboard/google/falco/dsdt.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define ENABLE_TPM - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - // Mainboard specific - #include "acpi/mainboard.asl" - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> -} diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c deleted file mode 100644 index c011f33..0000000 --- a/src/mainboard/google/falco/ec.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void mainboard_ec_init(void) -{ - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/google/falco/ec.h b/src/mainboard/google/falco/ec.h deleted file mode 100644 index 2bd46e3..0000000 --- a/src/mainboard/google/falco/ec.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ -#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#endif diff --git a/src/mainboard/google/falco/fadt.c b/src/mainboard/google/falco/fadt.c deleted file mode 100644 index 2452ac2..0000000 --- a/src/mainboard/google/falco/fadt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/pch.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/falco/gma.c b/src/mainboard/google/falco/gma.c deleted file mode 100644 index c76c50e..0000000 --- a/src/mainboard/google/falco/gma.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <stdlib.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <delay.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <smbios.h> -#include <device/pci.h> -#include <ec/google/chromeec/ec.h> - -#include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <edid.h> -#include <drivers/intel/gma/i915.h> -#include <northbridge/intel/haswell/haswell.h> -#include "mainboard.h" - -/* - * Here is the rough outline of how we bring up the display: - * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD - * 2. Source determines video mode by reading DPCD receiver capability field - * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD - * 0000Dh). - * 3. Sink replies DPCD receiver capability field. - * 4. Source starts EDID read thru I2C-over-AUX. - * 5. Sink replies EDID thru I2C-over-AUX. - * 6. Source determines link configuration, such as MAX_LINK_RATE and - * MAX_LANE_COUNT. Source also determines which type of eDP Authentication - * method to use and writes DPCD link configuration field (DPCD 00100h to - * 0010Ah) including eDP configuration set (DPCD 0010Ah). - * 7. Source starts link training. Sink does clock recovery and equalization. - * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). - * 9. Sink replies DPCD link status field. If main link is not stable, Source - * repeats Step 7. - * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video - * parameters and recovers stream clock. - * 11. Source sends video data. - */ - -/* how many bytes do we need for the framebuffer? - * Well, this gets messy. To get an exact answer, we have - * to ask the panel, but we'd rather zero the memory - * and set up the gtt while the panel powers up. So, - * we take a reasonable guess, secure in the knowledge that the - * MRC has to overestimate the number of bytes used. - * 8 MiB is a very safe guess. There may be a better way later, but - * fact is, the initial framebuffer is only very temporary. And taking - * a little long is ok; this is done much faster than the AUX - * channel is ready for IO. - */ -#define FRAME_BUFFER_BYTES (8*MiB) -/* how many 4096-byte pages do we need for the framebuffer? - * There are hard ways to get this, and easy ways: - * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 - * on this chip (and in fact every Intel graphics chip we've seen). - */ -#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) - -static int i915_init_done = 0; - -/* fill the palette. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for(i = 0; i < 256; i++, color += 0x010101){ - gtt_write(_LGC_PALETTE_A + (i << 2),color); - } -} - -void mainboard_train_link(struct intel_dp *intel_dp) -{ - u8 read_val; - u8 link_status[DP_LINK_STATUS_SIZE]; - - gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); - gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011); - - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); - intel_dp_get_lane_count(intel_dp, &read_val); - intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); - intel_dp_get_link_status(intel_dp, link_status); - - gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); - - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); - intel_dp_get_link_status(intel_dp, link_status); - intel_dp_get_lane_align_status(intel_dp, &read_val); - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); -} - -#define TEST_GFX 0 - -#if TEST_GFX -static void test_gfx(struct intel_dp *dp) -{ - int i; - - /* This is a sanity test code which fills the screen with two bands -- - green and blue. It is very useful to ensure all the initializations - are made right. Thus, to be used only for testing, not otherwise - */ - for (i = 0; i < (dp->edid.va - 4); i++) { - u32 *l; - int j; - u32 tcolor = 0x0ff; - for (j = 0; j < (dp->edid.ha-4); j++) { - if (j == (dp->edid.ha/2)) { - tcolor = 0xff00; - } - l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); - memcpy(l,&tcolor,sizeof(tcolor)); - } - } -} -#else -static void test_gfx(struct intel_dp *dp) {} -#endif - - -void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) -{ - u32 ddi_pll_sel = 0; - - switch (intel_dp->link_bw) { - case DP_LINK_BW_1_62: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; - break; - case DP_LINK_BW_2_7: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; - break; - case DP_LINK_BW_5_4: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; - break; - default: - printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); - return; - } - - gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); -} - -int panel_lightup(struct intel_dp *dp, unsigned int init_fb) -{ - int i; - int edid_ok; - int pixels = FRAME_BUFFER_BYTES/64; - - void runio(struct intel_dp *dp); - - dp->gen = 8; // This is gen 8 which we believe is Haswell - dp->is_haswell = 1; - dp->DP = 0x2; - /* These values are used for training the link */ - dp->lane_count = 2; - dp->link_bw = DP_LINK_BW_2_7; - dp->pipe = PIPE_A; - dp->port = PORT_A; - dp->plane = PLANE_A; - dp->clock = 160000; - dp->pipe_bits_per_pixel = 32; - dp->type = INTEL_OUTPUT_EDP; - dp->output_reg = DP_A; - /* observed from YABEL. */ - dp->aux_clock_divider = 0xe1; - dp->precharge = 3; - - /* 1. Normal mode: Set the first page to zero and make - all GTT entries point to the same page - 2. Developer/Recovery mode: We do not zero out all - the pages pointed to by GTT in order to avoid wasting time */ - if (init_fb){ - set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096); - memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096); - } else { - set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0); - memset((void*)dp->graphics, 0, 4096); - } - - dp->address = 0x50; - - if ( !intel_dp_get_dpcd(dp) ) - goto fail; - - intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); - for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ - if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, - 0x50, &dp->rawedid[i]) < 0) - break; - dp->edidlen++; - } - - edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); - printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - - compute_display_params(dp); - - intel_ddi_set_pipe_settings(dp); - - runio(dp); - - palette(); - - pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; - printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); - - test_gfx(dp); - - set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); - i915_init_done = 1; - return i915_init_done; - -fail: - printk(BIOS_SPEW, "Graphics could not be started;"); - printk(BIOS_SPEW, "Returning.\n"); - return 0; -} diff --git a/src/mainboard/google/falco/gpio.h b/src/mainboard/google/falco/gpio.h deleted file mode 100644 index c35b81e..0000000 --- a/src/mainboard/google/falco/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H - -struct pch_lp_gpio_map; - -const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_UNUSED, /* 0: UNUSED */ - LP_GPIO_UNUSED, /* 1: UNUSED */ - LP_GPIO_UNUSED, /* 2: UNUSED */ - LP_GPIO_UNUSED, /* 3: UNUSED */ - LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ - LP_GPIO_INPUT, /* 9: RAM_ID1 */ - LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ - LP_GPIO_INPUT, /* 13: RAM_ID0 */ - LP_GPIO_INPUT, /* 14: EC_IN_RW */ - LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 16: UNUSED */ - LP_GPIO_UNUSED, /* 17: UNUSED */ - LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ - LP_GPIO_UNUSED, /* 20: UNUSED */ - LP_GPIO_UNUSED, /* 21: UNUSED */ - LP_GPIO_UNUSED, /* 22: UNUSED */ - LP_GPIO_UNUSED, /* 23: UNUSED */ - LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ - LP_GPIO_UNUSED, /* 26: UNUSED */ - LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_UNUSED, /* 28: UNUSED */ - LP_GPIO_UNUSED, /* 29: UNUSED */ - LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ - LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - LP_GPIO_UNUSED, /* 37: UNUSED */ - LP_GPIO_UNUSED, /* 38: UNUSED */ - LP_GPIO_UNUSED, /* 39: UNUSED */ - LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - LP_GPIO_UNUSED, /* 41: UNUSED */ - LP_GPIO_UNUSED, /* 42: UNUSED */ - LP_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - LP_GPIO_UNUSED, /* 44: UNUSED */ - LP_GPIO_UNUSED, /* 45: UNUSED */ - LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ - LP_GPIO_INPUT, /* 47: RAM_ID2 */ - LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_UNUSED, /* 49: UNUSED */ - LP_GPIO_UNUSED, /* 50: UNUSED */ - LP_GPIO_INPUT, /* 51: ALS_INT_L */ - LP_GPIO_INPUT, /* 52: SIM_DET */ - LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX (PIRQV) */ - LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX (PIRQW) */ - LP_GPIO_UNUSED, /* 55: UNUSED */ - LP_GPIO_UNUSED, /* 56: UNUSED */ - LP_GPIO_UNUSED, /* 57: UNUSED */ - LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_UNUSED, /* 61: UNUSED */ - LP_GPIO_UNUSED, /* 62: UNUSED */ - LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - LP_GPIO_UNUSED, /* 64: UNUSED */ - LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 67: UNUSED */ - LP_GPIO_UNUSED, /* 68: UNUSED */ - LP_GPIO_UNUSED, /* 69: UNUSED */ - LP_GPIO_UNUSED, /* 70: UNUSED */ - LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - LP_GPIO_UNUSED, /* 72: UNUSED */ - LP_GPIO_UNUSED, /* 73: UNUSED */ - LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - LP_GPIO_UNUSED, /* 76: UNUSED */ - LP_GPIO_UNUSED, /* 77: UNUSED */ - LP_GPIO_UNUSED, /* 78: UNUSED */ - LP_GPIO_UNUSED, /* 79: UNUSED */ - LP_GPIO_UNUSED, /* 80: UNUSED */ - LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - LP_GPIO_UNUSED, /* 83: UNUSED */ - LP_GPIO_UNUSED, /* 84: UNUSED */ - LP_GPIO_UNUSED, /* 85: UNUSED */ - LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 87: UNUSED */ - LP_GPIO_UNUSED, /* 88: UNUSED */ - LP_GPIO_UNUSED, /* 89: UNUSED */ - LP_GPIO_UNUSED, /* 90: UNUSED */ - LP_GPIO_UNUSED, /* 91: UNUSED */ - LP_GPIO_UNUSED, /* 92: UNUSED */ - LP_GPIO_UNUSED, /* 93: UNUSED */ - LP_GPIO_UNUSED, /* 94: UNUSED */ - LP_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/falco/hda_verb.c b/src/mainboard/google/falco/hda_verb.c deleted file mode 100644 index 56c6508..0000000 --- a/src/mainboard/google/falco/hda_verb.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 - 0x10ec0283, // Subsystem ID - 0x0000000d, // Number of jacks (NID entries) - - 0x0017ff00, // Function Reset - 0x0017ff00, // Double Function Reset - 0x000F0000, // Pad - get vendor id - 0x000F0002, // Pad - get revision id - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - AZALIA_SUBVENDOR(0x0, 0x10ec0283), - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ - AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010), - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - // group 1, front left/right - // no connector, no jack detect - // speaker out, analog - // fixed function, internal - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* Pin Complex (NID 0x17) */ - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - // group 1, cap 1 - // black, jack detect - // mic in, analog - // connector, left panel - AZALIA_PIN_CFG(0x0, 0x19, 0x03a71011), - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* Pin Complex (NID 0x1d) PCBeep */ - // eapd low on ex-amp, laptop, custom enable - // mute spkr on hpout - // pcbeep en able, checksum - // no physical, internal - AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - - /* Pin Complex (NID 0x21) HPOUT PORT-I */ - // group1, - // black, jack detect - // HPOut, 1/8 stereo - // connector, left panel - AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), - - /* Undocumented settings from Realtek (needed for beep_gen) */ - /* Widget node 0x20 */ - 0x02050010, - 0x02040c20, - 0x0205001b, - 0x0204081b, -}; - -const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ - 0x01470740, /* enable speaker out */ - 0x01470c02, /* set speaker EAPD pin */ - 0x0143b01f, /* unmute speaker */ - 0x00c37100, /* unmute mixer nid 0xc input 1 */ - 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/falco/i915io.c b/src/mainboard/google/falco/i915io.c deleted file mode 100644 index 5f33586..0000000 --- a/src/mainboard/google/falco/i915io.c +++ /dev/null @@ -1,125 +0,0 @@ -/* -* This file is part of the coreboot project. -* -* Copyright 2013 Google Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; version 2 of the License. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ - -/* This code was originally generated using an i915tool program. It has been - * improved by hand. - */ - -#include <stdint.h> -#include <console/console.h> -#include <delay.h> -#include <drivers/intel/gma/i915.h> -#include <arch/io.h> -#include "mainboard.h" - -/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */ -void runio(struct intel_dp *dp); - -void runio(struct intel_dp *dp) -{ - u8 read_val; - - intel_dp_wait_panel_power_control(0xabcd0008); - - /* vbios spins at this point. Some haswell weirdness? */ - intel_dp_wait_panel_power_control(0xabcd0008); - - /* This should be a function like intel_panel_enable_backlight - However, we are not sure how the value 0x3a9 comes up. - It has to do something with PWM frequency */ - gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE); - - gtt_write(DEIIR,0x00008000); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - - intel_dp_sink_dpms(dp, 0); - - intel_dp_get_max_downspread(dp, &read_val); - - intel_dp_set_m_n_regs(dp); - - intel_dp_set_resolution(dp); - - gtt_write(PIPESRC(dp->pipe),dp->pipesrc); - gtt_write(PIPECONF(dp->transcoder),0x00000000); - gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000); - - mainboard_set_port_clk_dp(dp); - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888); - gtt_write(DEIIR,0x00000080); - - gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags); - gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN); - - intel_dp_wait_panel_power_control(0xabcd000a); - - /* what is this doing? Not sure yet. */ - intel_dp_i2c_write(dp, 0x0); - intel_dp_i2c_read(dp, &read_val); - intel_dp_i2c_write(dp, 0x04); - intel_dp_i2c_read(dp, &read_val); - intel_dp_i2c_write(dp, 0x7e); - intel_dp_i2c_read(dp, &read_val); - - /* this needs to be a call to a function */ - gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091); - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); - gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091); - - /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */ - gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a); - gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a); - - intel_dp_set_bw(dp); - intel_dp_set_lane_count(dp); - - mainboard_train_link(dp); - - /* need a function: intel_ddi_set_tp or similar */ - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE); - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL); - - gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL1,0x80000000); - - /* some of this is not needed. */ - gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE ); - - gtt_write(SDEIIR,0x00000000); - gtt_write(DEIIR,0x00000000); - gtt_write(DEIIR,0x00008000); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(PIPESRC(dp->pipe),dp->pipesrc); - - gtt_write(DEIIR,0x00000080); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - - gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON); - - gtt_write(SDEIIR,0x00000000); - gtt_write(SDEIIR,0x00000000); - gtt_write(DEIIR,0x00000000); -} diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c deleted file mode 100644 index 10252d8..0000000 --- a/src/mainboard/google/falco/mainboard.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <smbios.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" -#include "onboard.h" - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - - - -static void mainboard_init(device_t dev) -{ - mainboard_ec_init(); -} - -static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) -{ - int len = 0; - - len += smbios_write_type41( - current, handle, - BOARD_LIGHTSENSOR_NAME, /* name */ - BOARD_LIGHTSENSOR_IRQ, /* instance */ - BOARD_LIGHTSENSOR_I2C_BUS, /* segment */ - BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - BOARD_TRACKPAD_I2C_BUS, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - return len; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/falco/mainboard.h b/src/mainboard/google/falco/mainboard.h deleted file mode 100644 index 6329a27..0000000 --- a/src/mainboard/google/falco/mainboard.h +++ /dev/null @@ -1,21 +0,0 @@ -/* -* This file is part of the coreboot project. -* -* Copyright 2013 Google Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; version 2 of the License. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ - -#ifndef __MAINBOARD_H_ -#define __MAINBOARD_H_ -void mainboard_train_link(struct intel_dp *intel_dp); -void mainboard_set_port_clk_dp(struct intel_dp *intel_dp); - -#endif diff --git a/src/mainboard/google/falco/onboard.h b/src/mainboard/google/falco/onboard.h deleted file mode 100644 index 36a9195..0000000 --- a/src/mainboard/google/falco/onboard.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#define BOARD_LIGHTSENSOR_NAME "lightsensor" -#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */ -#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */ -#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */ -#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */ -#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */ -#define BOARD_TRACKPAD_I2C_ADDR 0x67 - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */ -#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */ -#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a - -#endif diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c deleted file mode 100644 index 73d404f..0000000 --- a/src/mainboard/google/falco/romstage.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/lp_gpio.h> -#include "gpio.h" - -const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - - RCBA_END_CONFIG, -}; - -/* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) -{ - const int gpio_vector[] = {13, 9, 47, -1}; - int spd_index = get_gpios(gpio_vector); - char *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < sizeof(peid->spd_data[0])) - die("Missing SPD data."); - - /* Index 0-2,6 are 4GB config with both CH0 and CH1 - * Index 3-5,7 are 2GB config with CH0 only - */ - switch (spd_index) { - case 3: case 4: case 5: case 7: - peid->dimm_channel1_disabled = 3; - } - - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); -} - -void mainboard_romstage_entry(unsigned long bist) -{ - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - // Enable 2x refresh mode - .ddr_refresh_2x = 1, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = 1, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0064, 1, 0, /* P0: Port A, CN8 */ - USB_PORT_BACK_PANEL }, - { 0x0052, 1, 0, /* P1: Port B, CN9 */ - USB_PORT_BACK_PANEL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ - USB_PORT_INTERNAL }, - { 0x0123, 1, 3, /* P7: USB2 Port */ - USB_PORT_INTERNAL }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN8 */ - { 1, 0 }, /* P2; Port B, CN9 */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }, - }; - - struct romstage_params romstage_params = { - .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], - .bist = bist, - .copy_spd = copy_spd, - }; - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); -} diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c deleted file mode 100644 index 342ca0c..0000000 --- a/src/mainboard/google/falco/smihandler.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> -#include <elog.h> - -/* Include EC functions */ -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -/* GPIO46 controls the WLAN_DISABLE_L signal. */ -#define GPIO_WLAN_DISABLE_L 46 -#define GPIO_LTE_DISABLE_L 59 - -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S3. */ - set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S5. */ - set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); -} - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } - return 0; -} diff --git a/src/mainboard/google/falco/thermal.h b/src/mainboard/google/falco/thermal.h deleted file mode 100644 index a2f8e71..0000000 --- a/src/mainboard/google/falco/thermal.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Power level to set when EC requests throttle */ -#define EC_THROTTLE_POWER_LIMIT 12 /* 12W */ - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 99 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif diff --git a/src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex deleted file mode 100644 index eb41f0b..0000000 --- a/src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Elpida EDJ4216EFBG-GN-F -92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE -45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 -00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex deleted file mode 100644 index 7b09327..0000000 --- a/src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Hynix HMT425S6AFR6A-PBA -92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB -48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 -20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig deleted file mode 100644 index fa20a18..0000000 --- a/src/mainboard/google/peppy/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -if BOARD_GOOGLE_PEPPY - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_HASWELL - select NORTHBRIDGE_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT - select INTEL_LYNXPOINT_LP - select BOARD_ROMSIZE_KB_8192 - select EC_GOOGLE_CHROMEEC - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_NATIVE_VGA_INIT - select INTEL_DP - select INTEL_DDI - select INTEL_INT15 - -config CHROMEOS - select EC_GOOGLE_CHROMEEC_SWITCHES - select EC_SOFTWARE_SYNC - select LID_SWITCH - select MAINBOARD_DO_NATIVE_VGA_INIT - select VBOOT_VBNV_CMOS - select VIRTUAL_DEV_SWITCH - -config MAINBOARD_DIR - string - default google/peppy - -config MAINBOARD_PART_NUMBER - string - default "Peppy" - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config MAX_CPUS - int - default 8 - -config VGA_BIOS_FILE - string - default "pci8086,0166.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config GBB_HWID - string - depends on CHROMEOS - default "X86 PEPPY TEST 4211" -endif diff --git a/src/mainboard/google/peppy/Kconfig.name b/src/mainboard/google/peppy/Kconfig.name deleted file mode 100644 index 8049a54..0000000 --- a/src/mainboard/google/peppy/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_PEPPY - bool "Peppy" diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc deleted file mode 100644 index b49f98e..0000000 --- a/src/mainboard/google/peppy/Makefile.inc +++ /dev/null @@ -1,48 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c - -romstage-y += chromeos.c -ramstage-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c - -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 -SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 -SPD_SOURCES += Elpida_EDJ4216EFBG # 2: 4GB / CH0 + CH1 -SPD_SOURCES += Micron_4KTF25664HZ # 3: Reserved / place holder -SPD_SOURCES += Micron_4KTF25664HZ # 4: 2GB / CH0 + CH1 -SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 + CH1 -SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex deleted file mode 100644 index cbe9e4f..0000000 --- a/src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex +++ /dev/null @@ -1,17 +0,0 @@ -# Micron 4KTF25664HZ-1G6E1 -92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 -34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 -31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/peppy/acpi/ec.asl b/src/mainboard/google/peppy/acpi/ec.asl deleted file mode 100644 index 70113f7..0000000 --- a/src/mainboard/google/peppy/acpi/ec.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/peppy/ec.h> - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9..0000000 --- a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/peppy/acpi/mainboard.asl b/src/mainboard/google/peppy/acpi/mainboard.asl deleted file mode 100644 index 3ab8fe2..0000000 --- a/src/mainboard/google/peppy/acpi/mainboard.asl +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mainboard/google/peppy/onboard.h> - -Scope (\_SB) -{ - Device (LID0) - { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - } - - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - } - - Device (TPAD) - { - Name (_ADR, 0x0) - Name (_UID, 1) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) - - Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - - VendorShort (ADDR) - { - BOARD_TRACKPAD_I2C_ADDR - } - }) - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) - } - } - } - - Device (TSCR) - { - Name (_ADR, 0x0) - Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) - - Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ - } - - VendorShort (ADDR) - { - BOARD_TOUCHSCREEN_I2C_ADDR - } - }) - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - - Method (_DSW, 3, NotSerialized) - { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - \_SB.PCI0.LPCB.GWAK (Local0) - } - } - } -} diff --git a/src/mainboard/google/peppy/acpi/platform.asl b/src/mainboard/google/peppy/acpi/platform.asl deleted file mode 100644 index 1bd054d..0000000 --- a/src/mainboard/google/peppy/acpi/platform.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) - Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) - } - - /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) - Notify (\_SB.LID0, 0x80) - } - - Return(Package(){0,0}) -} diff --git a/src/mainboard/google/peppy/acpi/superio.asl b/src/mainboard/google/peppy/acpi/superio.asl deleted file mode 100644 index bc05937..0000000 --- a/src/mainboard/google/peppy/acpi/superio.asl +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ -#include <mainboard/google/peppy/ec.h> - -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 - -/* ACPI code for EC SuperIO functions */ -#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/peppy/acpi/thermal.asl b/src/mainboard/google/peppy/acpi/thermal.asl deleted file mode 100644 index ac84b5e..0000000 --- a/src/mainboard/google/peppy/acpi/thermal.asl +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x05) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 2 seconds - Name (_TSP, 20) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - - Method (_TMP, 0, Serialized) - { - // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) - - // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { - Return (CTOK(0)) - } - - // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { - Return (CTOK(0)) - } - - // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { - Return (CTOK(0)) - } - - // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { - Return (CTOK(0)) - } - - // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) - - // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) - Return (Local0) - } - - /* CTDP Down */ - Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { - Return (CTOK (\F0OF)) - } Else { - Return (CTOK (\F0ON)) - } - } - - /* CTDP Nominal */ - Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { - Return (CTOK (\F1OF)) - } Else { - Return (CTOK (\F1ON)) - } - } - - Name (_AL0, Package () { TDP0 }) - Name (_AL1, Package () { TDP1 }) - - PowerResource (TNP0, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 0)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (0, \FLVL) - - /* Enable Power Limit */ - \_SB.PCI0.MCHC.CTLE (\F0PW) - - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (1, \FLVL) - - /* Disable Power Limit */ - \_SB.PCI0.MCHC.CTLD () - - Notify (\_TZ.THRM, 0x81) - } - } - - PowerResource (TNP1, 0, 0) - { - Method (_STA) { - If (LLessEqual (\FLVL, 1)) { - Return (One) - } Else { - Return (Zero) - } - } - Method (_ON) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - Method (_OFF) { - Store (1, \FLVL) - Notify (\_TZ.THRM, 0x81) - } - } - - Device (TDP0) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 0) - Name (_PR0, Package () { TNP0 }) - } - - Device (TDP1) - { - Name (_HID, EISAID ("PNP0C0B")) - Name (_UID, 1) - Name (_PR0, Package () { TNP1 }) - } - } -} diff --git a/src/mainboard/google/peppy/acpi_tables.c b/src/mainboard/google/peppy/acpi_tables.c deleted file mode 100644 index cd75eb2..0000000 --- a/src/mainboard/google/peppy/acpi_tables.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h> - -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tmps = CTL_TDP_SENSOR_ID; - - /* Normal TDP */ - gnvs->f1of = 0; - gnvs->f1on = 0; - - /* Limited TDP */ - gnvs->f0of = CTL_TDP_THRESHOLD_OFF; - gnvs->f0on = CTL_TDP_THRESHOLD_ON; - gnvs->f0pw = CTL_TDP_POWER_LIMIT; - - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; - gnvs->flvl = 1; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 1; - - -#if CONFIG_CHROMEOS - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/google/peppy/board_info.txt b/src/mainboard/google/peppy/board_info.txt deleted file mode 100644 index a802401..0000000 --- a/src/mainboard/google/peppy/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Vendor name: Acer -Board name: C720 Chromebook -Category: laptop -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c deleted file mode 100644 index 22ec074..0000000 --- a/src/mainboard/google/peppy/chromeos.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio chromeos_gpios[] = { - {58, ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, - {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, - {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, - {-1, ACTIVE_HIGH, 0, "power"}, - {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - }; - lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -} -#endif - -int get_write_protect_state(void) -{ - return get_gpio(58); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), -}; - -void mainboard_chromeos_acpi_generate(void) -{ - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); -} diff --git a/src/mainboard/google/peppy/chromeos.fmd b/src/mainboard/google/peppy/chromeos.fmd deleted file mode 100644 index 0c05ce9..0000000 --- a/src/mainboard/google/peppy/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY(CBFS)@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x6f000 - COREBOOT(CBFS)@0x70000 0x180000 - } - } - } -} diff --git a/src/mainboard/google/peppy/cmos.layout b/src/mainboard/google/peppy/cmos.layout deleted file mode 100644 index b575e02..0000000 --- a/src/mainboard/google/peppy/cmos.layout +++ /dev/null @@ -1,110 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb deleted file mode 100644 index 505b39e..0000000 --- a/src/mainboard/google/peppy/devicetree.cb +++ /dev/null @@ -1,126 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "0" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl deleted file mode 100644 index 83305ab..0000000 --- a/src/mainboard/google/peppy/dsdt.asl +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define ENABLE_TPM - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - #include "acpi/mainboard.asl" - - // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> -} diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c deleted file mode 100644 index c011f33..0000000 --- a/src/mainboard/google/peppy/ec.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void mainboard_ec_init(void) -{ - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/google/peppy/ec.h b/src/mainboard/google/peppy/ec.h deleted file mode 100644 index 22942ee..0000000 --- a/src/mainboard/google/peppy/ec.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_EC_H -#define MAINBOARD_EC_H - -#include <ec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ -#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#endif diff --git a/src/mainboard/google/peppy/fadt.c b/src/mainboard/google/peppy/fadt.c deleted file mode 100644 index 2452ac2..0000000 --- a/src/mainboard/google/peppy/fadt.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/pch.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c deleted file mode 100644 index f3470a4..0000000 --- a/src/mainboard/google/peppy/gma.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <stdlib.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <delay.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <smbios.h> -#include <device/pci.h> -#include <ec/google/chromeec/ec.h> - -#include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <edid.h> -#include <drivers/intel/gma/i915.h> -#include <northbridge/intel/haswell/haswell.h> -#include "mainboard.h" - -/* - * Here is the rough outline of how we bring up the display: - * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD - * 2. Source determines video mode by reading DPCD receiver capability field - * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD - * 0000Dh). - * 3. Sink replies DPCD receiver capability field. - * 4. Source starts EDID read thru I2C-over-AUX. - * 5. Sink replies EDID thru I2C-over-AUX. - * 6. Source determines link configuration, such as MAX_LINK_RATE and - * MAX_LANE_COUNT. Source also determines which type of eDP Authentication - * method to use and writes DPCD link configuration field (DPCD 00100h to - * 0010Ah) including eDP configuration set (DPCD 0010Ah). - * 7. Source starts link training. Sink does clock recovery and equalization. - * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). - * 9. Sink replies DPCD link status field. If main link is not stable, Source - * repeats Step 7. - * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video - * parameters and recovers stream clock. - * 11. Source sends video data. - */ - -/* how many bytes do we need for the framebuffer? - * Well, this gets messy. To get an exact answer, we have - * to ask the panel, but we'd rather zero the memory - * and set up the gtt while the panel powers up. So, - * we take a reasonable guess, secure in the knowledge that the - * MRC has to overestimate the number of bytes used. - * 8 MiB is a very safe guess. There may be a better way later, but - * fact is, the initial framebuffer is only very temporary. And taking - * a little long is ok; this is done much faster than the AUX - * channel is ready for IO. - */ -#define FRAME_BUFFER_BYTES (8*MiB) -/* how many 4096-byte pages do we need for the framebuffer? - * There are hard ways to get this, and easy ways: - * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 - * on this chip (and in fact every Intel graphics chip we've seen). - */ -#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) - - -static int i915_init_done = 0; - -/* fill the palette. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for(i = 0; i < 256; i++, color += 0x010101){ - gtt_write(_LGC_PALETTE_A + (i << 2),color); - } -} - -void mainboard_train_link(struct intel_dp *intel_dp) -{ - u8 read_val; - u8 link_status[DP_LINK_STATUS_SIZE]; - - gtt_write(DP_TP_CTL(intel_dp->port), - DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); - gtt_write(DDI_BUF_CTL_A, - DDI_BUF_CTL_ENABLE| - DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011); - - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, - DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | - DP_SYMBOL_ERROR_COUNT_BOTH); - - intel_dp_set_training_lane0(intel_dp, - DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); - intel_dp_get_link_status(intel_dp, link_status); - - gtt_write(DP_TP_CTL(intel_dp->port), - DP_TP_CTL_ENABLE | - DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); - - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | - DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); - intel_dp_get_link_status(intel_dp, link_status); - intel_dp_get_lane_align_status(intel_dp, &read_val); - intel_dp_get_training_pattern(intel_dp, &read_val); - intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | - DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); -} - -/* This variable controls whether the test_gfx function below puts up - * color bars or not. In previous revs we ifdef'd the test_gfx function out - * but it's handy, especially when using a JTAG debugger - * to be able to enable and disable a test graphics. - */ -int show_test = 0; - -static void test_gfx(struct intel_dp *dp) -{ - int i; - - if (!show_test) - return; - /* This is a sanity test code which fills the screen with two bands -- - green and blue. It is very useful to ensure all the initializations - are made right. Thus, to be used only for testing, not otherwise - */ - - for (i = 0; i < (dp->edid.mode.va - 4); i++) { - u32 *l; - int j; - u32 tcolor = 0x0ff; - for (j = 0; j < (dp->edid.mode.ha-4); j++) { - if (j == (dp->edid.mode.ha/2)) { - tcolor = 0xff00; - } - l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor)); - memcpy(l,&tcolor,sizeof(tcolor)); - } - } - printk(BIOS_SPEW, "sleep 10\n"); - delay(10); -} - -void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) -{ - u32 ddi_pll_sel = 0; - - switch (intel_dp->link_bw) { - case DP_LINK_BW_1_62: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; - break; - case DP_LINK_BW_2_7: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; - break; - case DP_LINK_BW_5_4: - ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; - break; - default: - printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); - return; - } - - gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); -} - -int panel_lightup(struct intel_dp *dp, unsigned int init_fb) -{ - int i; - int edid_ok; - int pixels = FRAME_BUFFER_BYTES/64; - - gtt_write(PCH_PP_CONTROL,0xabcd000f); - delay(1); - - void runio(struct intel_dp *dp); - /* hard codes -- stuff you can only know from the mainboard */ - dp->gen = 8; // This is gen 8 which we believe is Haswell - dp->is_haswell = 1; - dp->DP = 0x2; - dp->pipe = PIPE_A; - dp->port = PORT_A; - dp->plane = PLANE_A; - dp->pipe_bits_per_pixel = 24; - dp->type = INTEL_OUTPUT_EDP; - dp->output_reg = DP_A; - /* observed from YABEL. */ - dp->aux_clock_divider = 0xe1; - dp->precharge = 3; - - /* 1. Normal mode: Set the first page to zero and make - all GTT entries point to the same page - 2. Developer/Recovery mode: Set up a tasteful color - so people know we are alive. */ - if (init_fb || show_test) { - set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, - 4096); - memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096); - } else { - set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0); - memset((void*)dp->graphics, 0, 4096); - } - - dp->address = 0x50; - - if ( !intel_dp_get_dpcd(dp) ) - goto fail; - - intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); - for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ - if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, - 0x50, &dp->rawedid[i]) < 0) - break; - dp->edidlen++; - } - - edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); - - printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - - compute_display_params(dp); - - printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n", - dp->edid.mode.pixel_clock, dp->edid.link_clock); - - intel_ddi_set_pipe_settings(dp); - - runio(dp); - - palette(); - - pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; - printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); - test_gfx(dp); - - set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); - i915_init_done = 1; - return 1; - -fail: - printk(BIOS_SPEW, "Graphics could not be started;"); - /* unclear we will *ever* want to do this. */ - if (0){ - printk(BIOS_SPEW, "Turn off power and wait ..."); - gtt_write(PCH_PP_CONTROL,0xabcd0000); - udelay(600000); - gtt_write(PCH_PP_CONTROL,0xabcd000f); - } - printk(BIOS_SPEW, "Returning.\n"); - return 0; -} diff --git a/src/mainboard/google/peppy/gpio.h b/src/mainboard/google/peppy/gpio.h deleted file mode 100644 index 8eb3da9..0000000 --- a/src/mainboard/google/peppy/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PEPPY_GPIO_H -#define PEPPY_GPIO_H - -struct pch_lp_gpio_map; - -const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_UNUSED, /* 0: UNUSED */ - LP_GPIO_UNUSED, /* 1: UNUSED */ - LP_GPIO_UNUSED, /* 2: UNUSED */ - LP_GPIO_UNUSED, /* 3: UNUSED */ - LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ - LP_GPIO_INPUT, /* 9: RAM_ID1 */ - LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ - LP_GPIO_INPUT, /* 13: RAM_ID0 */ - LP_GPIO_INPUT, /* 14: EC_IN_RW */ - LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 16: UNUSED */ - LP_GPIO_UNUSED, /* 17: UNUSED */ - LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ - LP_GPIO_UNUSED, /* 20: UNUSED */ - LP_GPIO_UNUSED, /* 21: UNUSED */ - LP_GPIO_UNUSED, /* 22: UNUSED */ - LP_GPIO_UNUSED, /* 23: UNUSED */ - LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ - LP_GPIO_UNUSED, /* 26: UNUSED */ - LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_UNUSED, /* 28: UNUSED */ - LP_GPIO_UNUSED, /* 29: UNUSED */ - LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ - LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - LP_GPIO_UNUSED, /* 37: UNUSED */ - LP_GPIO_UNUSED, /* 38: UNUSED */ - LP_GPIO_UNUSED, /* 39: UNUSED */ - LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - LP_GPIO_UNUSED, /* 41: UNUSED */ - LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - LP_GPIO_UNUSED, /* 43: UNUSED */ - LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ - LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ - LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ - LP_GPIO_INPUT, /* 47: RAM_ID2 */ - LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_UNUSED, /* 49: UNUSED */ - LP_GPIO_UNUSED, /* 50: UNUSED */ - LP_GPIO_INPUT, /* 51: ALS_INT_L */ - LP_GPIO_INPUT, /* 52: SIM_DET */ - LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */ - LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ - LP_GPIO_UNUSED, /* 55: UNUSED */ - LP_GPIO_UNUSED, /* 56: UNUSED */ - LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ - LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_UNUSED, /* 61: UNUSED */ - LP_GPIO_UNUSED, /* 62: UNUSED */ - LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - LP_GPIO_UNUSED, /* 64: UNUSED */ - LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 67: UNUSED */ - LP_GPIO_UNUSED, /* 68: UNUSED */ - LP_GPIO_UNUSED, /* 69: UNUSED */ - LP_GPIO_UNUSED, /* 70: UNUSED */ - LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ - LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ - LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - LP_GPIO_UNUSED, /* 76: UNUSED */ - LP_GPIO_UNUSED, /* 77: UNUSED */ - LP_GPIO_UNUSED, /* 78: UNUSED */ - LP_GPIO_UNUSED, /* 79: UNUSED */ - LP_GPIO_UNUSED, /* 80: UNUSED */ - LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - LP_GPIO_UNUSED, /* 83: UNUSED */ - LP_GPIO_UNUSED, /* 84: UNUSED */ - LP_GPIO_UNUSED, /* 85: UNUSED */ - LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 87: UNUSED */ - LP_GPIO_UNUSED, /* 88: UNUSED */ - LP_GPIO_UNUSED, /* 89: UNUSED */ - LP_GPIO_UNUSED, /* 90: UNUSED */ - LP_GPIO_UNUSED, /* 91: UNUSED */ - LP_GPIO_UNUSED, /* 92: UNUSED */ - LP_GPIO_UNUSED, /* 93: UNUSED */ - LP_GPIO_UNUSED, /* 94: UNUSED */ - LP_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/peppy/hda_verb.c b/src/mainboard/google/peppy/hda_verb.c deleted file mode 100644 index 8b8077f..0000000 --- a/src/mainboard/google/peppy/hda_verb.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 - 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) - - /* Bits 31:28 - Codec Address */ - /* Bits 27:20 - NID */ - /* Bits 19:8 - Verb ID */ - /* Bits 7:0 - Payload */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - AZALIA_SUBVENDOR(0x0, 0x10ec0283), - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), - - /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ - // group 1, cap 0 - // no connector, no jack detect - // speaker out, analog - // fixed function, internal, Location N/A - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* Pin Complex (NID 0x18) Disabled */ - AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - - /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ - // group2, cap 0 - // black, jack detect - // Mic in, 3.5mm Jack - // connector, External left panel - AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020), - - /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */ - // group 1, cap 1 - // no connector, no jack detect - // mic in, analog connection - // Fixed function, internal, Location N/A - AZALIA_PIN_CFG(0x0, 0x1a, 0x90a70111), - - /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* Pin Complex (NID 0x1D) PCBeep */ - // eapd low on ex-amp, laptop, custom enable - // mute spkr on hpout - // pcbeep en able, checksum - // no physical, Internal, Location N/A - AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), - - /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - - /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ - // group2, cap 1 - // black, jack detect - // HPOut, 3.5mm Jack - // connector, left panel - AZALIA_PIN_CFG(0x0, 0x21, 0x03211021), - - /* Undocumented settings from Realtek (needed for beep_gen) */ - /* Widget node 0x20 */ - 0x02050010, - 0x02040c20, - 0x0205001b, - 0x0204081b, -}; - -const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ - 0x01470740, /* enable speaker out */ - 0x01470c02, /* set speaker EAPD pin */ - 0x0143b01f, /* unmute speaker */ - 0x00c37100, /* unmute mixer nid 0xc input 1 */ - 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/peppy/i915io.c b/src/mainboard/google/peppy/i915io.c deleted file mode 100644 index a97f994..0000000 --- a/src/mainboard/google/peppy/i915io.c +++ /dev/null @@ -1,139 +0,0 @@ -/* -* This file is part of the coreboot project. -* -* Copyright 2013 Google Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; version 2 of the License. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ - -#include <stdint.h> -#include <console/console.h> -#include <delay.h> -#include <drivers/intel/gma/i915.h> -#include <arch/io.h> -#include "mainboard.h" - -void runio(struct intel_dp *dp, int verbose); -void runio(struct intel_dp *dp, int verbose) -{ - u8 read_val; - gtt_write(DDI_BUF_CTL_A, - DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED - |0x00000091); - - intel_prepare_ddi(); - - gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL1,0x80000000); - - gtt_write(DEIIR,0x00008000); - intel_dp_wait_reg(DEIIR, 0x00000000); - gtt_write(DSPSTRIDE(dp->plane), dp->stride); - gtt_write(DSPADDR(dp->plane), 0x00000000); - - printk(BIOS_SPEW, "DP_SET_POWER"); - - intel_dp_sink_dpms(dp, 0); - - intel_dp_set_m_n_regs(dp); - - intel_dp_get_max_downspread(dp, &read_val); - - intel_dp_set_resolution(dp); - - gtt_write(PIPESRC(dp->pipe),dp->pipesrc); - gtt_write(PIPECONF(dp->transcoder),0x00000000); - gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000); - - mainboard_set_port_clk_dp(dp); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888); - - gtt_write(DEIIR,0x00000080); - intel_dp_wait_reg(DEIIR, 0x00000000); - - /* There is some reason we removed these three calls from - * slippy/gma.c -- I dont remember why!! */ - gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos); - gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl); - gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz); - - gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags); - gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN); - - /* what is this doing? Not sure yet. But we don't seem to be - * able to live without it.*/ - intel_dp_i2c_write(dp, 0x0); - intel_dp_i2c_read(dp, &read_val); - intel_dp_i2c_write(dp, 0x04); - intel_dp_i2c_read(dp, &read_val); - intel_dp_i2c_write(dp, 0x7e); - intel_dp_i2c_read(dp, &read_val); - - gtt_write(DDI_BUF_CTL_A, - DDI_BUF_IS_IDLE| - DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED - |0x00000091); - - gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001); - gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | - DP_TP_CTL_ENHANCED_FRAME_ENABLE); - - gtt_write(DDI_BUF_CTL_A, - DDI_BUF_CTL_ENABLE| - /* another undocumented setting. Surprised? */ 0x40000 | - DDI_BUF_IS_IDLE|DDI_A_4_LANES| - DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED| - 0x80040091); - - intel_dp_set_bw(dp); - - intel_dp_set_lane_count(dp); - - mainboard_train_link(dp); - - gtt_write(DP_TP_CTL(dp->port), - DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | - DP_TP_CTL_LINK_TRAIN_IDLE); - - gtt_write(DP_TP_CTL(dp->port), - DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | - DP_TP_CTL_LINK_TRAIN_NORMAL); - - gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); - gtt_write(BLC_PWM_PCH_CTL1,0x80000000); - - /* some of this is not needed. But with a total lack of docs, well ...*/ - gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE ); - - gtt_write(SDEIIR,0x00000000); - gtt_write(DEIIR,0x00000000); - gtt_write(DEIIR,0x00008000); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(PIPESRC(dp->pipe),dp->pipesrc); - - gtt_write(DEIIR,0x00000080); - intel_dp_wait_reg(DEIIR, 0x00000000); - - gtt_write(DSPSTRIDE(dp->plane),dp->stride); - gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - - gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON); - - gtt_write(SDEIIR,0x00000000); - gtt_write(SDEIIR,0x00000000); - gtt_write(DEIIR,0x00000000); - -} diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c deleted file mode 100644 index 10252d8..0000000 --- a/src/mainboard/google/peppy/mainboard.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <smbios.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" -#include "onboard.h" - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - - - -static void mainboard_init(device_t dev) -{ - mainboard_ec_init(); -} - -static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) -{ - int len = 0; - - len += smbios_write_type41( - current, handle, - BOARD_LIGHTSENSOR_NAME, /* name */ - BOARD_LIGHTSENSOR_IRQ, /* instance */ - BOARD_LIGHTSENSOR_I2C_BUS, /* segment */ - BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - BOARD_TRACKPAD_I2C_BUS, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - return len; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; - dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/peppy/mainboard.h b/src/mainboard/google/peppy/mainboard.h deleted file mode 100644 index 6329a27..0000000 --- a/src/mainboard/google/peppy/mainboard.h +++ /dev/null @@ -1,21 +0,0 @@ -/* -* This file is part of the coreboot project. -* -* Copyright 2013 Google Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; version 2 of the License. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ - -#ifndef __MAINBOARD_H_ -#define __MAINBOARD_H_ -void mainboard_train_link(struct intel_dp *intel_dp); -void mainboard_set_port_clk_dp(struct intel_dp *intel_dp); - -#endif diff --git a/src/mainboard/google/peppy/onboard.h b/src/mainboard/google/peppy/onboard.h deleted file mode 100644 index 9e1dc8b..0000000 --- a/src/mainboard/google/peppy/onboard.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#define BOARD_LIGHTSENSOR_NAME "lightsensor" -#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */ -#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */ -#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */ -#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */ -#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */ -#define BOARD_TRACKPAD_I2C_ADDR 0x67 - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */ -#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */ -#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a - -#define PEPPY_BOARD_VERSION_PROTO 0 -#define PEPPY_BOARD_VERSION_EVT 1 - -#endif diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c deleted file mode 100644 index 6be643f..0000000 --- a/src/mainboard/google/peppy/romstage.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include "ec/google/chromeec/ec.h" -#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/lp_gpio.h> -#include "gpio.h" -#include "onboard.h" - -const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), - - RCBA_END_CONFIG, -}; - -/* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) -{ - const int gpio_vector[] = {13, 9, 47, -1}; - int spd_index = get_gpios(gpio_vector); - char *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - switch (google_chromeec_get_board_version()) { - case PEPPY_BOARD_VERSION_PROTO: - /* Index 0 is 2GB config with CH0 only. */ - if (spd_index == 0) - peid->dimm_channel1_disabled = 3; - break; - - case PEPPY_BOARD_VERSION_EVT: - default: - /* Index 0-2 are 4GB config with both CH0 and CH1. - * Index 4-6 are 2GB config with CH0 only. */ - if (spd_index > 3) - peid->dimm_channel1_disabled = 3; - break; - } - - if (spd_file_len < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < sizeof(peid->spd_data[0])) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); -} - -void mainboard_romstage_entry(unsigned long bist) -{ - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_xhci_on_resume = 1, - .usb2_ports = { - /* Length, Enable, OCn#, Location */ - { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 0, /* P1: Port A, CN10 */ - USB_PORT_BACK_PANEL }, - { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ - USB_PORT_INTERNAL }, - { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ - USB_PORT_MINI_PCIE }, - { 0x0040, 1, 2, /* P4: Port B, CN6 */ - USB_PORT_BACK_PANEL }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ - USB_PORT_SKIP }, - { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ - USB_PORT_FLEX }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ - USB_PORT_SKIP }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN6 */ - { 0, USB_OC_PIN_SKIP }, /* P2; */ - { 0, USB_OC_PIN_SKIP }, /* P3; */ - { 0, USB_OC_PIN_SKIP }, /* P4; */ - }, - }; - - struct romstage_params romstage_params = { - .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], - .bist = bist, - .copy_spd = copy_spd, - }; - - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); -} diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c deleted file mode 100644 index f3e69f9..0000000 --- a/src/mainboard/google/peppy/smihandler.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> -#include <elog.h> - -/* Include EC functions */ -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -/* Codec enable: GPIO45 */ -#define GPIO_PP3300_CODEC_EN 45 -/* WLAN / BT enable: GPIO46 */ -#define GPIO_WLAN_DISABLE_L 46 - -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - set_gpio(GPIO_PP3300_CODEC_EN, 0); - set_gpio(GPIO_WLAN_DISABLE_L, 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - - set_gpio(GPIO_PP3300_CODEC_EN, 0); - set_gpio(GPIO_WLAN_DISABLE_L, 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); -} - - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - case APM_CNT_ACPI_ENABLE: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); - break; - } - return 0; -} diff --git a/src/mainboard/google/peppy/thermal.h b/src/mainboard/google/peppy/thermal.h deleted file mode 100644 index ded9be4..0000000 --- a/src/mainboard/google/peppy/thermal.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THERMAL_H -#define THERMAL_H - -/* Control TDP Settings */ -#define CTL_TDP_SENSOR_ID 0 /* PECI */ -#define CTL_TDP_POWER_LIMIT 12 /* 12W */ -#define CTL_TDP_THRESHOLD_OFF 80 /* Normal at 80C */ -#define CTL_TDP_THRESHOLD_ON 85 /* Limited at 85C */ - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 99 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif

1 0

New patch to review for coreboot: Add/Combine Haswell Chromebooks using variant board scheme
by Matt DeVillier 27 Nov '16

27 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17621 -gerrit commit 8427eb6e9c8fd1d89f7212ca32da7506a89cf1e6 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sun Nov 27 02:19:02 2016 -0600 Add/Combine Haswell Chromebooks using variant board scheme Combine existing boards google/falco and google/peppy with new ChromeOS devices leon and wolf, using their common reference board (slippy) as a base. Chromium sources used: firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...] firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode] firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...] Additionally, some minor cleanup/changes were made: - I2C devices set to use ACPI (vs PCI) mode - I2C device ACPI entries adjusted as per above - I2C devices set to use level (vs edge) interrupt triggering - XHCI finalization enabled in devicetree - HDA verb entries use simplified macro entry format Existing google/falco and google/peppy boards will be removed in a subsequent commit. Variant setup modeled after google/beltino Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/slippy/Kconfig | 88 +++++++ src/mainboard/google/slippy/Kconfig.name | 15 ++ src/mainboard/google/slippy/Makefile.inc | 26 ++ src/mainboard/google/slippy/acpi/ec.asl | 20 ++ .../google/slippy/acpi/haswell_pci_irqs.asl | 82 +++++++ src/mainboard/google/slippy/acpi/platform.asl | 82 +++++++ src/mainboard/google/slippy/acpi/superio.asl | 25 ++ src/mainboard/google/slippy/acpi/thermal.asl | 132 ++++++++++ src/mainboard/google/slippy/acpi_tables.c | 84 +++++++ src/mainboard/google/slippy/board_info.txt | 7 + src/mainboard/google/slippy/chromeos.c | 52 ++++ src/mainboard/google/slippy/chromeos.fmd | 38 +++ src/mainboard/google/slippy/cmos.layout | 110 +++++++++ src/mainboard/google/slippy/dsdt.asl | 67 +++++ src/mainboard/google/slippy/ec.c | 47 ++++ src/mainboard/google/slippy/ec.h | 55 +++++ src/mainboard/google/slippy/fadt.c | 152 ++++++++++++ src/mainboard/google/slippy/mainboard.c | 97 ++++++++ src/mainboard/google/slippy/onboard.h | 39 +++ src/mainboard/google/slippy/romstage.c | 24 ++ src/mainboard/google/slippy/smihandler.c | 154 ++++++++++++ src/mainboard/google/slippy/thermal.h | 33 +++ src/mainboard/google/slippy/variant.h | 21 ++ .../google/slippy/variants/falco/Makefile.inc | 43 ++++ .../google/slippy/variants/falco/devicetree.cb | 125 ++++++++++ src/mainboard/google/slippy/variants/falco/gma.c | 246 +++++++++++++++++++ .../google/slippy/variants/falco/hda_verb.c | 103 ++++++++ .../google/slippy/variants/falco/i915io.c | 125 ++++++++++ .../falco/include/variant/acpi/mainboard.asl | 84 +++++++ .../slippy/variants/falco/include/variant/gpio.h | 120 +++++++++ .../variants/falco/include/variant/mainboard.h | 21 ++ .../google/slippy/variants/falco/romstage.c | 175 +++++++++++++ .../variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex | 17 ++ .../variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 ++ .../variants/falco/spd/Micron_4KTF25664HZ.spd.hex | 17 ++ .../falco/spd/Samsung_M471B5674QH0.spd.hex | 17 ++ .../google/slippy/variants/leon/Makefile.inc | 40 +++ .../google/slippy/variants/leon/devicetree.cb | 157 ++++++++++++ .../google/slippy/variants/leon/hda_verb.c | 103 ++++++++ .../leon/include/variant/acpi/mainboard.asl | 88 +++++++ .../slippy/variants/leon/include/variant/gpio.h | 120 +++++++++ .../google/slippy/variants/leon/romstage.c | 171 +++++++++++++ .../variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 ++ .../variants/leon/spd/Micron_4KTF25664HZ.spd.hex | 17 ++ .../variants/leon/spd/Samsung_K4B4G1646Q.spd.hex | 17 ++ .../google/slippy/variants/peppy/Makefile.inc | 42 ++++ .../google/slippy/variants/peppy/devicetree.cb | 129 ++++++++++ src/mainboard/google/slippy/variants/peppy/gma.c | 272 +++++++++++++++++++++ .../google/slippy/variants/peppy/hda_verb.c | 107 ++++++++ .../google/slippy/variants/peppy/i915io.c | 139 +++++++++++ .../peppy/include/variant/acpi/mainboard.asl | 172 +++++++++++++ .../slippy/variants/peppy/include/variant/gpio.h | 120 +++++++++ .../variants/peppy/include/variant/mainboard.h | 21 ++ .../google/slippy/variants/peppy/romstage.c | 184 ++++++++++++++ .../variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex | 17 ++ .../variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 ++ .../variants/peppy/spd/Micron_4KTF25664HZ.spd.hex | 17 ++ .../google/slippy/variants/wolf/Makefile.inc | 39 +++ .../google/slippy/variants/wolf/devicetree.cb | 130 ++++++++++ .../google/slippy/variants/wolf/hda_verb.c | 112 +++++++++ .../wolf/include/variant/acpi/mainboard.asl | 88 +++++++ .../slippy/variants/wolf/include/variant/gpio.h | 120 +++++++++ .../google/slippy/variants/wolf/romstage.c | 175 +++++++++++++ .../variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex | 17 ++ .../variants/wolf/spd/Micron_4KTF25664HZ.spd.hex | 17 ++ .../variants/wolf/spd/Samsung_K4B4G1646B.spd.hex | 17 ++ 66 files changed, 5242 insertions(+) diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig new file mode 100644 index 0000000..045d6a8 --- /dev/null +++ b/src/mainboard/google/slippy/Kconfig @@ -0,0 +1,88 @@ +config BOARD_GOOGLE_BASEBOARD_SLIPPY + def_bool n + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_HASWELL + select NORTHBRIDGE_INTEL_HASWELL + select SOUTHBRIDGE_INTEL_LYNXPOINT + select INTEL_LYNXPOINT_LP + select BOARD_ROMSIZE_KB_8192 + select EC_GOOGLE_CHROMEEC + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_NATIVE_VGA_INIT if (BOARD_GOOGLE_FALCO || BOARD_GOOGLE_PEPPY) + select INTEL_DP if (BOARD_GOOGLE_FALCO || BOARD_GOOGLE_PEPPY) + select INTEL_DDI if (BOARD_GOOGLE_FALCO || BOARD_GOOGLE_PEPPY) + select INTEL_INT15 + +if BOARD_GOOGLE_BASEBOARD_SLIPPY + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + select EC_SOFTWARE_SYNC + select LID_SWITCH + select MAINBOARD_DO_NATIVE_VGA_INIT if (BOARD_GOOGLE_FALCO || BOARD_GOOGLE_PEPPY) + select VBOOT_VBNV_CMOS + select VIRTUAL_DEV_SWITCH + +config MAINBOARD_DIR + string + default google/slippy + +config VARIANT_DIR + string + default "falco" if BOARD_GOOGLE_FALCO + default "leon" if BOARD_GOOGLE_LEON + default "peppy" if BOARD_GOOGLE_PEPPY + default "wolf" if BOARD_GOOGLE_WOLF + +config MAINBOARD_PART_NUMBER + string + default "Falco" if BOARD_GOOGLE_FALCO + default "Leon" if BOARD_GOOGLE_LEON + default "Peppy" if BOARD_GOOGLE_PEPPY + default "Wolf" if BOARD_GOOGLE_WOLF + +config MAINBOARD_FAMILY + string + default "Google_Slippy" + +config GBB_HWID + string + depends on CHROMEOS + default "X86 FALCO TEST 0289" if BOARD_GOOGLE_FALCO + default "X86 LEON TEST 5181" if BOARD_GOOGLE_LEON + default "X86 PEPPY TEST 4211" if BOARD_GOOGLE_PEPPY + default "X86 WOLF TEST 6457" if BOARD_GOOGLE_WOLF + +config DEVICETREE + string + default "variants/falco/devicetree.cb" if BOARD_GOOGLE_FALCO + default "variants/leon/devicetree.cb" if BOARD_GOOGLE_LEON + default "variants/peppy/devicetree.cb" if BOARD_GOOGLE_PEPPY + default "variants/wolf/devicetree.cb" if BOARD_GOOGLE_WOLF + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0406.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/Kconfig.name b/src/mainboard/google/slippy/Kconfig.name new file mode 100644 index 0000000..4aebcff --- /dev/null +++ b/src/mainboard/google/slippy/Kconfig.name @@ -0,0 +1,15 @@ +config BOARD_GOOGLE_FALCO + bool "Falco" + select BOARD_GOOGLE_BASEBOARD_SLIPPY + +config BOARD_GOOGLE_LEON + bool "Leon" + select BOARD_GOOGLE_BASEBOARD_SLIPPY + +config BOARD_GOOGLE_PEPPY + bool "Peppy" + select BOARD_GOOGLE_BASEBOARD_SLIPPY + +config BOARD_GOOGLE_WOLF + bool "Wolf" + select BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc new file mode 100644 index 0000000..8c95ba1 --- /dev/null +++ b/src/mainboard/google/slippy/Makefile.inc @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/slippy/acpi/ec.asl b/src/mainboard/google/slippy/acpi/ec.asl new file mode 100644 index 0000000..58b9a55 --- /dev/null +++ b/src/mainboard/google/slippy/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..68ea474 --- /dev/null +++ b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for Haswell */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 22 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl new file mode 100644 index 0000000..1bd054d --- /dev/null +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Update AC status */ + Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) + if (LNotEqual (Local0, \PWRS)) { + Store (Local0, \PWRS) + Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) + } + + /* Update LID status */ + Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) + if (LNotEqual (Local0, \LIDS)) { + Store (Local0, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + Return(Package(){0,0}) +} diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl new file mode 100644 index 0000000..0460b2b --- /dev/null +++ b/src/mainboard/google/slippy/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/slippy/acpi/thermal.asl b/src/mainboard/google/slippy/acpi/thermal.asl new file mode 100644 index 0000000..36b0e21 --- /dev/null +++ b/src/mainboard/google/slippy/acpi/thermal.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + // Handler for throttle requests on this platform + // 0 = Stop throttling + // 1 = Start throttling + Method (THRT, 1, Serialized) + { + If (LEqual (Arg0, 0)) { + /* Disable Power Limit */ + \_SB.PCI0.MCHC.CTLD () + } Else { + /* Enable Power Limit */ + \_SB.PCI0.MCHC.CTLE (\F0PW) + } + } + + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (TCHK, 0, Serialized) + { + // Get Temperature from TIN# set in NVS + Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + + // Check for sensor not calibrated + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (CTOK(0)) + } + + // Check for sensor not present + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (CTOK(0)) + } + + // Check for sensor not powered + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (CTOK(0)) + } + + // Check for sensor bad reading + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (CTOK(0)) + } + + // Adjust by offset to get Kelvin + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + // Convert to 1/10 Kelvin + Multiply (Local0, 10, Local0) + Return (Local0) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from EC in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TCRT), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for EC to re-poll + Sleep (1000) + + // Re-read temperature from EC + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + } +} diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c new file mode 100644 index 0000000..97b246f --- /dev/null +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h> + +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = TEMPERATURE_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->f0pw = EC_THROTTLE_POWER_LIMIT; + gnvs->flvl = 1; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + +#if CONFIG_CHROMEOS + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} diff --git a/src/mainboard/google/slippy/board_info.txt b/src/mainboard/google/slippy/board_info.txt new file mode 100644 index 0000000..4e2fd7d --- /dev/null +++ b/src/mainboard/google/slippy/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Google +Board name: Slippy Haswell Chromebook Reference device +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c new file mode 100644 index 0000000..22ec074 --- /dev/null +++ b/src/mainboard/google/slippy/chromeos.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {58, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif + +int get_write_protect_state(void) +{ + return get_gpio(58); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd new file mode 100644 index 0000000..0c05ce9 --- /dev/null +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + RW_SECTION_A@0x0 0xf0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0xdffc0 + RW_FWID_A@0xeffc0 0x40 + } + RW_SECTION_B@0xf0000 0xf0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0xdffc0 + RW_FWID_B@0xeffc0 0x40 + } + RW_MRC_CACHE@0x1e0000 0x10000 + RW_ELOG@0x1f0000 0x4000 + RW_SHARED@0x1f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1f8000 0x2000 + RW_UNUSED@0x1fa000 0x6000 + RW_LEGACY(CBFS)@0x200000 0x200000 + WP_RO@0x400000 0x200000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x1f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x6f000 + COREBOOT(CBFS)@0x70000 0x180000 + } + } + } +} diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout new file mode 100644 index 0000000..b575e02 --- /dev/null +++ b/src/mainboard/google/slippy/cmos.layout @@ -0,0 +1,110 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl new file mode 100644 index 0000000..56771c2 --- /dev/null +++ b/src/mainboard/google/slippy/dsdt.asl @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <cpu/intel/haswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + Scope (\_SB.PCI0.RP01) + { + Device (WLAN) + { + Name (_ADR, Zero) + } + } + + // Mainboard specific + #include <variant/acpi/mainboard.asl> + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> +} diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c new file mode 100644 index 0000000..c011f33 --- /dev/null +++ b/src/mainboard/google/slippy/ec.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <types.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + + /* Restore SCI event mask on resume. */ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_wake_mask(0); + + post_code(0xf1); +} diff --git a/src/mainboard/google/slippy/ec.h b/src/mainboard/google/slippy/ec.h new file mode 100644 index 0000000..22942ee --- /dev/null +++ b/src/mainboard/google/slippy/ec.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ +#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#endif diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c new file mode 100644 index 0000000..2452ac2 --- /dev/null +++ b/src/mainboard/google/slippy/fadt.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = get_pmbase(); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c new file mode 100644 index 0000000..10252d8 --- /dev/null +++ b/src/mainboard/google/slippy/mainboard.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <smbios.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include "ec.h" +#include "onboard.h" + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + + + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +static int mainboard_smbios_data(device_t dev, int *handle, + unsigned long *current) +{ + int len = 0; + + len += smbios_write_type41( + current, handle, + BOARD_LIGHTSENSOR_NAME, /* name */ + BOARD_LIGHTSENSOR_IRQ, /* instance */ + BOARD_LIGHTSENSOR_I2C_BUS, /* segment */ + BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + len += smbios_write_type41( + current, handle, + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ + BOARD_TRACKPAD_I2C_BUS, /* segment */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + len += smbios_write_type41( + current, handle, + BOARD_TOUCHSCREEN_NAME, /* name */ + BOARD_TOUCHSCREEN_IRQ, /* instance */ + BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ + BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + return len; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/slippy/onboard.h b/src/mainboard/google/slippy/onboard.h new file mode 100644 index 0000000..9e1dc8b --- /dev/null +++ b/src/mainboard/google/slippy/onboard.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */ +#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */ +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */ +#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */ +#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */ +#define BOARD_TRACKPAD_I2C_ADDR 0x67 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */ +#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */ +#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +#define PEPPY_BOARD_VERSION_PROTO 0 +#define PEPPY_BOARD_VERSION_EVT 1 + +#endif diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c new file mode 100644 index 0000000..82931fc --- /dev/null +++ b/src/mainboard/google/slippy/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/intel/haswell/haswell.h> +#include "variant.h" + + +void mainboard_romstage_entry(unsigned long bist) +{ + variant_romstage_entry(bist); +} diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c new file mode 100644 index 0000000..24f76f5 --- /dev/null +++ b/src/mainboard/google/slippy/smihandler.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/me.h> +#include <northbridge/intel/haswell/haswell.h> +#include <cpu/intel/haswell/haswell.h> +#include <elog.h> + +/* Include EC functions */ +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +/* Codec enable: GPIO45 */ +#define GPIO_PP3300_CODEC_EN 45 +/* GPIO46 controls the WLAN_DISABLE_L signal. */ +#define GPIO_WLAN_DISABLE_L 46 +#define GPIO_LTE_DISABLE_L 59 + +static u8 mainboard_smi_ec(void) +{ + u8 cmd = google_chromeec_get_event(); + u32 pm1_cnt; + +#if CONFIG_ELOG_GSMI + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, get_pmbase() + PM1_CNT); + break; + } + + return cmd; +} + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0); + } +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case ACPI_S3: + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Prevent leak from standby rail to WLAN rail in S3. */ + set_gpio(GPIO_WLAN_DISABLE_L, 0); + set_gpio(GPIO_PP3300_CODEC_EN, 0); + /* Disable LTE */ + set_gpio(GPIO_LTE_DISABLE_L, 0); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case ACPI_S4: + case ACPI_S5: + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Prevent leak from standby rail to WLAN rail in S5. */ + set_gpio(GPIO_WLAN_DISABLE_L, 0); + set_gpio(GPIO_PP3300_CODEC_EN, 0); + /* Disable LTE */ + set_gpio(GPIO_LTE_DISABLE_L, 0); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); + break; + } + + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0); +} + + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + mainboard_finalized = 1; + break; + case APM_CNT_ACPI_ENABLE: + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + break; + case APM_CNT_ACPI_DISABLE: + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); + break; + } + return 0; +} diff --git a/src/mainboard/google/slippy/thermal.h b/src/mainboard/google/slippy/thermal.h new file mode 100644 index 0000000..a2f8e71 --- /dev/null +++ b/src/mainboard/google/slippy/thermal.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Power level to set when EC requests throttle */ +#define EC_THROTTLE_POWER_LIMIT 12 /* 12W */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 99 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif diff --git a/src/mainboard/google/slippy/variant.h b/src/mainboard/google/slippy/variant.h new file mode 100644 index 0000000..fe8b5e1 --- /dev/null +++ b/src/mainboard/google/slippy/variant.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARAINT_H + +void variant_romstage_entry(unsigned long bist); + +#endif diff --git a/src/mainboard/google/slippy/variants/falco/Makefile.inc b/src/mainboard/google/slippy/variants/falco/Makefile.inc new file mode 100644 index 0000000..aee33f9 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 (RAM_ID=000) +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 (RAM_ID=001) +SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 (RAM_ID=010) +SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only (RAM_ID=011) +SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only (RAM_ID=100) +SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only (RAM_ID=101) +SPD_SOURCES += Samsung_M471B5674QH0 # 4GB / CH0 + CH1 (RAM_ID=110) +SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111) + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb new file mode 100644 index 0000000..cdf47cf --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -0,0 +1,125 @@ +chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) + register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) + register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 1 + register "pcie_port_force_aspm" = "0x01" + + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013e0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/slippy/variants/falco/gma.c b/src/mainboard/google/slippy/variants/falco/gma.c new file mode 100644 index 0000000..19f467c --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/gma.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <stdlib.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <delay.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <smbios.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> + +#include <cpu/x86/tsc.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <edid.h> +#include <drivers/intel/gma/i915.h> +#include <northbridge/intel/haswell/haswell.h> +#include <variant/mainboard.h> + +/* + * Here is the rough outline of how we bring up the display: + * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD + * 2. Source determines video mode by reading DPCD receiver capability field + * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD + * 0000Dh). + * 3. Sink replies DPCD receiver capability field. + * 4. Source starts EDID read thru I2C-over-AUX. + * 5. Sink replies EDID thru I2C-over-AUX. + * 6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication + * method to use and writes DPCD link configuration field (DPCD 00100h to + * 0010Ah) including eDP configuration set (DPCD 0010Ah). + * 7. Source starts link training. Sink does clock recovery and equalization. + * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). + * 9. Sink replies DPCD link status field. If main link is not stable, Source + * repeats Step 7. + * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video + * parameters and recovers stream clock. + * 11. Source sends video data. + */ + +/* how many bytes do we need for the framebuffer? + * Well, this gets messy. To get an exact answer, we have + * to ask the panel, but we'd rather zero the memory + * and set up the gtt while the panel powers up. So, + * we take a reasonable guess, secure in the knowledge that the + * MRC has to overestimate the number of bytes used. + * 8 MiB is a very safe guess. There may be a better way later, but + * fact is, the initial framebuffer is only very temporary. And taking + * a little long is ok; this is done much faster than the AUX + * channel is ready for IO. + */ +#define FRAME_BUFFER_BYTES (8*MiB) +/* how many 4096-byte pages do we need for the framebuffer? + * There are hard ways to get this, and easy ways: + * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 + * on this chip (and in fact every Intel graphics chip we've seen). + */ +#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) + +static int i915_init_done = 0; + +/* fill the palette. */ +static void palette(void) +{ + int i; + unsigned long color = 0; + + for(i = 0; i < 256; i++, color += 0x010101){ + gtt_write(_LGC_PALETTE_A + (i << 2),color); + } +} + +void mainboard_train_link(struct intel_dp *intel_dp) +{ + u8 read_val; + u8 link_status[DP_LINK_STATUS_SIZE]; + + gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); + gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH |0x80000011); + + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); + intel_dp_get_lane_count(intel_dp, &read_val); + intel_dp_set_training_lane0(intel_dp, DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); + intel_dp_get_link_status(intel_dp, link_status); + + gtt_write(DP_TP_CTL(intel_dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); + + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); + intel_dp_get_link_status(intel_dp, link_status); + intel_dp_get_lane_align_status(intel_dp, &read_val); + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); +} + +#define TEST_GFX 0 + +#if TEST_GFX +static void test_gfx(struct intel_dp *dp) +{ + int i; + + /* This is a sanity test code which fills the screen with two bands -- + green and blue. It is very useful to ensure all the initializations + are made right. Thus, to be used only for testing, not otherwise + */ + for (i = 0; i < (dp->edid.va - 4); i++) { + u32 *l; + int j; + u32 tcolor = 0x0ff; + for (j = 0; j < (dp->edid.ha-4); j++) { + if (j == (dp->edid.ha/2)) { + tcolor = 0xff00; + } + l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor)); + memcpy(l,&tcolor,sizeof(tcolor)); + } + } +} +#else +static void test_gfx(struct intel_dp *dp) {} +#endif + + +void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) +{ + u32 ddi_pll_sel = 0; + + switch (intel_dp->link_bw) { + case DP_LINK_BW_1_62: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; + break; + case DP_LINK_BW_2_7: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; + break; + case DP_LINK_BW_5_4: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; + break; + default: + printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); + return; + } + + gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); +} + +int panel_lightup(struct intel_dp *dp, unsigned int init_fb) +{ + int i; + int edid_ok; + int pixels = FRAME_BUFFER_BYTES/64; + + void runio(struct intel_dp *dp); + + dp->gen = 8; // This is gen 8 which we believe is Haswell + dp->is_haswell = 1; + dp->DP = 0x2; + /* These values are used for training the link */ + dp->lane_count = 2; + dp->link_bw = DP_LINK_BW_2_7; + dp->pipe = PIPE_A; + dp->port = PORT_A; + dp->plane = PLANE_A; + dp->clock = 160000; + dp->pipe_bits_per_pixel = 32; + dp->type = INTEL_OUTPUT_EDP; + dp->output_reg = DP_A; + /* observed from YABEL. */ + dp->aux_clock_divider = 0xe1; + dp->precharge = 3; + + /* 1. Normal mode: Set the first page to zero and make + all GTT entries point to the same page + 2. Developer/Recovery mode: We do not zero out all + the pages pointed to by GTT in order to avoid wasting time */ + if (init_fb){ + set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 4096); + memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096); + } else { + set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0); + memset((void*)dp->graphics, 0, 4096); + } + + dp->address = 0x50; + + if ( !intel_dp_get_dpcd(dp) ) + goto fail; + + intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); + for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ + if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, + 0x50, &dp->rawedid[i]) < 0) + break; + dp->edidlen++; + } + + edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); + printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); + + compute_display_params(dp); + + intel_ddi_set_pipe_settings(dp); + + runio(dp); + + palette(); + + pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; + printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); + + test_gfx(dp); + + set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); + i915_init_done = 1; + return i915_init_done; + +fail: + printk(BIOS_SPEW, "Graphics could not be started;"); + printk(BIOS_SPEW, "Returning.\n"); + return 0; +} diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c new file mode 100644 index 0000000..790d501 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000e, // Number of jacks (NID entries) + + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010), + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + // group 1, front left/right + // no connector, no jack detect + // speaker out, analog + // fixed function, internal + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC2 PORTF */ + // group 1, cap 1 + // black, jack detect + // mic in, analog + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x19, 0x03a71011), + + /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* Pin Complex (NID 0x1d) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, internal + AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + // group1, + // black, jack detect + // HPOut, 1/8 stereo + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/slippy/variants/falco/i915io.c b/src/mainboard/google/slippy/variants/falco/i915io.c new file mode 100644 index 0000000..d51cb43 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/i915io.c @@ -0,0 +1,125 @@ +/* +* This file is part of the coreboot project. +* +* Copyright 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +/* This code was originally generated using an i915tool program. It has been + * improved by hand. + */ + +#include <stdint.h> +#include <console/console.h> +#include <delay.h> +#include <drivers/intel/gma/i915.h> +#include <arch/io.h> +#include <variant/mainboard.h> + +/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */ +void runio(struct intel_dp *dp); + +void runio(struct intel_dp *dp) +{ + u8 read_val; + + intel_dp_wait_panel_power_control(0xabcd0008); + + /* vbios spins at this point. Some haswell weirdness? */ + intel_dp_wait_panel_power_control(0xabcd0008); + + /* This should be a function like intel_panel_enable_backlight + However, we are not sure how the value 0x3a9 comes up. + It has to do something with PWM frequency */ + gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE); + + gtt_write(DEIIR,0x00008000); + intel_dp_wait_reg(DEIIR, 0x00000000); + + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + + intel_dp_sink_dpms(dp, 0); + + intel_dp_get_max_downspread(dp, &read_val); + + intel_dp_set_m_n_regs(dp); + + intel_dp_set_resolution(dp); + + gtt_write(PIPESRC(dp->pipe),dp->pipesrc); + gtt_write(PIPECONF(dp->transcoder),0x00000000); + gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000); + + mainboard_set_port_clk_dp(dp); + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888); + gtt_write(DEIIR,0x00000080); + + gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags); + gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN); + + intel_dp_wait_panel_power_control(0xabcd000a); + + /* what is this doing? Not sure yet. */ + intel_dp_i2c_write(dp, 0x0); + intel_dp_i2c_read(dp, &read_val); + intel_dp_i2c_write(dp, 0x04); + intel_dp_i2c_read(dp, &read_val); + intel_dp_i2c_write(dp, 0x7e); + intel_dp_i2c_read(dp, &read_val); + + /* this needs to be a call to a function */ + gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091); + gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); + gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091); + + /* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */ + gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x0001000a); + gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0 << 16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa << 0)|0x07d0000a); + + intel_dp_set_bw(dp); + intel_dp_set_lane_count(dp); + + mainboard_train_link(dp); + + /* need a function: intel_ddi_set_tp or similar */ + gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE); + gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL); + + gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL1,0x80000000); + + /* some of this is not needed. */ + gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE ); + + gtt_write(SDEIIR,0x00000000); + gtt_write(DEIIR,0x00000000); + gtt_write(DEIIR,0x00008000); + intel_dp_wait_reg(DEIIR, 0x00000000); + + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + gtt_write(PIPESRC(dp->pipe),dp->pipesrc); + + gtt_write(DEIIR,0x00000080); + intel_dp_wait_reg(DEIIR, 0x00000000); + + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + + gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON); + + gtt_write(SDEIIR,0x00000000); + gtt_write(SDEIIR,0x00000000); + gtt_write(DEIIR,0x00000000); +} diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..417dbfe --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (CTPA) + { + Name (_HID, "CYAP0000") + Name (_DDN, "Cypress Touchpad") + Name (_UID, 3) + Name (ISTP, 1) // Touchpad + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x67, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0" // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + + // Allow device to power off in S0 + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h new file mode 100644 index 0000000..c35b81e --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef FALCO_GPIO_H +#define FALCO_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_UNUSED, /* 42: UNUSED */ + LP_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + LP_GPIO_UNUSED, /* 44: UNUSED */ + LP_GPIO_UNUSED, /* 45: UNUSED */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_UNUSED, /* 49: UNUSED */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_INPUT, /* 51: ALS_INT_L */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX (PIRQV) */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX (PIRQW) */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_UNUSED, /* 57: UNUSED */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_UNUSED, /* 72: UNUSED */ + LP_GPIO_UNUSED, /* 73: UNUSED */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/mainboard.h b/src/mainboard/google/slippy/variants/falco/include/variant/mainboard.h new file mode 100644 index 0000000..6329a27 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/include/variant/mainboard.h @@ -0,0 +1,21 @@ +/* +* This file is part of the coreboot project. +* +* Copyright 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __MAINBOARD_H_ +#define __MAINBOARD_H_ +void mainboard_train_link(struct intel_dp *intel_dp); +void mainboard_set_port_clk_dp(struct intel_dp *intel_dp); + +#endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c new file mode 100644 index 0000000..8254bc2 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <variant/gpio.h> +#include "../../variant.h" + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +/* Copy SPD data for on-board memory */ +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + char *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < + ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < sizeof(peid->spd_data[0])) + die("Missing SPD data."); + + /* Index 0-2,6 are 4GB config with both CH0 and CH1 + * Index 3-5,7 are 2GB config with CH0 only + */ + switch (spd_index) { + case 3: case 4: case 5: case 7: + peid->dimm_channel1_disabled = 3; + } + + memcpy(peid->spd_data[0], + spd_file + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); +} + +void variant_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .ec_present = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + // Enable 2x refresh mode + .ddr_refresh_2x = 1, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0064, 1, 0, /* P0: Port A, CN8 */ + USB_PORT_BACK_PANEL }, + { 0x0052, 1, 0, /* P1: Port B, CN9 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_INTERNAL }, + { 0x0123, 1, 3, /* P7: USB2 Port */ + USB_PORT_INTERNAL }, + }, + .usb3_ports = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN8 */ + { 1, 0 }, /* P2; Port B, CN9 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + .copy_spd = copy_spd, + }; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex new file mode 100644 index 0000000..eb41f0b --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex @@ -0,0 +1,17 @@ +# Elpida EDJ4216EFBG-GN-F +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex b/src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex new file mode 100644 index 0000000..c2a23cd --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex @@ -0,0 +1,17 @@ +# Samsung M471B5674QH0-YK0 (K4B4G1646Q) +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 11 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/leon/Makefile.inc b/src/mainboard/google/slippy/variants/leon/Makefile.inc new file mode 100644 index 0000000..5d8d9d3 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/Makefile.inc @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 +SPD_SOURCES += Samsung_K4B4G1646Q # 2: 4GB / CH0 + Ch1 +SPD_SOURCES += Micron_4KTF25664HZ # 3: space holder +SPD_SOURCES += Micron_4KTF25664HZ # 4: space holder +SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 +SPD_SOURCES += Samsung_K4B4G1646Q # 6: 2GB / CH0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb new file mode 100644 index 0000000..b0edb7f --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -0,0 +1,157 @@ +chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 1 + register "pcie_port_force_aspm" = "0x01" + + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on # SMBus + chip drivers/i2c/rtd2132 + # Panel Power Timings (1 ms units) + # Note: the panel Tx timings are very + # different from the LVDS bridge + # Tx timing settings. Below is a mapping + # for RTD2132 -> Panel timings. + # T1 = T2 + # T2 = T8 + T10 + T12 + # T3 = T14 + # T4 = T15 + # T5 = T9 + T11 + T13 + # T6 = T3 + # T7 = T4 + register "t1" = "0x14" + register "t2" = "0xdc" + register "t3" = "0x0e" + register "t4" = "0x02" + register "t5" = "0xdc" + register "t6" = "0x14" + register "t7" = "0x208" + # LVDS Swap settings are normal. + register "lvds_swap" = "0" + # Enable Spread Sprectrum at 0.5% + register "sscg_percent" = "0x05" + device i2c 35 on end # (8bit address: 0x6A) + end # rtd2132 + end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c new file mode 100644 index 0000000..39a5c78 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000e, // Number of jacks (NID entries) + + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - Internal Mic */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010), + + /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ + // group 1, cap 0 + // no connector, no jack detect + // speaker out, analog + // fixed function, internal + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ + // group2, cap 0 + // black, jack detect + // Mic in, 3.5mm Jack + // connector, External left panel + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020), + + /* Pin Complex (NID 0x1A) LINE1 - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* Pin Complex (NID 0x1B) LINE2 - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* Pin Complex (NID 0x1D) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, Internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ + // group2, cap 1 + // black, jack detect + // HPOut, 3.5mm Jack + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x03211021), + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..4afe310 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + + // There is no GPIO for LID, the EC pulses WAKE# pin instead. + // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE + Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (CTPA) + { + Name (_HID, "CYAP0000") + Name (_DDN, "Cypress Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x67, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0" // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h new file mode 100644 index 0000000..d808899 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LEON_GPIO_H +#define LEON_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_UNUSED, /* 43: UNUSED */ + LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ + LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_UNUSED, /* 49: UNUSED */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_UNUSED, /* 51: ALS_INT_L */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ + LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_END +}; + +#endif \ No newline at end of file diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c new file mode 100644 index 0000000..c9cf07b --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <variant/gpio.h> +#include "../../variant.h" + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +/* Copy SPD data for on-board memory */ +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + char *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* Limiting to a single dimm for 2GB configuration + * Identified by bit 3 + */ + if (spd_index & 0x4) + peid->dimm_channel1_disabled = 3; + + if (spd_file_len < + ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < sizeof(peid->spd_data[0])) + die("Missing SPD data."); + + memcpy(peid->spd_data[0], + spd_file + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); +} + +void variant_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .ec_present = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, /* P1: Port B, CN11 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, + }, + .usb3_ports = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN11 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + .copy_spd = copy_spd, + }; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex b/src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex new file mode 100644 index 0000000..d6b0770 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646Q-HYK0 +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/google/slippy/variants/peppy/Makefile.inc b/src/mainboard/google/slippy/variants/peppy/Makefile.inc new file mode 100644 index 0000000..576af04 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 +SPD_SOURCES += Elpida_EDJ4216EFBG # 2: 4GB / CH0 + CH1 +SPD_SOURCES += Micron_4KTF25664HZ # 3: Reserved / place holder +SPD_SOURCES += Micron_4KTF25664HZ # 4: 2GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 + CH1 +SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb new file mode 100644 index 0000000..e9875a6 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -0,0 +1,129 @@ +chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/slippy/variants/peppy/gma.c b/src/mainboard/google/slippy/variants/peppy/gma.c new file mode 100644 index 0000000..afdb4d6 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/gma.c @@ -0,0 +1,272 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <stdlib.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <delay.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <smbios.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> + +#include <cpu/x86/tsc.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <edid.h> +#include <drivers/intel/gma/i915.h> +#include <northbridge/intel/haswell/haswell.h> +#include <variant/mainboard.h> + +/* + * Here is the rough outline of how we bring up the display: + * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD + * 2. Source determines video mode by reading DPCD receiver capability field + * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD + * 0000Dh). + * 3. Sink replies DPCD receiver capability field. + * 4. Source starts EDID read thru I2C-over-AUX. + * 5. Sink replies EDID thru I2C-over-AUX. + * 6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication + * method to use and writes DPCD link configuration field (DPCD 00100h to + * 0010Ah) including eDP configuration set (DPCD 0010Ah). + * 7. Source starts link training. Sink does clock recovery and equalization. + * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh). + * 9. Sink replies DPCD link status field. If main link is not stable, Source + * repeats Step 7. + * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video + * parameters and recovers stream clock. + * 11. Source sends video data. + */ + +/* how many bytes do we need for the framebuffer? + * Well, this gets messy. To get an exact answer, we have + * to ask the panel, but we'd rather zero the memory + * and set up the gtt while the panel powers up. So, + * we take a reasonable guess, secure in the knowledge that the + * MRC has to overestimate the number of bytes used. + * 8 MiB is a very safe guess. There may be a better way later, but + * fact is, the initial framebuffer is only very temporary. And taking + * a little long is ok; this is done much faster than the AUX + * channel is ready for IO. + */ +#define FRAME_BUFFER_BYTES (8*MiB) +/* how many 4096-byte pages do we need for the framebuffer? + * There are hard ways to get this, and easy ways: + * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096 + * on this chip (and in fact every Intel graphics chip we've seen). + */ +#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096)) + + +static int i915_init_done = 0; + +/* fill the palette. */ +static void palette(void) +{ + int i; + unsigned long color = 0; + + for(i = 0; i < 256; i++, color += 0x010101){ + gtt_write(_LGC_PALETTE_A + (i << 2),color); + } +} + +void mainboard_train_link(struct intel_dp *intel_dp) +{ + u8 read_val; + u8 link_status[DP_LINK_STATUS_SIZE]; + + gtt_write(DP_TP_CTL(intel_dp->port), + DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE); + gtt_write(DDI_BUF_CTL_A, + DDI_BUF_CTL_ENABLE| + DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011); + + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, + DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE | + DP_SYMBOL_ERROR_COUNT_BOTH); + + intel_dp_set_training_lane0(intel_dp, + DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0); + intel_dp_get_link_status(intel_dp, link_status); + + gtt_write(DP_TP_CTL(intel_dp->port), + DP_TP_CTL_ENABLE | + DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2); + + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 | + DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); + intel_dp_get_link_status(intel_dp, link_status); + intel_dp_get_lane_align_status(intel_dp, &read_val); + intel_dp_get_training_pattern(intel_dp, &read_val); + intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE | + DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH); +} + +/* This variable controls whether the test_gfx function below puts up + * color bars or not. In previous revs we ifdef'd the test_gfx function out + * but it's handy, especially when using a JTAG debugger + * to be able to enable and disable a test graphics. + */ +int show_test = 0; + +static void test_gfx(struct intel_dp *dp) +{ + int i; + + if (!show_test) + return; + /* This is a sanity test code which fills the screen with two bands -- + green and blue. It is very useful to ensure all the initializations + are made right. Thus, to be used only for testing, not otherwise + */ + + for (i = 0; i < (dp->edid.mode.va - 4); i++) { + u32 *l; + int j; + u32 tcolor = 0x0ff; + for (j = 0; j < (dp->edid.mode.ha-4); j++) { + if (j == (dp->edid.mode.ha/2)) { + tcolor = 0xff00; + } + l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor)); + memcpy(l,&tcolor,sizeof(tcolor)); + } + } + printk(BIOS_SPEW, "sleep 10\n"); + delay(10); +} + +void mainboard_set_port_clk_dp(struct intel_dp *intel_dp) +{ + u32 ddi_pll_sel = 0; + + switch (intel_dp->link_bw) { + case DP_LINK_BW_1_62: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; + break; + case DP_LINK_BW_2_7: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; + break; + case DP_LINK_BW_5_4: + ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; + break; + default: + printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw); + return; + } + + gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel); +} + +int panel_lightup(struct intel_dp *dp, unsigned int init_fb) +{ + int i; + int edid_ok; + int pixels = FRAME_BUFFER_BYTES/64; + + gtt_write(PCH_PP_CONTROL,0xabcd000f); + delay(1); + + void runio(struct intel_dp *dp); + /* hard codes -- stuff you can only know from the mainboard */ + dp->gen = 8; // This is gen 8 which we believe is Haswell + dp->is_haswell = 1; + dp->DP = 0x2; + dp->pipe = PIPE_A; + dp->port = PORT_A; + dp->plane = PLANE_A; + dp->pipe_bits_per_pixel = 24; + dp->type = INTEL_OUTPUT_EDP; + dp->output_reg = DP_A; + /* observed from YABEL. */ + dp->aux_clock_divider = 0xe1; + dp->precharge = 3; + + /* 1. Normal mode: Set the first page to zero and make + all GTT entries point to the same page + 2. Developer/Recovery mode: Set up a tasteful color + so people know we are alive. */ + if (init_fb || show_test) { + set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, + 4096); + memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096); + } else { + set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0); + memset((void*)dp->graphics, 0, 4096); + } + + dp->address = 0x50; + + if ( !intel_dp_get_dpcd(dp) ) + goto fail; + + intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL); + for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){ + if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ, + 0x50, &dp->rawedid[i]) < 0) + break; + dp->edidlen++; + } + + edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid); + + printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); + + compute_display_params(dp); + + printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n", + dp->edid.mode.pixel_clock, dp->edid.link_clock); + + intel_ddi_set_pipe_settings(dp); + + runio(dp); + + palette(); + + pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4; + printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va); + test_gfx(dp); + + set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics); + i915_init_done = 1; + return 1; + +fail: + printk(BIOS_SPEW, "Graphics could not be started;"); + /* unclear we will *ever* want to do this. */ + if (0){ + printk(BIOS_SPEW, "Turn off power and wait ..."); + gtt_write(PCH_PP_CONTROL,0xabcd0000); + udelay(600000); + gtt_write(PCH_PP_CONTROL,0xabcd000f); + } + printk(BIOS_SPEW, "Returning.\n"); + return 0; +} diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c new file mode 100644 index 0000000..a5ec9bb --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000e, // Number of jacks (NID entries) + + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ + // group 1, cap 0 + // no connector, no jack detect + // speaker out, analog + // fixed function, internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ + // group2, cap 0 + // black, jack detect + // Mic in, 3.5mm Jack + // connector, External left panel + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020), + + /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */ + // group 1, cap 1 + // no connector, no jack detect + // mic in, analog connection + // Fixed function, internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x1a, 0x90a70111), + + /* Pin Complex (NID 0x1B) LINE2 - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* Pin Complex (NID 0x1D) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, Internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ + // group2, cap 1 + // black, jack detect + // HPOut, 3.5mm Jack + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x03211021), + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/slippy/variants/peppy/i915io.c b/src/mainboard/google/slippy/variants/peppy/i915io.c new file mode 100644 index 0000000..6cf2d0e --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/i915io.c @@ -0,0 +1,139 @@ +/* +* This file is part of the coreboot project. +* +* Copyright 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <stdint.h> +#include <console/console.h> +#include <delay.h> +#include <drivers/intel/gma/i915.h> +#include <arch/io.h> +#include <variant/mainboard.h> + +void runio(struct intel_dp *dp, int verbose); +void runio(struct intel_dp *dp, int verbose) +{ + u8 read_val; + gtt_write(DDI_BUF_CTL_A, + DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED + |0x00000091); + + intel_prepare_ddi(); + + gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL1,0x80000000); + + gtt_write(DEIIR,0x00008000); + intel_dp_wait_reg(DEIIR, 0x00000000); + gtt_write(DSPSTRIDE(dp->plane), dp->stride); + gtt_write(DSPADDR(dp->plane), 0x00000000); + + printk(BIOS_SPEW, "DP_SET_POWER"); + + intel_dp_sink_dpms(dp, 0); + + intel_dp_set_m_n_regs(dp); + + intel_dp_get_max_downspread(dp, &read_val); + + intel_dp_set_resolution(dp); + + gtt_write(PIPESRC(dp->pipe),dp->pipesrc); + gtt_write(PIPECONF(dp->transcoder),0x00000000); + gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000); + + mainboard_set_port_clk_dp(dp); + + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888); + + gtt_write(DEIIR,0x00000080); + intel_dp_wait_reg(DEIIR, 0x00000000); + + /* There is some reason we removed these three calls from + * slippy/gma.c -- I dont remember why!! */ + gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos); + gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl); + gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz); + + gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags); + gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN); + + /* what is this doing? Not sure yet. But we don't seem to be + * able to live without it.*/ + intel_dp_i2c_write(dp, 0x0); + intel_dp_i2c_read(dp, &read_val); + intel_dp_i2c_write(dp, 0x04); + intel_dp_i2c_read(dp, &read_val); + intel_dp_i2c_write(dp, 0x7e); + intel_dp_i2c_read(dp, &read_val); + + gtt_write(DDI_BUF_CTL_A, + DDI_BUF_IS_IDLE| + DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED + |0x00000091); + + gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001); + gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | + DP_TP_CTL_ENHANCED_FRAME_ENABLE); + + gtt_write(DDI_BUF_CTL_A, + DDI_BUF_CTL_ENABLE| + /* another undocumented setting. Surprised? */ 0x40000 | + DDI_BUF_IS_IDLE|DDI_A_4_LANES| + DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED| + 0x80040091); + + intel_dp_set_bw(dp); + + intel_dp_set_lane_count(dp); + + mainboard_train_link(dp); + + gtt_write(DP_TP_CTL(dp->port), + DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | + DP_TP_CTL_LINK_TRAIN_IDLE); + + gtt_write(DP_TP_CTL(dp->port), + DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | + DP_TP_CTL_LINK_TRAIN_NORMAL); + + gtt_write(BLC_PWM_CPU_CTL,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9); + gtt_write(BLC_PWM_PCH_CTL1,0x80000000); + + /* some of this is not needed. But with a total lack of docs, well ...*/ + gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE ); + + gtt_write(SDEIIR,0x00000000); + gtt_write(DEIIR,0x00000000); + gtt_write(DEIIR,0x00008000); + intel_dp_wait_reg(DEIIR, 0x00000000); + + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + gtt_write(PIPESRC(dp->pipe),dp->pipesrc); + + gtt_write(DEIIR,0x00000080); + intel_dp_wait_reg(DEIIR, 0x00000000); + + gtt_write(DSPSTRIDE(dp->plane),dp->stride); + gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + + gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON); + + gtt_write(SDEIIR,0x00000000); + gtt_write(SDEIIR,0x00000000); + gtt_write(DEIIR,0x00000000); + +} diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..cc0c688 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 1) + Name (ISTP, 1) // Touchpad + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0" // ResourceSource + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + } + Device (CTPA) + { + Name (_HID, "CYAP0000") + Name (_DDN, "Cypress Touchpad") + Name (_UID, 3) + Name (ISTP, 1) // Touchpad + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x67, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0" // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + + // Allow device to power off in S0 + Name (_S0W, 4) + } +} +Scope (\_SB.PCI0.I2C1) +{ + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ + Name (GPIO, 25) + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4a, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1" // ResourceSource + ) + + // GPIO54 (ball L3) is PIRQW: PIRQL_GSI + PIRQL - PIRQW = PIRQW_GSI + // 27 + 3 - 14 = 38 + Interrupt (ResourceConsumer, Edge, ActiveLow) { 38 } + }) + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} \ No newline at end of file diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h new file mode 100644 index 0000000..8eb3da9 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PEPPY_GPIO_H +#define PEPPY_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_UNUSED, /* 43: UNUSED */ + LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ + LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_UNUSED, /* 49: UNUSED */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_INPUT, /* 51: ALS_INT_L */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ + LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/mainboard.h b/src/mainboard/google/slippy/variants/peppy/include/variant/mainboard.h new file mode 100644 index 0000000..6329a27 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/mainboard.h @@ -0,0 +1,21 @@ +/* +* This file is part of the coreboot project. +* +* Copyright 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __MAINBOARD_H_ +#define __MAINBOARD_H_ +void mainboard_train_link(struct intel_dp *intel_dp); +void mainboard_set_port_clk_dp(struct intel_dp *intel_dp); + +#endif diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c new file mode 100644 index 0000000..4a39101 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> +#include "ec/google/chromeec/ec.h" +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <variant/gpio.h> +#include "../../onboard.h" +#include "../../variant.h" + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +/* Copy SPD data for on-board memory */ +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + char *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + switch (google_chromeec_get_board_version()) { + case PEPPY_BOARD_VERSION_PROTO: + /* Index 0 is 2GB config with CH0 only. */ + if (spd_index == 0) + peid->dimm_channel1_disabled = 3; + break; + + case PEPPY_BOARD_VERSION_EVT: + default: + /* Index 0-2 are 4GB config with both CH0 and CH1. + * Index 4-6 are 2GB config with CH0 only. */ + if (spd_index > 3) + peid->dimm_channel1_disabled = 3; + break; + } + + if (spd_file_len < + ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < sizeof(peid->spd_data[0])) + die("Missing SPD data."); + + memcpy(peid->spd_data[0], + spd_file + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); +} + +void variant_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .ec_present = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 0, /* P1: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, 2, /* P4: Port B, CN6 */ + USB_PORT_BACK_PANEL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_FLEX }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, + }, + .usb3_ports = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P2; */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + .copy_spd = copy_spd, + }; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex new file mode 100644 index 0000000..eb41f0b --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex @@ -0,0 +1,17 @@ +# Elpida EDJ4216EFBG-GN-F +92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE +45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/wolf/Makefile.inc b/src/mainboard/google/slippy/variants/wolf/Makefile.inc new file mode 100644 index 0000000..0c860bf --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/Makefile.inc @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1 +SPD_SOURCES += Samsung_K4B4G1646B # 2: 4GB / CH0 + CH1 +SPD_SOURCES += Micron_4KTF25664HZ # 3: 2GB / CH0 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4: 2GB / CH0 +SPD_SOURCES += Samsung_K4B4G1646B # 4: 2GB / CH0 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb new file mode 100644 index 0000000..7655c41 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -0,0 +1,130 @@ +chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Disable DisplayPort C Hotplug + register "gpu_dp_c_hotplug" = "0x00" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) + register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) + register "gpu_panel_power_down_delay" = "500" # 50ms (T10) + register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + + register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "ide_legacy_combined" = "0x0" + register "sata_ahci" = "0x1" + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + register "sio_acpi_mode" = "1" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 1 + register "pcie_port_force_aspm" = "0x01" + + # Route all USB ports to XHCI per default + register "xhci_default" = "1" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c new file mode 100644 index 0000000..b043bf5 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000e, // Number of jacks (NID entries) + + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC - interior mobile lid */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a61010), + + /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ + // group 1, cap 0 + // no connector, no jack detect + // speaker out, analog + // fixed function, internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ + // group2, cap 0 + // black, jack detect + // Mic in, 3.5mm Jack + // connector, External left panel + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11020), + + /* Pin Complex (NID 0x1A) LINE1 - Internal Mic */ + // group 1, cap 1 + // no connector, no jack detect + // mic in, analog connection + // Fixed function, internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x1a, 0x90a70111), + + /* Pin Complex (NID 0x1B) LINE2 - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* Pin Complex (NID 0x1D) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, Internal, Location N/A + AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ + // group2, cap 1 + // black, jack detect + // HPOut, 3.5mm Jack + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x03211021), + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..335077c --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + + // There is no GPIO for LID, the EC pulses WAKE# pin instead. + // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE + Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (CTPA) + { + Name (_HID, "CYAP0000") + Name (_DDN, "Cypress Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x67, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0" // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} \ No newline at end of file diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h new file mode 100644 index 0000000..fe2b314 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef WOLF_GPIO_H +#define WOLF_GPIO_H + +struct pch_lp_gpio_map; + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_UNUSED, /* 43: UNUSED */ + LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ + LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_UNUSED, /* 49: UNUSED */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_UNUSED, /* 51: UNUSED */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ + LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_END +}; + +#endif \ No newline at end of file diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c new file mode 100644 index 0000000..4bdde31 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <cbfs.h> +#include <console/console.h> +#include <cpu/intel/haswell/haswell.h> +#include "ec/google/chromeec/ec.h" +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <variant/gpio.h> +#include "../../variant.h" + +const struct rcba_config_instruction rcba_config[] = { + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP PCIE INTA -> PIRQA + * D29IP_E1P EHCI INTA -> PIRQD + * D20IP_XHCI XHCI INTA -> PIRQC (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQG + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + */ + + /* Device interrupt pin register (board specific) */ + RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), + RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP)), + RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), + RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), + RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + + /* Device interrupt route registers */ + RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ + RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ + RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ + RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ + RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ + RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ + RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ + RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ + + /* Disable unused devices (board specific) */ + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +/* Copy SPD data for on-board memory */ +static void copy_spd(struct pei_data *peid) +{ + const int gpio_vector[] = {13, 9, 47, -1}; + int spd_index = get_gpios(gpio_vector); + char *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "SPD index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < + ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < sizeof(peid->spd_data[0])) + die("Missing SPD data."); + + /* Index 0-2, are 4GB config with both CH0 and CH1 + * Index 3-5, are 2GB config with CH0 only + */ + switch (spd_index) { + case 3: case 4: case 5: + peid->dimm_channel1_disabled = 3; + } + + memcpy(peid->spd_data[0], + spd_file + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); +} + +void variant_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .ec_present = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, /* P0: Port A, CN10 */ + USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, /* P1: Port B, CN11 */ + USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ + USB_PORT_INTERNAL }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ + USB_PORT_MINI_PCIE }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ + USB_PORT_INTERNAL }, + { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ + USB_PORT_SKIP }, + { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ + USB_PORT_INTERNAL }, + { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ + USB_PORT_SKIP }, + }, + .usb3_ports = { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN11 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + .copy_spd = copy_spd, + }; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(&romstage_params); +} diff --git a/src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex new file mode 100644 index 0000000..7b09327 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex @@ -0,0 +1,17 @@ +# Hynix HMT425S6AFR6A-PBA +92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB +48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex new file mode 100644 index 0000000..cbe9e4f --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex @@ -0,0 +1,17 @@ +# Micron 4KTF25664HZ-1G6E1 +92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75 +34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45 +31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex b/src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex new file mode 100644 index 0000000..fb529d0 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646B-HYXX +92 11 0B 03 04 19 02 02 03 11 01 08 0C 00 3E 00 +69 78 69 3C 69 11 20 89 20 08 3C 3C 01 68 83 01 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 2A E3 +4D 34 37 31 42 35 36 37 34 42 48 30 2D 43 48 39 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF \ No newline at end of file

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New patch to review for coreboot: sb/intel/lynxpoint: add missing I2C ACPI SSCN/FMCN methods
by Matt DeVillier 27 Nov '16

27 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17620 -gerrit commit f1d148fc5a5dee30b42d1548d7f846fba10c91f8 Author: CoolStar <coolstarorganization(a)gmail.com> Date: Thu Jul 14 12:34:33 2016 -0700 sb/intel/lynxpoint: add missing I2C ACPI SSCN/FMCN methods The SSCN and FMCN methods provide the optimal HCNT/LCNT timing values to the driver, and are necessary when using I2C devices (eg, trackpad and touchscreen) in ACPI (vs PCI) mode. Add these methods using the timing values from Broadwell, which work for Haswell/Lynxpoint as well. TEST: build google/peppy with trackpad/touchscreen devices in ACPI mode, observe proper operation under Windows and Linux Change-Id: I25f07ac474b041358315530e5f391bb33d9c4d04 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 930a8ee..e4d8659 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -127,6 +127,9 @@ Device (SDMA) Name (_UID, 1) Name (_ADR, 0x00150000) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) + // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () { @@ -165,6 +168,9 @@ Device (I2C0) Name (_UID, 1) Name (_ADR, 0x00150001) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) + // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () {

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coreboot-gerrit November 2016