coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Makefile: Explicitly set C99 as language standard
by Paul Menzel 29 Nov '16

29 Nov '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17636 -gerrit commit f15ac90e17e897874955c6f6fd70f01be8fc0496 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Tue Nov 29 10:30:44 2016 +0100 Makefile: Explicitly set C99 as language standard Different compiler versions use a different C language standard. GCC 4.9 uses C89, while GCC 5.x uses C99 [1]. So explicitly set it to C99 as discussed on the mailing list in thread *[RFC] Setting C99 by default*. [1] https://www.coreboot.org/pipermail/coreboot/2016-November/082541.html Change-Id: If1569618f8044925ff72dcf3543480b34d4f90d6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index a193158..189de40 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -353,7 +353,7 @@ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h CPPFLAGS_common += -I3rdparty -CFLAGS_common += -pipe -g -nostdinc +CFLAGS_common += -pipe -g -nostdinc -std=c99 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time

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Patch set updated for coreboot: soc/skylake: Move IO decode range out from pch_lpc_init
by Boon Tiong Teo 29 Nov '16

29 Nov '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17337 -gerrit commit a3b1f120003ffeb9350e72ab49bffd17fbf7c81a Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Nov 10 01:21:23 2016 +0800 soc/skylake: Move IO decode range out from pch_lpc_init 1. Move existing IO decode range from pch_lpc_init to early stage before SIO init. 2. At the same time, enable SIO decode range (0x2e/0x2f) for platform which use super IO. Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/soc/intel/skylake/bootblock/bootblock.c | 1 + src/soc/intel/skylake/bootblock/pch.c | 27 ++++++++++++++++----------- src/soc/intel/skylake/include/soc/bootblock.h | 1 + 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index ea41b4b..93a031f 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -27,6 +27,7 @@ void bootblock_soc_early_init(void) bootblock_systemagent_early_init(); bootblock_pch_early_init(); bootblock_cpu_init(); + pch_early_iorange_init(); if (IS_ENABLED(CONFIG_UART_DEBUG)) pch_uart_init(); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 371dd63..6279cf2 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -95,17 +95,6 @@ static void pch_enable_lpc(void) /* Lookup device tree in romstage */ const struct device *dev; const config_t *config; - u16 lpc_en; - - /* IO Decode Range */ - lpc_en = COMA_RANGE | (COMB_RANGE << 4); - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); - - /* IO Decode Enable */ - lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); - pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); if (!dev || !dev->chip_info) @@ -272,6 +261,22 @@ static void enable_heci(void) pci_write_config8(dev, PCI_COMMAND, pcireg); } +void pch_early_iorange_init(void) +{ + /* Lookup device tree in romstage */ + u16 lpc_en; + + /* IO Decode Range */ + lpc_en = COMA_RANGE | (COMB_RANGE << 4); + pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en); + + /* IO Decode Enable */ + lpc_en = CNF1_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en); + pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en); +} + void pch_early_init(void) { /* diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 4895912..df81d3f 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -32,6 +32,7 @@ void pch_uart_init(void); void enable_smbus(void); void i2c_early_init(void); void pch_early_init(void); +void pch_early_iorange_init(void); void report_platform_info(void); void report_memory_config(void); void set_max_freq(void);

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New patch to review for coreboot: mainboard/intel/kblrvp: Revert back USB OC pin programming
by Barnali Sarkar 29 Nov '16

29 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17635 -gerrit commit 9239290b2ccae396a0734f4769e70efbb8a722b9 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Nov 29 12:05:28 2016 +0530 mainboard/intel/kblrvp: Revert back USB OC pin programming With CL:17570 USB OC pin programming is already initiated from devicetree.cb, hence removed from ramstage.c BUG=none BRANCH=none TEST=Build and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/mainboard/intel/kblrvp/ramstage.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index d33c967..bcd72bc 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -21,21 +21,10 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - size_t i; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Set proper OC for various USB ports*/ - u8 usb2_oc[] = {0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8}; - u8 usb3_oc[] = {0x0, 0x8, 0x8, 0x1, 0x8, 0x8}; - - for (i = 0; i < ARRAY_SIZE(usb2_oc); i++) - params->Usb2OverCurrentPin[i] = usb2_oc[i]; - - for (i = 0; i < ARRAY_SIZE(usb3_oc); i++) - params->Usb3OverCurrentPin[i] = usb3_oc[i]; } static void ioexpander_init(void *unused)

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Patch set updated for coreboot: soc/intel/skylake: Remove pad configuration size hardcoding
by Subrata Banik 29 Nov '16

29 Nov '16

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17571 -gerrit commit 77e48dff7fdb7d593a4df0cb90ec82efae8c162d Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Nov 23 00:54:47 2016 +0530 soc/intel/skylake: Remove pad configuration size hardcoding Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/gpio.c | 3 ++- src/soc/intel/skylake/include/soc/gpio.h | 2 ++ src/soc/intel/skylake/include/soc/gpio_defs.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5b9babf..6334b3e 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad) pad_relative = pad - comm->min; /* DW0 and DW1 regs are 4 bytes each. */ - return &regs[PAD_CFG_DW_OFFSET + pad_relative * 8]; + return &regs[PAD_CFG_DW_OFFSET + pad_relative * + GPIO_DWx_SIZE(GPIO_DWx_COUNT)]; } static void *gpio_hostsw_reg(gpio_t pad, size_t *bit) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index dd9b9a3..75d8abe 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -19,6 +19,8 @@ #include <soc/gpio_defs.h> +#define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x)) + #define CROS_GPIO_DEVICE_NAME "INT344B:00" #ifndef __ACPI__ diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 112db63..42a409b 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -33,6 +33,7 @@ #define GPIO_NUM_GROUPS 8 #define GPIO_MAX_NUM_PER_GROUP 24 +#define GPIO_DWx_COUNT 2 /* DW0 and DW1 */ /* * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */

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New patch to review for coreboot: mainboard/google/snappy: Tune i2c frequency to 400 Khz
by Wisley Chen 29 Nov '16

29 Nov '16

Wisley Chen (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17634 -gerrit commit 8d4f27af90d3aaffc5a677ec50b6eef12393d2ed Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Sun Nov 27 16:56:30 2016 +0800 mainboard/google/snappy: Tune i2c frequency to 400 Khz tune i2c devices clk for snappy: I2C0: audio I2C2: TPM H1 I2C3: elan touchscreen I2C4: elan touchpad I2C5: wacom digitizer BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.7kHz Rise Time 58.8ns Fall time 12.11ns TPM H1: Freq. 398.8kHz Rise Time 31.71ns Fall time 13.28ns elan touchscreen: Freq. 390.5kHz Rise Time 235.7ns Fall time 37.64ns elan touchpad: Freq. 393.7kHz Rise Time 288.8ns Fall time 51.67ns wacom digitizer: Freq. 388.8kHz Rise Time 124.1ns Fall time 21.10ns Change-Id: Ib2be9e1575d4962476423eafa80f9bb10ba40e17 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- .../google/reef/variants/snappy/devicetree.cb | 37 ++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 00df9bd..91e2e96 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -71,8 +71,41 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0" - # Enable I2C2 bus early for TPM access - register "i2c[2].early_init" = "1" + # Enable I2C0 for audio codec at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 22, + }" + + # Enable I2C2 bus early for TPM at 400kHz + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 40, + .fall_time_ns = 20, + }" + + # touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 70, + .fall_time_ns = 164, + }" + + # trackpad at 400kHz + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 20, + .fall_time_ns = 164, + }" + + # digitizer at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }" # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000"

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Patch set updated for coreboot: mainboard/reef: Shrink RW_MRC_CACHE to fit only one item
by Andrey Petrov 29 Nov '16

29 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17498 -gerrit commit 0e5393792ae4b537badd4cd87d827447e5e15e80 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 18 16:18:15 2016 -0800 mainboard/reef: Shrink RW_MRC_CACHE to fit only one item Now that variable and constant MRC cache are separated MRC cache stays static. Static cache is not to change unless memory is retrained from scratch. As result multiple cache entries are not required. Shrink RW_MRC_CACHE so that it is large enough to fit only one cache dataset, and update other sections offsets accordingly. Change-Id: I3565757987ca7c5d5788d3b76a9cdfbe2e216f2d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/google/reef/chromeos.fmd | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index c7e51ee..9a470fa 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -12,31 +12,31 @@ FLASH 16M { RO_UNUSED@0x1bc000 0x40000 } } - MISC_RW@0x400000 0x4a000 { - UNIFIED_MRC_CACHE@0x0 0x40000 { + MISC_RW@0x400000 0x2b000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x2f000 - RW_VAR_MRC_CACHE@0x3f000 0x1000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG@0x40000 0x4000 - RW_SHARED@0x44000 0x4000 { + RW_ELOG@0x21000 0x4000 + RW_SHARED@0x25000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x48000 0x2000 + RW_VPD@0x29000 0x2000 } - RW_SECTION_A@0x44a000 0x477800 { + RW_SECTION_A@0x42b000 0x477800 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x4677c0 RW_FWID_A@0x4777c0 0x40 } - RW_SECTION_B@0x8c1800 0x477800 { + RW_SECTION_B@0x8a2800 0x477800 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x4677c0 RW_FWID_B@0x4777c0 0x40 } - RW_NVRAM@0xd39000 0x6000 - RW_LEGACY(CBFS)@0xd3f000 0x200000 + RW_NVRAM@0xd1a000 0x6000 + RW_LEGACY(CBFS)@0xd20000 0x200000 BIOS_UNUSABLE@0xf3f000 0x40000 DEVICE_EXTENSION@0xf7f000 0x80000 # Currently, it is required that the BIOS region be a multiple of 8KiB.

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Patch set updated for coreboot: soc/intel/apollolake: Add save/restore variable MRC cache
by Andrey Petrov 29 Nov '16

29 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17237 -gerrit commit 616003797cc75e913de5c565c2c3c9063b6fac2a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 4 16:18:30 2016 -0700 soc/intel/apollolake: Add save/restore variable MRC cache Apollolake MRC cache is divided into two regions: constant and variable. Currently they are clubbed together. Since variable data changes across cold reboot it triggers invalidation of the whole cache region. This change declubs the data, adds routines to load/store variable data on flash. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I374519777abe9b9a1e6cceae5318decd405bb527 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ src/soc/intel/apollolake/romstage.c | 39 ++++++++++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d1d660b..092102c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -161,6 +161,10 @@ config CACHE_MRC_SETTINGS bool default y +config MRC_SETTINGS_VARIABLE_DATA + bool + default y + config FSP_M_ADDR hex default 0xfef40000 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index d623913..039b586 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -32,6 +32,7 @@ #include <fsp/memmap.h> #include <fsp/util.h> #include <soc/cpu.h> +#include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> @@ -47,6 +48,13 @@ static struct chipset_power_state power_state CAR_GLOBAL; +static const uint8_t hob_variable_guid[16] = { + 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, + 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, +}; + +static uint32_t fsp_version CAR_GLOBAL; + /* High Performance Event Timer Configuration */ #define P2SB_HPTC 0x60 #define P2SB_HPTC_ADDRESS_ENABLE (1 << 7) @@ -170,7 +178,8 @@ asmlinkage void car_stage_entry(void) bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); void *smm_base; - size_t smm_size; + size_t smm_size, var_size; + const void *new_var_data; uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -188,6 +197,15 @@ asmlinkage void car_stage_entry(void) else printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); + /* Stash variable MRC data and let cache system update it later */ + new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, + &var_size); + if (new_var_data) + mrc_cache_stash_vardata(new_var_data, var_size, + car_get_var(fsp_version)); + else + printk(BIOS_ERR, "Failed to determine variable data\n"); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -239,6 +257,8 @@ static void fill_console_params(FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + const struct mrc_saved_data *msd; + fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -262,6 +282,23 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * skip HECI2 reset. */ mupd->FspmConfig.EnableS3Heci2 = 0; + + /* + * Apollolake splits MRC cache into two parts: constant and variable. + * The constant part is not expected to change often and variable is. + * Currently variable part consists of parameters that change on cold + * boots such as scrambler seed and some memory controller registers. + * Scrambler seed is vital for S3 resume case because attempt to use + * wrong/missing key renders DRAM contents useless. + */ + + if (mrc_cache_get_vardata(&msd, version) < 0) { + printk(BIOS_DEBUG, "MRC variable data missing/invalid\n"); + } else { + mupd->FspmConfig.VariableNvsBufferPtr = (void*) msd->data; + } + + car_set_var(fsp_version, version); } __attribute__ ((weak))

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Patch set updated for coreboot: soc/intel/common: Add store/restore for variable MRC data
by Andrey Petrov 29 Nov '16

29 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17320 -gerrit commit bd65fd4af19fdfbdf148b694eee8b3db6be8728c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Nov 8 08:30:06 2016 -0800 soc/intel/common: Add store/restore for variable MRC data Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/commonlib/include/commonlib/cbmem_id.h | 2 + src/include/elog.h | 1 + src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/mrc_cache.c | 116 +++++++++++++++++++++-------- src/soc/intel/common/mrc_cache.h | 4 + 5 files changed, 96 insertions(+), 31 deletions(-) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 0d2a7c3..9fb1606 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -41,6 +41,7 @@ #define CBMEM_ID_MMA_DATA 0x4D4D4144 #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 +#define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_PIRQ 0x49525154 @@ -92,6 +93,7 @@ { CBMEM_ID_MMA_DATA, "MMA DATA " }, \ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ + { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ { CBMEM_ID_MTC, "MTC " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ diff --git a/src/include/elog.h b/src/include/elog.h index f2e587c..501e30d 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -160,6 +160,7 @@ struct elog_event_data_me_extended { #define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa #define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 #define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 +#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 #define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 #define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 struct elog_event_mem_cache_update { diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 7ae7e60..23dd601 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -31,6 +31,10 @@ config HAS_RECOVERY_MRC_CACHE bool default n +config MRC_SETTINGS_VARIABLE_DATA + bool + default n + endif # CACHE_MRC_SETTINGS config DISPLAY_MTRRS diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 7b66043..ad01551 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -35,6 +35,14 @@ struct mrc_data_region { uint32_t size; }; +enum result { + WRITE_FAILURE = -1, + ERASE_FAILURE = -2, + OTHER_FAILURE = -3, + UPDATE_SUCCESS = 0, + ALREADY_UPTODATE = 1 +}; + /* common code */ static int mrc_cache_get_region(const char *name, struct mrc_data_region *region) @@ -235,6 +243,16 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return mrc_cache_get_current_with_version(cache, 0); } +int mrc_cache_get_vardata(const struct mrc_saved_data **cache, uint32_t version) +{ + struct mrc_data_region region; + + if (mrc_cache_get_region(VARIABLE_MRC_CACHE, &region) < 0) + return -1; + + return __mrc_cache_get_current(&region, cache, version); +} + /* Fill in mrc_saved_data structure with payload. */ static void mrc_cache_fill(struct mrc_saved_data *cache, const void *data, size_t size, uint32_t version) @@ -247,15 +265,15 @@ static void mrc_cache_fill(struct mrc_saved_data *cache, const void *data, cache->size); } -int mrc_cache_stash_data_with_version(const void *data, size_t size, - uint32_t version) +static int _mrc_stash_data(const void *data, size_t size, uint32_t version, + uint32_t cbmem_id) { int cbmem_size; struct mrc_saved_data *cache; cbmem_size = sizeof(*cache) + ALIGN(size, 16); - cache = cbmem_add(CBMEM_ID_MRCDATA, cbmem_size); + cache = cbmem_add(cbmem_id, cbmem_size); if (cache == NULL) { printk(BIOS_ERR, "MRC: No space in cbmem for training data.\n"); @@ -273,6 +291,18 @@ int mrc_cache_stash_data_with_version(const void *data, size_t size, return 0; } +int mrc_cache_stash_data_with_version(const void *data, size_t size, + uint32_t version) +{ + return _mrc_stash_data(data, size, version, CBMEM_ID_MRCDATA); +} + +int mrc_cache_stash_vardata(const void *data, size_t size, uint32_t version) +{ + return _mrc_stash_data(data, size, version, CBMEM_ID_VAR_MRCDATA); +} + + int mrc_cache_stash_data(const void *data, size_t size) { return mrc_cache_stash_data_with_version(data, size, 0); @@ -324,51 +354,57 @@ mrc_cache_next_slot(const struct mrc_data_region *region, return next_slot; } -static void log_event_cache_update(uint8_t slot, uint8_t status) +static void log_event_cache_update(uint8_t slot, enum result res) { const int type = ELOG_TYPE_MEM_CACHE_UPDATE; struct elog_event_mem_cache_update event = { - .slot = slot, - .status = status, + .slot = slot }; + /* Filter through interesting events only */ + switch (res) { + case WRITE_FAILURE: /* fall-through */ + case ERASE_FAILURE: /* fall-through */ + case OTHER_FAILURE: /* fall-through */ + event.status = ELOG_MEM_CACHE_UPDATE_STATUS_FAIL; + break; + case UPDATE_SUCCESS: + event.status = ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS; + break; + default: + return; + } + if (elog_add_event_raw(type, &event, sizeof(event)) < 0) printk(BIOS_ERR, "Failed to log mem cache update event.\n"); } -static void update_mrc_region(void) +static int update_mrc_cache_type(uint32_t cbmem_id, const char *region_name) { const struct mrc_saved_data *current_boot; const struct mrc_saved_data *current_saved; const struct mrc_saved_data *next_slot; struct mrc_data_region region; - const char *region_name = DEFAULT_MRC_CACHE; - uint8_t slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL; + int res; printk(BIOS_DEBUG, "MRC: Updating cache data.\n"); - if (vboot_recovery_mode_enabled() && - IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) { - region_name = RECOVERY_MRC_CACHE; - slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY; - } - printk(BIOS_ERR, "MRC: Cache region selected - %s\n", region_name); if (mrc_cache_get_region(region_name, &region)) { printk(BIOS_ERR, "MRC: Could not obtain cache region.\n"); - return; + return OTHER_FAILURE; } - current_boot = cbmem_find(CBMEM_ID_MRCDATA); + current_boot = cbmem_find(cbmem_id); if (!current_boot) { printk(BIOS_ERR, "MRC: No cache in cbmem.\n"); - return; + return OTHER_FAILURE; } if (!mrc_cache_valid(&region, current_boot)) { printk(BIOS_ERR, "MRC: Cache data in cbmem invalid.\n"); - return; + return OTHER_FAILURE; } current_saved = NULL; @@ -379,7 +415,7 @@ static void update_mrc_region(void) !memcmp(&current_saved->data[0], &current_boot->data[0], current_saved->size)) { printk(BIOS_DEBUG, "MRC: Cache up to date.\n"); - return; + return ALREADY_UPTODATE; } } @@ -391,21 +427,15 @@ static void update_mrc_region(void) if (nvm_erase(region.base, region.size) < 0) { printk(BIOS_DEBUG, "MRC: Failure erasing " "region %s.\n", region_name); - return; + return ERASE_FAILURE; } } next_slot = region.base; } - if (nvm_write((void *)next_slot, current_boot, - current_boot->size + sizeof(*current_boot))) { - printk(BIOS_DEBUG, "MRC: Failure writing MRC cache to %s:%p\n", - region_name, next_slot); - log_event_cache_update(slot, ELOG_MEM_CACHE_UPDATE_STATUS_FAIL); - } else { - log_event_cache_update(slot, - ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS); - } + res = nvm_write((void *)next_slot, current_boot, current_boot->size + + sizeof(*current_boot)); + return res < 0 ? WRITE_FAILURE : UPDATE_SUCCESS; } static void protect_mrc_region(void) @@ -429,7 +459,31 @@ static void protect_mrc_region(void) static void update_mrc_cache(void *unused) { - update_mrc_region(); + uint8_t slot; + const char *region_name; + enum result res; + + /* First update either recovery or default cache */ + if (vboot_recovery_mode_enabled() && + IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) { + region_name = RECOVERY_MRC_CACHE; + slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY; + } else { + region_name = DEFAULT_MRC_CACHE; + slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL; + } + + res = update_mrc_cache_type(CBMEM_ID_MRCDATA, region_name); + log_event_cache_update(slot, res); + + /* Next update variable cache if in use */ + if (IS_ENABLED(CONFIG_MRC_SETTINGS_VARIABLE_DATA)) { + res = update_mrc_cache_type(CBMEM_ID_VAR_MRCDATA, + VARIABLE_MRC_CACHE); + log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE, + res); + } + protect_mrc_region(); } diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 850acd6..6414acc 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -20,6 +20,7 @@ #include <stdint.h> #define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define VARIABLE_MRC_CACHE "RW_VAR_MRC_CACHE" #define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" #define UNIFIED_MRC_CACHE "UNIFIED_MRC_CACHE" @@ -36,6 +37,8 @@ struct mrc_saved_data { int mrc_cache_get_current(const struct mrc_saved_data **cache); int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, uint32_t version); +int mrc_cache_get_vardata(const struct mrc_saved_data **cache, + uint32_t version); int mrc_cache_get_current_from_region(const struct mrc_saved_data **cache, uint32_t version, const char *region_name); @@ -44,5 +47,6 @@ int mrc_cache_get_current_from_region(const struct mrc_saved_data **cache, int mrc_cache_stash_data(const void *data, size_t size); int mrc_cache_stash_data_with_version(const void *data, size_t size, uint32_t version); +int mrc_cache_stash_vardata(const void *data, size_t size, uint32_t version); #endif /* _COMMON_MRC_CACHE_H_ */

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Patch set updated for coreboot: mainboard/reef: Add RW_VAR_MRC_CACHE
by Andrey Petrov 29 Nov '16

29 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17235 -gerrit commit 8b22c23114d2930aa39f5c132fa281a570756ad0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 4 16:17:11 2016 -0700 mainboard/reef: Add RW_VAR_MRC_CACHE Chop off 4kb block from RW_MRC_CACHE to store variable MRC cache. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I3e19fff9c9b20d6c73cbb13bfeec49e9a274bb72 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/google/reef/chromeos.fmd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 1fea910..c7e51ee 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -15,7 +15,8 @@ FLASH 16M { MISC_RW@0x400000 0x4a000 { UNIFIED_MRC_CACHE@0x0 0x40000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x30000 + RW_MRC_CACHE@0x10000 0x2f000 + RW_VAR_MRC_CACHE@0x3f000 0x1000 } RW_ELOG@0x40000 0x4000 RW_SHARED@0x44000 0x4000 {

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Patch set updated for coreboot: driver/intel/fsp2_0: Add version parameter to FSP platform callback
by Andrey Petrov 29 Nov '16

29 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17497 -gerrit commit a5e4e6d6d0052a621853c5780e92698874de7464 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 18 14:57:51 2016 -0800 driver/intel/fsp2_0: Add version parameter to FSP platform callback Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 2 +- src/drivers/intel/fsp2_0/memory_init.c | 2 +- src/soc/intel/apollolake/romstage.c | 2 +- src/soc/intel/quark/romstage/fsp2_0.c | 2 +- src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b012040..a8445ba 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -41,7 +41,7 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(bool s3wake); /* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callback after processing FSP notify */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b833561..56de0ef 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -316,7 +316,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, die("FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ - platform_fsp_memory_init_params_cb(&fspm_upd); + platform_fsp_memory_init_params_cb(&fspm_upd, hdr->fsp_revision); /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index f1d4b57..d623913 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -237,7 +237,7 @@ static void fill_console_params(FSPM_UPD *mupd) } } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { fill_console_params(mupd); mainboard_memory_init_params(mupd); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index d90bd38..17080a3 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -87,7 +87,7 @@ int fill_power_state(void) return ps->prev_sleep_state; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) { FSPM_ARCH_UPD *aupd; const struct device *dev; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8e08323..adb8442 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->PcieRpEnableMask = mask; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;

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coreboot-gerrit November 2016