coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

New patch to review for coreboot: vboot: No vboot verification when Chrome EC disabled
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17246 -gerrit commit a38eaa1284d240460764f77bc5532ef10612ae4b Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:51:14 2016 +0530 vboot: No vboot verification when Chrome EC disabled When Chrome EC is disabled, vboot hash is not available during S3 resume. Hence disbale vboot verification when Chrome EC is not available. Change-Id: I665f5f0e2e53da7b735de30443d323572d8a1a9c Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/vboot/vboot_logic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/vboot/vboot_logic.c b/src/vboot/vboot_logic.c index bc6ab48..e565cb6 100644 --- a/src/vboot/vboot_logic.c +++ b/src/vboot/vboot_logic.c @@ -119,6 +119,12 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) int is_resume; /* + * If Chrome EC is not enabled then return + */ + if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return 0; + + /* * Nothing to do since resuming on the platform doesn't require * vboot verification again. */

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New patch to review for coreboot: soc/intel/skylake: Add device id for PCH-Y
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17244 -gerrit commit f12ff03f6cb47f7beb06af8e94a16086283aa5d5 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:36:31 2016 +0530 soc/intel/skylake: Add device id for PCH-Y Add device id for PCH-Y used in Kaby Lake RVP3 board. Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/bootblock/report_platform.c | 1 + src/soc/intel/skylake/include/soc/pch.h | 1 + src/soc/intel/skylake/lpc.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index f10159f..3112437 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -57,6 +57,7 @@ static struct { { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, + { PCH_KBL_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium"}, }; static struct { diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 37fe1f9..701a6f5 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -26,6 +26,7 @@ #define PCH_SPT_LP_U_BASE 0x9d43 #define PCH_SPT_LP_U_PREMIUM 0x9d48 #define PCH_SPT_LP_Y_PREMIUM 0x9d46 +#define PCH_KBL_LP_Y_PREMIUM_HDCP22 0x9d4b #define PCH_KBL_LP_U_PREMIUM 0x9d58 #define PCH_KBL_LP_Y_PREMIUM 0x9d56 diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 3b5ccfe..1355c80 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -319,6 +319,7 @@ static const unsigned short pci_device_ids[] = { PCH_SPT_LP_Y_PREMIUM, PCH_KBL_LP_U_PREMIUM, PCH_KBL_LP_Y_PREMIUM, + PCH_KBL_LP_Y_PREMIUM_HDCP22, 0 };

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New patch to review for coreboot: mainboard/google/reef: Add support for RECOVERY_MRC_CACHE
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17243 -gerrit commit 4b3c60ed4f357af0f4f7acecbb3334576c85f80c Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Nov 6 00:07:08 2016 -0700 mainboard/google/reef: Add support for RECOVERY_MRC_CACHE 1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper functions for getting and clearing event for recovery mode with memory retraining. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/chromeos.c | 24 ++++++++++++++++++++++-- src/mainboard/google/reef/chromeos.fmd | 3 ++- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 58c2cd8..ddb0cc4 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -50,9 +50,23 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check if the EC has posted the keyboard recovery event. */ + /* + * Check if the EC has posted the keyboard recovery event with/without + * memory retrain. + */ return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))); +} + +int get_recovery_mode_retrain_switch(void) +{ + /* + * Check if the EC has posted the keyboard recovery event with memory + * retrain. + */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } int clear_recovery_mode_switch(void) @@ -62,6 +76,12 @@ int clear_recovery_mode_switch(void) EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } +int clear_recovery_mode_retrain_switch(void) +{ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); +} + int get_write_protect_state(void) { /* Read PCH_WP GPIO. */ diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index d25a9b2..c6a413d 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -13,7 +13,8 @@ FLASH 16M { } } MISC_RW@0x400000 0x4a000 { - RW_MRC_CACHE@0x0 0x40000 + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x30000 RW_ELOG@0x40000 0x4000 RW_SHARED@0x44000 0x4000 { SHARED_DATA@0x0 0x2000

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New patch to review for coreboot: mrc: Add support for separate training cache in recovery mode
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17242 -gerrit commit c4f0d285d922fd9ab633841351386fe4f6d12289 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:57:02 2016 -0700 mrc: Add support for separate training cache in recovery mode 1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RECOVERY_MRC_CACHE before jumping from RO to RW in recovery mode. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/fsp2_0/memory_init.c | 18 ----- src/soc/intel/common/mrc_cache.c | 136 ++++++++++++++++++++++----------- src/soc/intel/common/mrc_cache.h | 3 + 3 files changed, 94 insertions(+), 63 deletions(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..798cd87 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -55,13 +55,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) printk(BIOS_ERR, "Failed to stash MRC data\n"); } -/* - * On every trip to recovery, newly generated MRC data is stored with this - * version since it is not expected to be a legit version. This ensures that on - * next normal boot, memory re-training occurs and new MRC data is stored. - */ -#define MRC_DEAD_VERSION (0xdeaddead) - static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -89,10 +82,6 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request!\n"); - /* Now that CBMEM is up, save the list so ramstage can use it */ - if (vboot_recovery_mode_enabled()) - fsp_version = MRC_DEAD_VERSION; - save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ @@ -113,14 +102,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { - printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); - return; - } - if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { - printk(BIOS_SPEW, "MRC cache was not found\n"); return; } diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index c123da9..29721e4 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -34,13 +34,37 @@ struct mrc_data_region { uint32_t size; }; +/* Protect RW_MRC_CACHE region with a Protected Range Register */ +static int protect_mrc_cache(const struct mrc_data_region *region, + const char *name) +{ +#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) + if (nvm_is_write_protected() <= 0) { + printk(BIOS_INFO, "MRC: NOT enabling PRR for %s.\n", name); + return 1; + } + + if (nvm_protect(region->base, region->size) < 0) { + printk(BIOS_ERR, "MRC: ERROR setting PRR for %s.\n", name); + return -1; + } + + printk(BIOS_INFO, "MRC: Enabled Protected Range on %s.\n", name); +#endif + return 0; +} + /* common code */ -static int mrc_cache_get_region(struct mrc_data_region *region) +static int mrc_cache_get_region(const char *name, + struct mrc_data_region *region) { bool located_by_fmap = true; struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev)) + region->base = NULL; + region->size = 0; + + if (fmap_locate_area_as_rdev(name, &rdev)) located_by_fmap = false; /* CHROMEOS builds must get their MRC cache from FMAP. */ @@ -61,6 +85,18 @@ static int mrc_cache_get_region(struct mrc_data_region *region) return 0; } +/* + * Check if RECOVERY_MRC_CACHE exists on this device. + * Returns 1 if region exists, 0 otherwise. + */ +static int mrc_recovery_cache_exists(void) +{ + if (!IS_ENABLED(CONFIG_CHROMEOS)) + return 0; + + return fmap_region_exists(RECOVERY_MRC_CACHE); +} + static int mrc_cache_in_region(const struct mrc_data_region *region, const struct mrc_saved_data *cache) { @@ -148,22 +184,43 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region, return -1; if (verified_cache->version != version) { - printk(BIOS_DEBUG, "MRC cache version mismatch: %x vs %x\n", + printk(BIOS_DEBUG, "MRC: cache version mismatch: %x vs %x\n", verified_cache->version, version); return -1; } - printk(BIOS_DEBUG, "MRC cache slot %d @ %p\n", slot-1, verified_cache); + printk(BIOS_DEBUG, "MRC: cache slot %d @ %p\n", slot-1, verified_cache); return 0; } int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, - uint32_t version) + uint32_t version) { struct mrc_data_region region; + const char *region_name = DEFAULT_MRC_CACHE; + + if (vboot_recovery_mode_enabled()) { + if (mrc_recovery_cache_exists() && + !vboot_recovery_mode_memory_retrain()) + region_name = RECOVERY_MRC_CACHE; + else + region_name = NULL; + } else { + if (!mrc_cache_get_region(RECOVERY_MRC_CACHE, &region)) { + printk(BIOS_INFO, "MRC: Protecting recovery cache.\n"); + protect_mrc_cache(&region, RECOVERY_MRC_CACHE); + } + } - if (mrc_cache_get_region(&region) < 0) + if (!region_name) { + printk(BIOS_ERR, "MRC: Requires memory retraining\n"); + return -1; + } + + printk(BIOS_ERR, "MRC: Using data from %s\n", region_name); + + if (mrc_cache_get_region(region_name, &region) < 0) return -1; return __mrc_cache_get_current(&region, cache, version); @@ -196,14 +253,14 @@ int mrc_cache_stash_data_with_version(const void *data, size_t size, cache = cbmem_add(CBMEM_ID_MRCDATA, cbmem_size); if (cache == NULL) { - printk(BIOS_ERR, "No space in cbmem for MRC data.\n"); + printk(BIOS_ERR, "MRC: No space in cbmem for training data.\n"); return -1; } /* Clear alignment padding bytes at end of data. */ memset(&cache->data[size], 0, cbmem_size - size - sizeof(*cache)); - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%zu bytes)\n", + printk(BIOS_DEBUG, "MRC: Relocate data from %p to %p (%zu bytes)\n", data, cache, size); mrc_cache_fill(cache, data, size, version); @@ -262,48 +319,35 @@ mrc_cache_next_slot(const struct mrc_data_region *region, return next_slot; } -/* Protect RW_MRC_CACHE region with a Protected Range Register */ -static int protect_mrc_cache(const struct mrc_data_region *region) -{ -#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) - if (nvm_is_write_protected() <= 0) { - printk(BIOS_INFO, "NOT enabling PRR for RW_MRC_CACHE region\n"); - return 1; - } - - if (nvm_protect(region->base, region->size) < 0) { - printk(BIOS_ERR, "ERROR setting PRR for RW_MRC_CACHE region\n"); - return -1; - } - - printk(BIOS_INFO, "Enabled Protected Range on RW_MRC_CACHE region\n"); -#endif - return 0; -} - static void update_mrc_cache(void *unused) { const struct mrc_saved_data *current_boot; const struct mrc_saved_data *current_saved; const struct mrc_saved_data *next_slot; struct mrc_data_region region; + const char *region_name = DEFAULT_MRC_CACHE; - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + printk(BIOS_DEBUG, "MRC: Updating cache data.\n"); - current_boot = cbmem_find(CBMEM_ID_MRCDATA); - if (!current_boot) { - printk(BIOS_ERR, "No MRC cache in cbmem.\n"); + if (vboot_recovery_mode_enabled() && mrc_recovery_cache_exists()) + region_name = RECOVERY_MRC_CACHE; + + printk(BIOS_ERR, "MRC: Cache region selected - %s\n", region_name); + + if (mrc_cache_get_region(region_name, &region)) { + printk(BIOS_ERR, "MRC: Could not obtain cache region.\n"); return; } - if (mrc_cache_get_region(&region)) { - printk(BIOS_ERR, "Could not obtain MRC cache region.\n"); - return; + current_boot = cbmem_find(CBMEM_ID_MRCDATA); + if (!current_boot) { + printk(BIOS_ERR, "MRC: No cache in cbmem.\n"); + goto out; } if (!mrc_cache_valid(&region, current_boot)) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; + printk(BIOS_ERR, "MRC: Cache data in cbmem invalid.\n"); + goto out; } current_saved = NULL; @@ -313,20 +357,20 @@ static void update_mrc_cache(void *unused) if (current_saved->size == current_boot->size && !memcmp(&current_saved->data[0], &current_boot->data[0], current_saved->size)) { - printk(BIOS_DEBUG, "MRC cache up to date.\n"); - protect_mrc_cache(&region); - return; + printk(BIOS_DEBUG, "MRC: Cache up to date.\n"); + goto out; } } next_slot = mrc_cache_next_slot(&region, current_saved); if (!mrc_slot_valid(&region, next_slot, current_boot)) { - printk(BIOS_DEBUG, "Slot @ %p is invalid.\n", next_slot); + printk(BIOS_DEBUG, "MRC: Slot @ %p is invalid.\n", next_slot); if (!nvm_is_erased(region.base, region.size)) { if (nvm_erase(region.base, region.size) < 0) { - printk(BIOS_DEBUG, "Failure erasing region.\n"); - return; + printk(BIOS_DEBUG, "MRC: Failure erasing " + "region %s.\n", region_name); + goto out; } } next_slot = region.base; @@ -334,10 +378,12 @@ static void update_mrc_cache(void *unused) if (nvm_write((void *)next_slot, current_boot, current_boot->size + sizeof(*current_boot))) { - printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n", - next_slot); + printk(BIOS_DEBUG, "MRC: Failure writing cache to %s(%p).\n", + region_name, next_slot); } - protect_mrc_cache(&region); + +out: + protect_mrc_cache(&region, region_name); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 9b14c1e..09ab306 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -19,6 +19,9 @@ #include <stddef.h> #include <stdint.h> +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" + /* Wrapper object to save MRC information. */ struct mrc_saved_data { uint32_t signature;

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New patch to review for coreboot: vboot: Add support for recovery mode with forced memory retraining
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17241 -gerrit commit a21804dbefbaa1af50ad3ca57867d949e36be958 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:52:08 2016 -0700 vboot: Add support for recovery mode with forced memory retraining 1. Add new function vboot_recovery_mode_memory_retrain that indicates if recovery mode requires memory retraining to be performed. 2. Add helper functions {get,clear}_recovery_mode_retrain_switch to read memory retrain switch. These are provided as weak functions which should be implemented by mainboard just like {get,clear}_recovery_mode_switch. 3. Additionally, the switch for recovery mode with forced memory training should be cleared when recovery mode switch is cleared. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified behavior of recovery mode with forced memory retraining on reef. Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/include/bootmode.h | 2 ++ src/vboot/bootmode.c | 15 +++++++++++++++ src/vboot/vboot_common.h | 1 + src/vboot/vboot_handoff.c | 1 + 4 files changed, 19 insertions(+) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 21aa386..012bc39 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -22,7 +22,9 @@ int get_write_protect_state(void); int get_sw_write_protect_state(void); int get_developer_mode_switch(void); int get_recovery_mode_switch(void); +int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); +int clear_recovery_mode_retrain_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 12a4dc0..34377e1 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -162,6 +162,21 @@ int vboot_recovery_mode_enabled(void) return !!vboot_check_recovery_request(); } +int __attribute__((weak)) get_recovery_mode_retrain_switch(void) +{ + return 0; +} + +int __attribute__((weak)) clear_recovery_mode_retrain_switch(void) +{ + return 0; +} + +int vboot_recovery_mode_memory_retrain(void) +{ + return get_recovery_mode_retrain_switch(); +} + int vboot_developer_mode_enabled(void) { if (!IS_ENABLED(CONFIG_VBOOT)) diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 59fd44c..956b54c 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -107,5 +107,6 @@ void verstage_mainboard_init(void); /* Check boot modes */ int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); +int vboot_recovery_mode_memory_retrain(void); #endif /* __VBOOT_VBOOT_COMMON_H__ */ diff --git a/src/vboot/vboot_handoff.c b/src/vboot/vboot_handoff.c index b0bd04c..a2409cf 100644 --- a/src/vboot/vboot_handoff.c +++ b/src/vboot/vboot_handoff.c @@ -163,6 +163,7 @@ void vboot_fill_handoff(void) * is known to be up. */ clear_recovery_mode_switch(); + clear_recovery_mode_retrain_switch(); } /*

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New patch to review for coreboot: google/chromeec: Sync ec_commands.h host events with ec codebase
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17240 -gerrit commit 9f86592651657ed9e505435a766f2839821fd65d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Nov 6 00:12:23 2016 -0700 google/chromeec: Sync ec_commands.h host events with ec codebase BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: Ibfa5681e16a97e342633104d2aae1fb0402939b8 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/ec/google/chromeec/ec_commands.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4a551c2..ec404f0 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -471,9 +471,21 @@ enum host_event_code { /* Emulate MKBP event */ EC_HOST_EVENT_MKBP = 27, + /* EC desires to change state of host-controlled USB mux */ + EC_HOST_EVENT_USB_MUX = 28, + /* TABLET/LAPTOP mode event*/ EC_HOST_EVENT_MODE_CHANGE = 29, + /* Keyboard recovery combo with hardware reinitialization */ + EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, + + /* + * Reserve this last bit to indicate that at least one bit in a + * secondary host event word is set. See crbug.com/633646. + */ + EC_HOST_EVENT_EXTENDED = 31, + /* * The high bit of the event mask is not used as a host event code. If * it reads back as set, then the entire event mask should be

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New patch to review for coreboot: soc/intel/common: Enable SPI and NVM drivers in pre-ram stages
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17239 -gerrit commit 995a35dc43434bba3b2fc54e2fe988f8f4c7ac6f Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:46:10 2016 -0700 soc/intel/common: Enable SPI and NVM drivers in pre-ram stages BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that spi region can be protected in romstage using nvm functions. Change-Id: Iba32b0828b7f2078ee3dbaeb0c6abd2157307fb2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/common/Makefile.inc | 2 ++ src/soc/intel/common/nvm.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0..4abe524 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -10,7 +10,9 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 6b86faf..b0ca814 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <stdint.h> #include <stddef.h> #include <bootmode.h> @@ -28,10 +29,12 @@ * address space for reading. Also this module assumes an area it erased * when all bytes read as all 0xff's. */ -static struct spi_flash *flash; +static struct spi_flash *gflash CAR_GLOBAL; static int nvm_init(void) { + struct spi_flash *flash = car_get_var(gflash); + if (flash != NULL) return 0; @@ -41,6 +44,7 @@ static int nvm_init(void) printk(BIOS_DEBUG, "Could not find SPI device\n"); return -1; } + car_set_var(gflash, flash); return 0; } @@ -81,6 +85,9 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; + + struct spi_flash *flash = car_get_var(gflash); + return flash->erase(flash, nvm_mmio_to_flash_offset(start), size); } @@ -89,6 +96,9 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; + + struct spi_flash *flash = car_get_var(gflash); + return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data); } @@ -98,6 +108,8 @@ int nvm_is_write_protected(void) if (nvm_init() < 0) return -1; + struct spi_flash *flash = car_get_var(gflash); + if (IS_ENABLED(CONFIG_CHROMEOS)) { u8 sr1; u8 wp_gpio;

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New patch to review for coreboot: fmap: Add support for checking existence of region
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17238 -gerrit commit d9dc0ec5f16f8fc8bdb40461edc2e5967027ecd9 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:37:11 2016 -0700 fmap: Add support for checking existence of region Implement fmap_region_exists which acts as a wrapper for checking if a region name exists in FMAP. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that fmap_exists returns existence of region names present in FMAP. Change-Id: I288ea8c7c57d3b0f237cdece42c4f5fe9c2c066a Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/include/fmap.h | 3 +++ src/lib/fmap.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/src/include/fmap.h b/src/include/fmap.h index 5834831..774fbfe 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -36,6 +36,9 @@ int fmap_locate_area_as_rdev_rw(const char *name, struct region_device *area); * < 0 on error. */ int fmap_locate_area(const char *name, struct region *r); +/* Check if region exists in fmap. Return 1 on success, 0 on error. */ +int fmap_region_exists(const char *name); + /* Find fmap area name by offset and size. * Return 0 on success, < 0 on error. */ int fmap_find_region_name(const struct region * const ar, diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 9602134..8cb7267 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -131,6 +131,12 @@ int fmap_locate_area(const char *name, struct region *ar) return -1; } +int fmap_region_exists(const char *name) +{ + struct region ar; + return !fmap_locate_area(name, &ar); +} + int fmap_find_region_name(const struct region * const ar, char name[FMAP_STRLEN]) {

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Patch set updated for coreboot: soc/intel/common: Enable SPI NVM functions in pre-RAM stages
by Andrey Petrov 06 Nov '16

06 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17234 -gerrit commit 8849609b16fcd07bb229dd5554748e0e217b912c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 4 15:37:27 2016 -0700 soc/intel/common: Enable SPI NVM functions in pre-RAM stages Put global variable into CAR global. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I35ea29096abcdde482b99d90db022b7c7bc95c29 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/nvm.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0..51b6f86 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 6b86faf..5af73d5 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <stdint.h> #include <stddef.h> #include <bootmode.h> @@ -28,10 +29,12 @@ * address space for reading. Also this module assumes an area it erased * when all bytes read as all 0xff's. */ -static struct spi_flash *flash; +static struct spi_flash *gflash CAR_GLOBAL; static int nvm_init(void) { + struct spi_flash *flash = car_get_var(gflash); + if (flash != NULL) return 0; @@ -41,6 +44,7 @@ static int nvm_init(void) printk(BIOS_DEBUG, "Could not find SPI device\n"); return -1; } + car_set_var(gflash, flash); return 0; } @@ -79,25 +83,35 @@ int nvm_is_erased(const void *start, size_t size) int nvm_erase(void *start, size_t size) { + struct spi_flash *flash; + if (nvm_init() < 0) return -1; + flash = car_get_var(gflash); return flash->erase(flash, nvm_mmio_to_flash_offset(start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ int nvm_write(void *start, const void *data, size_t size) { + struct spi_flash *flash; + if (nvm_init() < 0) return -1; + flash = car_get_var(gflash); return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data); } /* Read flash status register to determine if write protect is active */ int nvm_is_write_protected(void) { + struct spi_flash *flash; + if (nvm_init() < 0) return -1; + flash = car_get_var(gflash); + if (IS_ENABLED(CONFIG_CHROMEOS)) { u8 sr1; u8 wp_gpio;

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New patch to review for coreboot: WIP: soc/intel/apollolake: Add save/restore variable MRC cache
by Andrey Petrov 05 Nov '16

05 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17237 -gerrit commit 14240a4dc605276990f4663f5748c34817f24adc Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 4 16:18:30 2016 -0700 WIP: soc/intel/apollolake: Add save/restore variable MRC cache Apollolake MRC cache is divided into two regions: constant and variable. Currently they are clubbed together. Since variable data changes across cold reboot it triggers invalidation of the whole cache region. This change declubs the data, adds routines to load/store variable data on flash. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I374519777abe9b9a1e6cceae5318decd405bb527 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/mrc.c | 90 +++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/mrc.h | 37 ++++++++++++++ src/soc/intel/apollolake/romstage.c | 40 +++++++++++++++- 4 files changed, 166 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4f867e1..2c1bc23 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += lpc_lib.c romstage-y += memmap.c romstage-y += meminit.c romstage-y += mmap_boot.c +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc.c romstage-y += tsc_freq.c romstage-y += pmutil.c romstage-y += reset.c diff --git a/src/soc/intel/apollolake/mrc.c b/src/soc/intel/apollolake/mrc.c new file mode 100644 index 0000000..11eeb93 --- /dev/null +++ b/src/soc/intel/apollolake/mrc.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <bootstate.h> +#include <fmap.h> +#include <ip_checksum.h> +#include <string.h> + +#include "mrc.h" +#include "soc/intel/common/nvm.h" + +#define MRC_VAR_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('V'<<24)) + +int mrc_save_variable_data(const void *payload, size_t payload_size) +{ + struct region_device rdev; + void *regbase; + struct mrc_saved_variable_data data; + + if (!payload) + return -1; + + if (payload_size > ARRAY_SIZE(data.payload)) + return -1; + + if (fmap_locate_area_as_rdev("RW_VAR_MRC_CACHE", &rdev) < 0) + return -1; + + regbase = rdev_mmap_full(&rdev); + memset(&data, 0, sizeof(data)); + + data.signature = MRC_VAR_DATA_SIGNATURE; + data.size = payload_size; + data.checksum = compute_ip_checksum((void*)payload, payload_size); + + memcpy(&data.payload, payload, MIN(payload_size, + ARRAY_SIZE(data.payload))); + rdev_munmap(&rdev, regbase); + nvm_erase(regbase, region_device_sz(&rdev)); + + return nvm_write(regbase, &data, sizeof(data)); +} + +int mrc_restore_variable_data(void *data) +{ + struct region_device rdev; + struct mrc_saved_variable_data *svd; + int ret = -1; + + if (fmap_locate_area_as_rdev("RW_VAR_MRC_CACHE", &rdev) < 0) + return ret; + + svd = (struct mrc_saved_variable_data*) rdev_mmap_full(&rdev); + + if (!svd) + return ret; + + if (svd->signature != MRC_VAR_DATA_SIGNATURE || + svd->size > region_device_sz(&rdev) || + svd->checksum != compute_ip_checksum(&svd->payload, svd->size)) { + printk(BIOS_WARNING, "Variable MRC data unusable\n"); + } else { + memcpy(data, svd->payload, + MIN(ARRAY_SIZE(svd->payload), svd->size)); + ret = 0; + } + + rdev_munmap(&rdev, svd); + return ret; +} + +int mrc_protect_variable_data(void) +{ + /* Not implemented yet */ + return 0; +} diff --git a/src/soc/intel/apollolake/mrc.h b/src/soc/intel/apollolake/mrc.h new file mode 100644 index 0000000..ddcb745 --- /dev/null +++ b/src/soc/intel/apollolake/mrc.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_MRC_H_ +#define _SOC_APOLLOLAKE_MRC_H_ + +#include <stddef.h> +#include <stdint.h> + +#define MRC_MAX_VARDATA_SIZE 32 + +struct mrc_saved_variable_data { + uint32_t signature; + unsigned long checksum; + size_t size; + uint8_t payload[MRC_MAX_VARDATA_SIZE]; +} __attribute__((packed)); + +/* store variable data */ +int mrc_save_variable_data(const void *payload, size_t payload_size); +/* restore MRC into provided storage */ +int mrc_restore_variable_data(void *data); +int mrc_protect_variable_data(void); + +#endif \ No newline at end of file diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..cc5d25a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -40,8 +40,18 @@ #include <soc/uart.h> #include <string.h> #include <timestamp.h> +#include "mrc.h" + +#include <lib.h> static struct chipset_power_state power_state CAR_GLOBAL; +static uint8_t mrc_var_buff[MRC_MAX_VARDATA_SIZE] CAR_GLOBAL; + +static const uint8_t variable_guid[16] = { + 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, + 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, +}; + /* High Performance Event Timer Configuration */ #define P2SB_HPTC 0x60 @@ -106,8 +116,9 @@ asmlinkage void car_stage_entry(void) uintptr_t top_of_ram; bool s3wake; struct chipset_power_state *ps = car_get_var_ptr(&power_state); - void *smm_base; - size_t smm_size; + void *smm_base, *mrc_buff; + const void *new_var_data; + size_t smm_size, new_sz; uintptr_t tseg_base; timestamp_add_now(TS_START_ROMSTAGE); @@ -119,6 +130,15 @@ asmlinkage void car_stage_entry(void) s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + + /* Update saved MRC variable data if it doesn't match current */ + new_var_data = fsp_find_extension_hob_by_guid(variable_guid, &new_sz); + mrc_buff = car_get_var_ptr(mrc_var_buff); + if (new_var_data && memcmp(mrc_buff, new_var_data, new_sz)) { + printk(BIOS_SPEW, "MRC variable data changed, updating..\n"); + mrc_save_variable_data(new_var_data, new_sz); + } + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); @@ -170,6 +190,8 @@ static void fill_console_params(FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) { + void *saved_data = car_get_var_ptr(mrc_var_buff); + fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -193,6 +215,20 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) * skip HECI2 reset. */ mupd->FspmConfig.EnableS3Heci2 = 0; + + /* + * Apollolake splits MRC cache into two parts: constant and variable. + * The constant part is not expected to change often and variable is. + * Currently variable part consists of parameters that change on cold + * boot, such as scrambler seed, and some memory controller registers. + * Scrambler seed is vital for S3 resume case because attempt to use + * wrong/missing key renders DRAM contents into junk. + */ + + if (saved_data && mrc_restore_variable_data(saved_data) >= 0) { + mupd->FspmConfig.VariableNvsBufferPtr = saved_data; + printk(BIOS_DEBUG,"MRC variable data loaded\n"); + } } __attribute__ ((weak))

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coreboot-gerrit November 2016