coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch set updated for coreboot: mainboard/intel/kblrvp: Configure usb over current pin & cdclock
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17251 -gerrit commit f760fe5e903d5361a76cda1ded6d1f061592e47c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:12:55 2016 +0530 mainboard/intel/kblrvp: Configure usb over current pin & cdclock Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/ramstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ed37681..6a509b7 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -18,7 +18,19 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + u8 i; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; + + /* Set proper OC for various USB ports*/ + u8 usb2_oc[] = { 0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8}; + u8 usb3_oc[] = { 0x0, 0x8, 0x8, 0x1, 0x8, 0x8 }; + + for (i = 0; i < ARRAY_SIZE(usb2_oc); i++) + params->Usb2OverCurrentPin[i] = usb2_oc[i]; + + for (i = 0; i < ARRAY_SIZE(usb3_oc); i++) + params->Usb3OverCurrentPin[i] = usb3_oc[i]; }

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Patch set updated for coreboot: mainboard/intel/kblrvp: Enable Build with ChromeOS
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17250 -gerrit commit 4368f0596ff8bf7e0b7037eacd63372a915f5365 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:09:06 2016 +0530 mainboard/intel/kblrvp: Enable Build with ChromeOS Enable building with ChromeOS support. Change-Id: I9fbb7422be205b304253478a70e334a63afab71f Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/dsdt.asl | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 9427c9d..7df726c 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 + select MAINBOARD_HAS_CHROMEOS config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index ebbdeec..25e6a30 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -44,8 +44,10 @@ DefinitionBlock( #include "acpi/dptf.asl" } +#if IS_ENABLED(CONFIG_CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif // Chipset specific sleep states #include <soc/intel/skylake/acpi/sleepstates.asl>

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Patch set updated for coreboot: mainboard/intel/kblrvp: Cleanup dptf.asl
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17249 -gerrit commit 9d667406c60e346e075e2da328fdf1b448b049c5 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:07:53 2016 +0530 mainboard/intel/kblrvp: Cleanup dptf.asl Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/acpi/dptf.asl | 74 -------------------------------- 1 file changed, 74 deletions(-) diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index e011c97..c33bb06 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -22,86 +22,12 @@ #define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC4 50 -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -#ifdef DPTF_ENABLE_FAN_CONTROL -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, - Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, - Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, - Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, - Package () {60, 0xFFFFFFFF, 3838, 90, 900}, - Package () {50, 0xFFFFFFFF, 3402, 65, 650}, - Package () {40, 0xFFFFFFFF, 2904, 45, 450}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, - 0, 0, 0 - } -}) -#endif Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package ()

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Patch set updated for coreboot: mainboard/intel/kblrvp: Add Chrome EC switch
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17248 -gerrit commit 8d8942f08ea706f32970b29ea6395b9585f6a158 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:05:35 2016 +0530 mainboard/intel/kblrvp: Add Chrome EC switch Add Chrome EC switch to enable building with/without Chrome EC. Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/acpi/ec.asl | 3 +- src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 ++ src/mainboard/intel/kblrvp/chromeos.c | 40 +++++++++++++++++---------- 3 files changed, 29 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index 2203e2f..7d7ff2f 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -22,6 +22,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE - +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> +#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 1b8fe43..5d2b307 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -16,6 +16,7 @@ #include "../gpio.h" +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (LID0) @@ -34,6 +35,7 @@ Scope (\_SB) Name (_HID, EisaId ("PNP0C0C")) } } +#endif /* * LPC Trusted Platform Module diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index a9704da..f1a6287 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -40,8 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -49,8 +47,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - /* Read lid switch state from the EC. */ - return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + + /* Lid alway open */ + return 1; } int get_developer_mode_switch(void) @@ -61,31 +63,39 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check for dedicated recovery switch first. */ - if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & + EC_SWITCH_DEDICATED_RECOVERY) return 1; - /* Otherwise check if the EC has posted the keyboard recovery event. */ - return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + /* Otherwise check if the EC has posted the keyboard recovery + * event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + } + + return 0; } int clear_recovery_mode_switch(void) { - /* Clear keyboard recovery event. */ - return google_chromeec_clear_events_b( - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + + return 0; } int get_write_protect_state(void) { - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); + return 0; } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void)

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New patch to review for coreboot: soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17245 -gerrit commit 9d82c9589707dc5b7eff0f74e79794935b3d191c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:42:30 2016 +0530 soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl Avoid use of Local0 variable in TEVT acpi method. If mainboard doesn't exposes any thermal sensor, then warning is generated for variable Local0 not been used. Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/acpi/dptf/thermal.asl | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 97484e5..d9bd9c0 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -17,25 +17,24 @@ /* Thermal Threshold Event Handler */ Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR0_SENSOR_ID)) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR1_SENSOR_ID)) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR2_SENSOR_ID)) { Notify (^TSR2, 0x90) } #endif #ifdef DPTF_TSR3_SENSOR_ID - If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR3_SENSOR_ID)) { Notify (^TSR3, 0x90) } #endif

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New patch to review for coreboot: mainboard/intel/kblrvp: Configure usb over current pin & cdclock
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17251 -gerrit commit cdde5163b1db6cb0f716acbe6c63a55681cdce39 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:12:55 2016 +0530 mainboard/intel/kblrvp: Configure usb over current pin & cdclock Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/ramstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ed37681..6a509b7 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -18,7 +18,19 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + u8 i; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; + + /* Set proper OC for various USB ports*/ + u8 usb2_oc[] = { 0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8}; + u8 usb3_oc[] = { 0x0, 0x8, 0x8, 0x1, 0x8, 0x8 }; + + for (i = 0; i < ARRAY_SIZE(usb2_oc); i++) + params->Usb2OverCurrentPin[i] = usb2_oc[i]; + + for (i = 0; i < ARRAY_SIZE(usb3_oc); i++) + params->Usb3OverCurrentPin[i] = usb3_oc[i]; }

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New patch to review for coreboot: mainboard/intel/kblrvp: Enable Build with ChromeOS
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17250 -gerrit commit 3bda3455d495ac21afbcafde893ddce8685ff8a0 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:09:06 2016 +0530 mainboard/intel/kblrvp: Enable Build with ChromeOS Enable building with ChromeOS support. Change-Id: I9fbb7422be205b304253478a70e334a63afab71f Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/dsdt.asl | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 9427c9d..7df726c 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 + select MAINBOARD_HAS_CHROMEOS config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index ebbdeec..25e6a30 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -44,8 +44,10 @@ DefinitionBlock( #include "acpi/dptf.asl" } +#if IS_ENABLED(CONFIG_CHROMEOS) // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif // Chipset specific sleep states #include <soc/intel/skylake/acpi/sleepstates.asl>

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New patch to review for coreboot: mainboard/intel/kblrvp: Cleanup dptf.asl
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17249 -gerrit commit 4362f4765629a1aff9995dab2444ac30e09ed6b5 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:07:53 2016 +0530 mainboard/intel/kblrvp: Cleanup dptf.asl Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/acpi/dptf.asl | 74 -------------------------------- 1 file changed, 74 deletions(-) diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index e011c97..c33bb06 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -22,86 +22,12 @@ #define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC4 50 -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -#ifdef DPTF_ENABLE_FAN_CONTROL -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, - Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, - Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, - Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, - Package () {60, 0xFFFFFFFF, 3838, 90, 900}, - Package () {50, 0xFFFFFFFF, 3402, 65, 650}, - Package () {40, 0xFFFFFFFF, 2904, 45, 450}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, - 0, 0, 0 - } -}) -#endif Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package ()

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New patch to review for coreboot: mainboard/intel/kblrvp: Add Chrome EC switch
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17248 -gerrit commit 708ee14971ad269c56393ca01b8a051f694b452c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:05:35 2016 +0530 mainboard/intel/kblrvp: Add Chrome EC switch Add Chrome EC switch to enable building with/without Chrome EC. Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/acpi/ec.asl | 3 +- src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 ++ src/mainboard/intel/kblrvp/chromeos.c | 40 +++++++++++++++++---------- 3 files changed, 29 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index 2203e2f..7d7ff2f 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -22,6 +22,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE - +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> +#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 1b8fe43..5d2b307 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -16,6 +16,7 @@ #include "../gpio.h" +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (LID0) @@ -34,6 +35,7 @@ Scope (\_SB) Name (_HID, EisaId ("PNP0C0C")) } } +#endif /* * LPC Trusted Platform Module diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index a9704da..f1a6287 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -40,8 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -49,8 +47,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - /* Read lid switch state from the EC. */ - return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + + /* Lid alway open */ + return 1; } int get_developer_mode_switch(void) @@ -61,31 +63,39 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check for dedicated recovery switch first. */ - if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & + EC_SWITCH_DEDICATED_RECOVERY) return 1; - /* Otherwise check if the EC has posted the keyboard recovery event. */ - return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + /* Otherwise check if the EC has posted the keyboard recovery + * event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + } + + return 0; } int clear_recovery_mode_switch(void) { - /* Clear keyboard recovery event. */ - return google_chromeec_clear_events_b( - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + + return 0; } int get_write_protect_state(void) { - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); + return 0; } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void)

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New patch to review for coreboot: mainboard/intel/kblrvp: Update devicetree.cb
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17247 -gerrit commit aca09503f195176649c910e1ec919bcb3124e7a7 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 13:37:34 2016 +0530 mainboard/intel/kblrvp: Update devicetree.cb Update devicetree.cb as per RVP3 mainboard. Disable pull down for power button in gpio.h. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/devicetree.cb | 192 ++++++++++--------------------- src/mainboard/intel/kblrvp/gpio.h | 4 +- 2 files changed, 64 insertions(+), 132 deletions(-) diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb index 8dded98..ad4d877 100644 --- a/src/mainboard/intel/kblrvp/devicetree.cb +++ b/src/mainboard/intel/kblrvp/devicetree.cb @@ -1,14 +1,14 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable" = "1" + register "deep_s5_enable" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -23,9 +23,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" @@ -63,23 +60,10 @@ chip soc/intel/skylake register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ + .psi2threshold = 0x14, \ .psi3threshold = 0x4, \ .psi3enable = 1, \ .psi4enable = 1, \ @@ -124,7 +108,7 @@ chip soc/intel/skylake .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .voltage_limit = 0x5F0, \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -142,29 +126,56 @@ chip soc/intel/skylake register "FspSkipMpInit" = "1" - # Enable Root port 1 and 5. + # Enable Root ports. + # PCIE Port 1 x4 -> SLOT1 register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpClkReqNumber[0]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card) - register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera - register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - - register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # PCIE Port 5 x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + + # PCIE Port 6 x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + # PCIE Port 9 x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + + # PCIE Port 10 x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "1" # Enable SSIC for WWAN # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ @@ -181,9 +192,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # PL2 override 25W - register "tdp_pl2_override" = "25" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" @@ -191,7 +199,7 @@ chip soc/intel/skylake register "VmxEnable" = "0" # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio_default" = "GPP_D10" device cpu_cluster 0 on device lapic 0 on end @@ -202,23 +210,8 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 @@ -229,61 +222,14 @@ chip soc/intel/skylake device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "1" - register "jkdet_pull_up" = "1" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - register "device_present_gpio" = "GPP_E3" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - register "device_present_gpio" = "GPP_E3" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 19.2 on end + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.0 on end # PCI Express Port 9 x1 WLAN + device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 @@ -291,24 +237,10 @@ chip soc/intel/skylake device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface + device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "device_present_gpio" = "GPP_E3" - register "device_present_gpio_invert" = "1" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h index f8ee994..5e251d8 100644 --- a/src/mainboard/intel/kblrvp/gpio.h +++ b/src/mainboard/intel/kblrvp/gpio.h @@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), @@ -204,4 +204,4 @@ static const struct pad_config early_gpio_table[] = { #endif -#endif \ No newline at end of file +#endif

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coreboot-gerrit November 2016