coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: elog: add sources to reflect full event type namespace usage
by gerrit＠coreboot.org 06 Nov '16

06 Nov '16

the following patch was just integrated into master: commit d5be4e3d7e7d092d3ea9dc98738c39ea43d3f738 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 10:53:43 2016 -0500 elog: add sources to reflect full event type namespace usage Some events were added in other places, but coreboot's elog namespace wasn't updated. As such there's a collision with the thermtrip event. This change at least updates the elog information to reflect potential event type uage. BUG=chrome-os-partner:59395 Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17230 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17230 for details. -gerrit

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Patch merged into coreboot/master: elog: fix default elog_add_event_raw() declaration
by gerrit＠coreboot.org 06 Nov '16

06 Nov '16

the following patch was just integrated into master: commit d9b1050dfba7cc97b95ca9dcc72ae6172d8a1735 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 11:17:54 2016 -0500 elog: fix default elog_add_event_raw() declaration When CONFIG_ELOG isn't used default empty inline functions are provided, however the elog_add_event_raw() had the wrong type signature. Fix that. BUG=chrome-os-partner:59395 Change-Id: Iaee68440bbafc1e91c88a7b03e283fc3e72de0a3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17232 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17232 for details. -gerrit

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Patch set updated for coreboot: mrc: Add support for separate training cache in recovery mode
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17242 -gerrit commit 0ec826f8812f676b26c6e45be175e4cd2e74bafd Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:57:02 2016 -0700 mrc: Add support for separate training cache in recovery mode 1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RECOVERY_MRC_CACHE before jumping from RO to RW in recovery mode. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/fsp2_0/memory_init.c | 21 +---- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/mrc_cache.c | 159 +++++++++++++++++++++++---------- src/soc/intel/common/mrc_cache.h | 3 + 4 files changed, 122 insertions(+), 65 deletions(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..a561d76 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -55,13 +55,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) printk(BIOS_ERR, "Failed to stash MRC data\n"); } -/* - * On every trip to recovery, newly generated MRC data is stored with this - * version since it is not expected to be a legit version. This ensures that on - * next normal boot, memory re-training occurs and new MRC data is stored. - */ -#define MRC_DEAD_VERSION (0xdeaddead) - static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -89,10 +82,6 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request!\n"); - /* Now that CBMEM is up, save the list so ramstage can use it */ - if (vboot_recovery_mode_enabled()) - fsp_version = MRC_DEAD_VERSION; - save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ @@ -113,16 +102,8 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { - printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); + if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) return; - } - - if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { - printk(BIOS_SPEW, "MRC cache was not found\n"); - return; - } /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index affec55..5d8bf66 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -27,6 +27,10 @@ config MRC_SETTINGS_PROTECT bool "Enable protection on MRC settings" default n +config HAS_RECOVERY_MRC_CACHE + bool + default n + endif # CACHE_MRC_SETTINGS config DISPLAY_MTRRS diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index c123da9..186c556 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -34,13 +34,37 @@ struct mrc_data_region { uint32_t size; }; +/* Protect RW_MRC_CACHE region with a Protected Range Register */ +static int protect_mrc_cache(const struct mrc_data_region *region, + const char *name) +{ +#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) + if (nvm_is_write_protected() <= 0) { + printk(BIOS_INFO, "MRC: NOT enabling PRR for %s.\n", name); + return 1; + } + + if (nvm_protect(region->base, region->size) < 0) { + printk(BIOS_ERR, "MRC: ERROR setting PRR for %s.\n", name); + return -1; + } + + printk(BIOS_INFO, "MRC: Enabled Protected Range on %s.\n", name); +#endif + return 0; +} + /* common code */ -static int mrc_cache_get_region(struct mrc_data_region *region) +static int mrc_cache_get_region(const char *name, + struct mrc_data_region *region) { bool located_by_fmap = true; struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev)) + region->base = NULL; + region->size = 0; + + if (fmap_locate_area_as_rdev(name, &rdev)) located_by_fmap = false; /* CHROMEOS builds must get their MRC cache from FMAP. */ @@ -61,6 +85,19 @@ static int mrc_cache_get_region(struct mrc_data_region *region) return 0; } +/* + * Check if RECOVERY_MRC_CACHE exists on this device. + * Returns 1 if region exists, 0 otherwise. + */ +static int mrc_recovery_cache_exists(void) +{ + if (!IS_ENABLED(CONFIG_CHROMEOS) || + !IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) + return 0; + + return fmap_region_exists(RECOVERY_MRC_CACHE); +} + static int mrc_cache_in_region(const struct mrc_data_region *region, const struct mrc_saved_data *cache) { @@ -148,22 +185,65 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region, return -1; if (verified_cache->version != version) { - printk(BIOS_DEBUG, "MRC cache version mismatch: %x vs %x\n", + printk(BIOS_DEBUG, "MRC: cache version mismatch: %x vs %x\n", verified_cache->version, version); return -1; } - printk(BIOS_DEBUG, "MRC cache slot %d @ %p\n", slot-1, verified_cache); + printk(BIOS_DEBUG, "MRC: cache slot %d @ %p\n", slot-1, verified_cache); return 0; } +static const char *mrc_cache_get_region_name(void) +{ + struct mrc_data_region region; + + /* + * In recovery mode: + * 1. If recovery cache does not exist, retrain memory. + * 2. Else if memory retrain switch is set, retrain memory. + * 3. Else use RECOVERY_MRC_CACHE. + */ + if (vboot_recovery_mode_enabled()) { + if (!mrc_recovery_cache_exists()) + return NULL; + + if (vboot_recovery_mode_memory_retrain()) + return NULL; + + return RECOVERY_MRC_CACHE; + } + + /* + * In normal mode: + * 1. If recovery mrc cache exists, protect it. + * 2. Use DEFAULT_MRC_CACHE. + */ + if (mrc_recovery_cache_exists() && + !mrc_cache_get_region(RECOVERY_MRC_CACHE, &region)) { + printk(BIOS_ERR, "MRC: Protecting recovery cache.\n"); + protect_mrc_cache(&region, RECOVERY_MRC_CACHE); + } + + return DEFAULT_MRC_CACHE; +} + int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, - uint32_t version) + uint32_t version) { struct mrc_data_region region; + const char *region_name = NULL; + + region_name = mrc_cache_get_region_name(); + if (!region_name) { + printk(BIOS_ERR, "MRC: Requires memory retraining\n"); + return -1; + } + + printk(BIOS_ERR, "MRC: Using data from %s\n", region_name); - if (mrc_cache_get_region(&region) < 0) + if (mrc_cache_get_region(region_name, &region) < 0) return -1; return __mrc_cache_get_current(&region, cache, version); @@ -196,14 +276,14 @@ int mrc_cache_stash_data_with_version(const void *data, size_t size, cache = cbmem_add(CBMEM_ID_MRCDATA, cbmem_size); if (cache == NULL) { - printk(BIOS_ERR, "No space in cbmem for MRC data.\n"); + printk(BIOS_ERR, "MRC: No space in cbmem for training data.\n"); return -1; } /* Clear alignment padding bytes at end of data. */ memset(&cache->data[size], 0, cbmem_size - size - sizeof(*cache)); - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%zu bytes)\n", + printk(BIOS_DEBUG, "MRC: Relocate data from %p to %p (%zu bytes)\n", data, cache, size); mrc_cache_fill(cache, data, size, version); @@ -262,48 +342,35 @@ mrc_cache_next_slot(const struct mrc_data_region *region, return next_slot; } -/* Protect RW_MRC_CACHE region with a Protected Range Register */ -static int protect_mrc_cache(const struct mrc_data_region *region) -{ -#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) - if (nvm_is_write_protected() <= 0) { - printk(BIOS_INFO, "NOT enabling PRR for RW_MRC_CACHE region\n"); - return 1; - } - - if (nvm_protect(region->base, region->size) < 0) { - printk(BIOS_ERR, "ERROR setting PRR for RW_MRC_CACHE region\n"); - return -1; - } - - printk(BIOS_INFO, "Enabled Protected Range on RW_MRC_CACHE region\n"); -#endif - return 0; -} - static void update_mrc_cache(void *unused) { const struct mrc_saved_data *current_boot; const struct mrc_saved_data *current_saved; const struct mrc_saved_data *next_slot; struct mrc_data_region region; + const char *region_name = DEFAULT_MRC_CACHE; - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + printk(BIOS_DEBUG, "MRC: Updating cache data.\n"); - current_boot = cbmem_find(CBMEM_ID_MRCDATA); - if (!current_boot) { - printk(BIOS_ERR, "No MRC cache in cbmem.\n"); + if (vboot_recovery_mode_enabled() && mrc_recovery_cache_exists()) + region_name = RECOVERY_MRC_CACHE; + + printk(BIOS_ERR, "MRC: Cache region selected - %s\n", region_name); + + if (mrc_cache_get_region(region_name, &region)) { + printk(BIOS_ERR, "MRC: Could not obtain cache region.\n"); return; } - if (mrc_cache_get_region(&region)) { - printk(BIOS_ERR, "Could not obtain MRC cache region.\n"); - return; + current_boot = cbmem_find(CBMEM_ID_MRCDATA); + if (!current_boot) { + printk(BIOS_ERR, "MRC: No cache in cbmem.\n"); + goto out; } if (!mrc_cache_valid(&region, current_boot)) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; + printk(BIOS_ERR, "MRC: Cache data in cbmem invalid.\n"); + goto out; } current_saved = NULL; @@ -313,20 +380,20 @@ static void update_mrc_cache(void *unused) if (current_saved->size == current_boot->size && !memcmp(&current_saved->data[0], &current_boot->data[0], current_saved->size)) { - printk(BIOS_DEBUG, "MRC cache up to date.\n"); - protect_mrc_cache(&region); - return; + printk(BIOS_DEBUG, "MRC: Cache up to date.\n"); + goto out; } } next_slot = mrc_cache_next_slot(&region, current_saved); if (!mrc_slot_valid(&region, next_slot, current_boot)) { - printk(BIOS_DEBUG, "Slot @ %p is invalid.\n", next_slot); + printk(BIOS_DEBUG, "MRC: Slot @ %p is invalid.\n", next_slot); if (!nvm_is_erased(region.base, region.size)) { if (nvm_erase(region.base, region.size) < 0) { - printk(BIOS_DEBUG, "Failure erasing region.\n"); - return; + printk(BIOS_DEBUG, "MRC: Failure erasing " + "region %s.\n", region_name); + goto out; } } next_slot = region.base; @@ -334,10 +401,12 @@ static void update_mrc_cache(void *unused) if (nvm_write((void *)next_slot, current_boot, current_boot->size + sizeof(*current_boot))) { - printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n", - next_slot); + printk(BIOS_DEBUG, "MRC: Failure writing cache to %s(%p).\n", + region_name, next_slot); } - protect_mrc_cache(&region); + +out: + protect_mrc_cache(&region, region_name); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 9b14c1e..09ab306 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -19,6 +19,9 @@ #include <stddef.h> #include <stdint.h> +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" + /* Wrapper object to save MRC information. */ struct mrc_saved_data { uint32_t signature;

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Patch set updated for coreboot: mainboard/google/reef: Add support for RECOVERY_MRC_CACHE
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17243 -gerrit commit 1a7694d95d94c08ce25dc581cbd98a10e0da29d3 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Nov 6 00:07:08 2016 -0700 mainboard/google/reef: Add support for RECOVERY_MRC_CACHE 1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper functions for getting and clearing event for recovery mode with memory retraining. 3. Select HAS_RECOVERY_MRC_CACHE. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/chromeos.c | 24 ++++++++++++++++++++++-- src/mainboard/google/reef/chromeos.fmd | 3 ++- 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 6045f47..bb7a531 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -33,6 +33,7 @@ config DRIVER_TPM_I2C_IRQ config CHROMEOS select LID_SWITCH if BASEBOARD_REEF_LAPTOP + select HAS_RECOVERY_MRC_CACHE config DRIVERS_I2C_DA7219 default y diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 58c2cd8..ddb0cc4 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -50,9 +50,23 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check if the EC has posted the keyboard recovery event. */ + /* + * Check if the EC has posted the keyboard recovery event with/without + * memory retrain. + */ return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))); +} + +int get_recovery_mode_retrain_switch(void) +{ + /* + * Check if the EC has posted the keyboard recovery event with memory + * retrain. + */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } int clear_recovery_mode_switch(void) @@ -62,6 +76,12 @@ int clear_recovery_mode_switch(void) EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } +int clear_recovery_mode_retrain_switch(void) +{ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); +} + int get_write_protect_state(void) { /* Read PCH_WP GPIO. */ diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index d25a9b2..c6a413d 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -13,7 +13,8 @@ FLASH 16M { } } MISC_RW@0x400000 0x4a000 { - RW_MRC_CACHE@0x0 0x40000 + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x30000 RW_ELOG@0x40000 0x4000 RW_SHARED@0x44000 0x4000 { SHARED_DATA@0x0 0x2000

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Patch set updated for coreboot: mrc: Add support for separate training cache in recovery mode
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17242 -gerrit commit 941ef48b2d7c8a11127e193fca63cbcda28690d5 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:57:02 2016 -0700 mrc: Add support for separate training cache in recovery mode 1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RECOVERY_MRC_CACHE before jumping from RO to RW in recovery mode. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/fsp2_0/memory_init.c | 18 ---- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/mrc_cache.c | 159 +++++++++++++++++++++++---------- src/soc/intel/common/mrc_cache.h | 3 + 4 files changed, 121 insertions(+), 63 deletions(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..798cd87 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -55,13 +55,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) printk(BIOS_ERR, "Failed to stash MRC data\n"); } -/* - * On every trip to recovery, newly generated MRC data is stored with this - * version since it is not expected to be a legit version. This ensures that on - * next normal boot, memory re-training occurs and new MRC data is stored. - */ -#define MRC_DEAD_VERSION (0xdeaddead) - static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -89,10 +82,6 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request!\n"); - /* Now that CBMEM is up, save the list so ramstage can use it */ - if (vboot_recovery_mode_enabled()) - fsp_version = MRC_DEAD_VERSION; - save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ @@ -113,14 +102,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { - printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); - return; - } - if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { - printk(BIOS_SPEW, "MRC cache was not found\n"); return; } diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index affec55..5d8bf66 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -27,6 +27,10 @@ config MRC_SETTINGS_PROTECT bool "Enable protection on MRC settings" default n +config HAS_RECOVERY_MRC_CACHE + bool + default n + endif # CACHE_MRC_SETTINGS config DISPLAY_MTRRS diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index c123da9..186c556 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -34,13 +34,37 @@ struct mrc_data_region { uint32_t size; }; +/* Protect RW_MRC_CACHE region with a Protected Range Register */ +static int protect_mrc_cache(const struct mrc_data_region *region, + const char *name) +{ +#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) + if (nvm_is_write_protected() <= 0) { + printk(BIOS_INFO, "MRC: NOT enabling PRR for %s.\n", name); + return 1; + } + + if (nvm_protect(region->base, region->size) < 0) { + printk(BIOS_ERR, "MRC: ERROR setting PRR for %s.\n", name); + return -1; + } + + printk(BIOS_INFO, "MRC: Enabled Protected Range on %s.\n", name); +#endif + return 0; +} + /* common code */ -static int mrc_cache_get_region(struct mrc_data_region *region) +static int mrc_cache_get_region(const char *name, + struct mrc_data_region *region) { bool located_by_fmap = true; struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev)) + region->base = NULL; + region->size = 0; + + if (fmap_locate_area_as_rdev(name, &rdev)) located_by_fmap = false; /* CHROMEOS builds must get their MRC cache from FMAP. */ @@ -61,6 +85,19 @@ static int mrc_cache_get_region(struct mrc_data_region *region) return 0; } +/* + * Check if RECOVERY_MRC_CACHE exists on this device. + * Returns 1 if region exists, 0 otherwise. + */ +static int mrc_recovery_cache_exists(void) +{ + if (!IS_ENABLED(CONFIG_CHROMEOS) || + !IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) + return 0; + + return fmap_region_exists(RECOVERY_MRC_CACHE); +} + static int mrc_cache_in_region(const struct mrc_data_region *region, const struct mrc_saved_data *cache) { @@ -148,22 +185,65 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region, return -1; if (verified_cache->version != version) { - printk(BIOS_DEBUG, "MRC cache version mismatch: %x vs %x\n", + printk(BIOS_DEBUG, "MRC: cache version mismatch: %x vs %x\n", verified_cache->version, version); return -1; } - printk(BIOS_DEBUG, "MRC cache slot %d @ %p\n", slot-1, verified_cache); + printk(BIOS_DEBUG, "MRC: cache slot %d @ %p\n", slot-1, verified_cache); return 0; } +static const char *mrc_cache_get_region_name(void) +{ + struct mrc_data_region region; + + /* + * In recovery mode: + * 1. If recovery cache does not exist, retrain memory. + * 2. Else if memory retrain switch is set, retrain memory. + * 3. Else use RECOVERY_MRC_CACHE. + */ + if (vboot_recovery_mode_enabled()) { + if (!mrc_recovery_cache_exists()) + return NULL; + + if (vboot_recovery_mode_memory_retrain()) + return NULL; + + return RECOVERY_MRC_CACHE; + } + + /* + * In normal mode: + * 1. If recovery mrc cache exists, protect it. + * 2. Use DEFAULT_MRC_CACHE. + */ + if (mrc_recovery_cache_exists() && + !mrc_cache_get_region(RECOVERY_MRC_CACHE, &region)) { + printk(BIOS_ERR, "MRC: Protecting recovery cache.\n"); + protect_mrc_cache(&region, RECOVERY_MRC_CACHE); + } + + return DEFAULT_MRC_CACHE; +} + int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, - uint32_t version) + uint32_t version) { struct mrc_data_region region; + const char *region_name = NULL; + + region_name = mrc_cache_get_region_name(); + if (!region_name) { + printk(BIOS_ERR, "MRC: Requires memory retraining\n"); + return -1; + } + + printk(BIOS_ERR, "MRC: Using data from %s\n", region_name); - if (mrc_cache_get_region(&region) < 0) + if (mrc_cache_get_region(region_name, &region) < 0) return -1; return __mrc_cache_get_current(&region, cache, version); @@ -196,14 +276,14 @@ int mrc_cache_stash_data_with_version(const void *data, size_t size, cache = cbmem_add(CBMEM_ID_MRCDATA, cbmem_size); if (cache == NULL) { - printk(BIOS_ERR, "No space in cbmem for MRC data.\n"); + printk(BIOS_ERR, "MRC: No space in cbmem for training data.\n"); return -1; } /* Clear alignment padding bytes at end of data. */ memset(&cache->data[size], 0, cbmem_size - size - sizeof(*cache)); - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%zu bytes)\n", + printk(BIOS_DEBUG, "MRC: Relocate data from %p to %p (%zu bytes)\n", data, cache, size); mrc_cache_fill(cache, data, size, version); @@ -262,48 +342,35 @@ mrc_cache_next_slot(const struct mrc_data_region *region, return next_slot; } -/* Protect RW_MRC_CACHE region with a Protected Range Register */ -static int protect_mrc_cache(const struct mrc_data_region *region) -{ -#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) - if (nvm_is_write_protected() <= 0) { - printk(BIOS_INFO, "NOT enabling PRR for RW_MRC_CACHE region\n"); - return 1; - } - - if (nvm_protect(region->base, region->size) < 0) { - printk(BIOS_ERR, "ERROR setting PRR for RW_MRC_CACHE region\n"); - return -1; - } - - printk(BIOS_INFO, "Enabled Protected Range on RW_MRC_CACHE region\n"); -#endif - return 0; -} - static void update_mrc_cache(void *unused) { const struct mrc_saved_data *current_boot; const struct mrc_saved_data *current_saved; const struct mrc_saved_data *next_slot; struct mrc_data_region region; + const char *region_name = DEFAULT_MRC_CACHE; - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + printk(BIOS_DEBUG, "MRC: Updating cache data.\n"); - current_boot = cbmem_find(CBMEM_ID_MRCDATA); - if (!current_boot) { - printk(BIOS_ERR, "No MRC cache in cbmem.\n"); + if (vboot_recovery_mode_enabled() && mrc_recovery_cache_exists()) + region_name = RECOVERY_MRC_CACHE; + + printk(BIOS_ERR, "MRC: Cache region selected - %s\n", region_name); + + if (mrc_cache_get_region(region_name, &region)) { + printk(BIOS_ERR, "MRC: Could not obtain cache region.\n"); return; } - if (mrc_cache_get_region(&region)) { - printk(BIOS_ERR, "Could not obtain MRC cache region.\n"); - return; + current_boot = cbmem_find(CBMEM_ID_MRCDATA); + if (!current_boot) { + printk(BIOS_ERR, "MRC: No cache in cbmem.\n"); + goto out; } if (!mrc_cache_valid(&region, current_boot)) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; + printk(BIOS_ERR, "MRC: Cache data in cbmem invalid.\n"); + goto out; } current_saved = NULL; @@ -313,20 +380,20 @@ static void update_mrc_cache(void *unused) if (current_saved->size == current_boot->size && !memcmp(&current_saved->data[0], &current_boot->data[0], current_saved->size)) { - printk(BIOS_DEBUG, "MRC cache up to date.\n"); - protect_mrc_cache(&region); - return; + printk(BIOS_DEBUG, "MRC: Cache up to date.\n"); + goto out; } } next_slot = mrc_cache_next_slot(&region, current_saved); if (!mrc_slot_valid(&region, next_slot, current_boot)) { - printk(BIOS_DEBUG, "Slot @ %p is invalid.\n", next_slot); + printk(BIOS_DEBUG, "MRC: Slot @ %p is invalid.\n", next_slot); if (!nvm_is_erased(region.base, region.size)) { if (nvm_erase(region.base, region.size) < 0) { - printk(BIOS_DEBUG, "Failure erasing region.\n"); - return; + printk(BIOS_DEBUG, "MRC: Failure erasing " + "region %s.\n", region_name); + goto out; } } next_slot = region.base; @@ -334,10 +401,12 @@ static void update_mrc_cache(void *unused) if (nvm_write((void *)next_slot, current_boot, current_boot->size + sizeof(*current_boot))) { - printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n", - next_slot); + printk(BIOS_DEBUG, "MRC: Failure writing cache to %s(%p).\n", + region_name, next_slot); } - protect_mrc_cache(&region); + +out: + protect_mrc_cache(&region, region_name); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 9b14c1e..09ab306 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -19,6 +19,9 @@ #include <stddef.h> #include <stdint.h> +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" + /* Wrapper object to save MRC information. */ struct mrc_saved_data { uint32_t signature;

1 0

Patch set updated for coreboot: mainboard/google/reef: Add support for RECOVERY_MRC_CACHE
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17243 -gerrit commit d68e74fe7a39b87cfd1d4cb9da05cde96c64d599 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Nov 6 00:07:08 2016 -0700 mainboard/google/reef: Add support for RECOVERY_MRC_CACHE 1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper functions for getting and clearing event for recovery mode with memory retraining. 3. Select HAS_RECOVERY_MRC_CACHE. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/chromeos.c | 24 ++++++++++++++++++++++-- src/mainboard/google/reef/chromeos.fmd | 3 ++- 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 6045f47..bb7a531 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -33,6 +33,7 @@ config DRIVER_TPM_I2C_IRQ config CHROMEOS select LID_SWITCH if BASEBOARD_REEF_LAPTOP + select HAS_RECOVERY_MRC_CACHE config DRIVERS_I2C_DA7219 default y diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 58c2cd8..ddb0cc4 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -50,9 +50,23 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check if the EC has posted the keyboard recovery event. */ + /* + * Check if the EC has posted the keyboard recovery event with/without + * memory retrain. + */ return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))); +} + +int get_recovery_mode_retrain_switch(void) +{ + /* + * Check if the EC has posted the keyboard recovery event with memory + * retrain. + */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } int clear_recovery_mode_switch(void) @@ -62,6 +76,12 @@ int clear_recovery_mode_switch(void) EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } +int clear_recovery_mode_retrain_switch(void) +{ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); +} + int get_write_protect_state(void) { /* Read PCH_WP GPIO. */ diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index d25a9b2..c6a413d 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -13,7 +13,8 @@ FLASH 16M { } } MISC_RW@0x400000 0x4a000 { - RW_MRC_CACHE@0x0 0x40000 + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x30000 RW_ELOG@0x40000 0x4000 RW_SHARED@0x44000 0x4000 { SHARED_DATA@0x0 0x2000

1 0

Patch merged into coreboot/master: Add option to use Ada code in ramstage
by gerrit＠coreboot.org 06 Nov '16

06 Nov '16

the following patch was just integrated into master: commit e0ed9025cf7453212e5e5a845e34e0b7ecfa3eb9 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Oct 7 12:58:17 2016 +0200 Add option to use Ada code in ramstage If selected, libgnat will be linked into ramstage. And, to support Ada package intializations, we have to call ramstage_adainit(). Change-Id: I11417db21f16bf3007739a097d63fd592344bce3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16944 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16944 for details. -gerrit

1 0

New patch to review for coreboot: ec/lenovo/h8: Add USB Always On
by Nicola Corna 06 Nov '16

06 Nov '16

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17252 -gerrit commit 27ec5093ed622a32930f8891dbec45366a49049b Author: Nicola Corna <nicola(a)corna.info> Date: Sat Nov 5 16:06:59 2016 +0100 ec/lenovo/h8: Add USB Always On USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN (bit 0) is internal name for enabling this feature while AOCF (bits 2 and 3) is the configuration field. According to Peter Stuge, AOCF can be configured in this way: 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also adds a new configuration field in the CMOS of the X220 and the X201 to activate this feature. It probably can be also added to all the Thinkpads that support this functionality. With this functionality USB devices are able to negotiate full power from the dedicated port (usually the yellow one) even in S3. Tested on a X201 and X220 with an Android smartphone: with this feature enabled it shows "Charging" when connected during S3, without it it shows "Charging slowly" (or it doesn't charge at all on the X201). Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/ec/lenovo/h8/h8.c | 1 + src/ec/lenovo/h8/h8.h | 5 +++++ src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 6 ++++-- src/mainboard/lenovo/x201/smihandler.c | 17 +++++++++++++++-- src/mainboard/lenovo/x220/cmos.default | 1 + src/mainboard/lenovo/x220/cmos.layout | 5 ++++- src/mainboard/lenovo/x220/smihandler.c | 17 +++++++++++++++-- 8 files changed, 46 insertions(+), 7 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 703acad..2484b3b 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -313,6 +313,7 @@ static void h8_enable(struct device *dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_DISABLE); h8_trackpoint_enable(1); h8_usb_power_enable(1); diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index d3803c0..c893396 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -64,6 +64,11 @@ void h8_mainboard_init_dock (void); #define H8_LED_CONTROL_ON 0x80 #define H8_LED_CONTROL_BLINK 0xc0 +#define H8_USB_ALWAYS_ON 0x0d +#define H8_USB_ALWAYS_ON_DISABLE 0x00 +#define H8_USB_ALWAYS_ON_AC_ONLY 0x0d +#define H8_USB_ALWAYS_ON_AC_BAT 0x01 + #define H8_LED_CONTROL_POWER_LED 0x00 #define H8_LED_CONTROL_BAT0_LED 0x01 #define H8_LED_CONTROL_BAT1_LED 0x02 diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 50d17ae..9f1e31d 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +usb_always_on=Disable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 2a91eb7..36b09f2 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -70,8 +70,7 @@ entries 419 1 e 1 power_management_beeps 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode - -#422 2 r 0 unused +422 2 e 11 usb_always_on # coreboot config options: northbridge 424 3 e 10 gfx_uma_size @@ -123,6 +122,9 @@ enumerations 10 3 128M 10 5 96M 10 6 160M +11 0 Disable +11 1 AC only +11 2 AC and battery # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 591a521..60186d3 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -178,10 +179,22 @@ int mainboard_smi_apmc(u8 data) void mainboard_smi_sleep(u8 slp_typ) { + u8 val; + + if (get_option(&val, "usb_always_on") != CB_SUCCESS) + val = 0; + + if (val == 1) + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_AC_ONLY); + else if (val == 2) + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_AC_BAT); + else + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_DISABLE); + if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); + val = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { + if (val & 0x14) { /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 1b8e212..91331ab 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -10,6 +10,7 @@ wwan=Enable wlan=Enable touchpad=Enable sata_mode=AHCI +usb_always_on=Disable fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 143ee80..bc506f1 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -69,7 +69,7 @@ entries 418 1 e 1 sticky_fn 419 1 e 1 power_management_beeps 421 1 e 9 sata_mode -#422 2 r 1 unused +422 2 e 12 usb_always_on # coreboot config options: cpu 424 1 e 2 hyper_threading @@ -134,6 +134,9 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Disable +12 1 AC only +12 2 AC and battery # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 08554c9..71af2cc 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -133,10 +134,22 @@ int mainboard_smi_apmc(u8 data) void mainboard_smi_sleep(u8 slp_typ) { + u8 val; + + if (get_option(&val, "usb_always_on") != CB_SUCCESS) + val = 0; + + if (val == 1) + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_AC_ONLY); + else if (val == 2) + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_AC_BAT); + else + ec_write(H8_USB_ALWAYS_ON, H8_USB_ALWAYS_ON_DISABLE); + if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); + val = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { + if (val & 0x14) { /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); }

1 0

Patch set updated for coreboot: soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17067 -gerrit commit 55a7f10a78e272228b869e7884ce0fcec485d9cc Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 10:57:58 2016 +0530 soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control This patch updates below info, [1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not being used. Hence, removing unnecessary defines. [2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0 external thermal sensor. These trip points are being used by _ACx methods to control the fan speed on Skylake-U fan based Lars and Kunimitsu platforms. [3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to control the fan speed as per the CPU temperature trip points. [4] Newly added _ACx methods for thermal sensor TSR0 in this patch has nothing to do with DPTF_CPU_ACTIVE_AC*. We can control fan speed using various different thermal sensors. In this patch, we have added new _ACx methods for TSR0 thermal sensor. We run the fan at different speeds to cool down the system at different TSR0 temperatures. Similarly, we considered CPU sensor temperature values and ran the fan at different speeds to cool down the system. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified these _ACx methods with _ART table on these boards with different workloads. Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/332368 --- src/soc/intel/skylake/acpi/dptf/cpu.asl | 20 ---------------- src/soc/intel/skylake/acpi/dptf/thermal.asl | 37 +++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 32e8863..6278b9f 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -22,26 +22,6 @@ #define DPTF_CPU_CRITICAL 90 #endif -#ifndef DPTF_CPU_ACTIVE_AC0 -#define DPTF_CPU_ACTIVE_AC0 90 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC1 -#define DPTF_CPU_ACTIVE_AC1 80 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC2 -#define DPTF_CPU_ACTIVE_AC2 70 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC3 -#define DPTF_CPU_ACTIVE_AC3 60 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC4 -#define DPTF_CPU_ACTIVE_AC4 50 -#endif - External (\_PR.CP00._PSS, PkgObj) External (\_PR.CP00._TSS, PkgObj) External (\_PR.CP00._TPC, MethodObj) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index d9bd9c0..a94c278 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -110,6 +110,43 @@ Device (TSR0) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } + + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } + + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } + + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } + + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } + + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } + + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif } #endif

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Patch set updated for coreboot: mainboard/intel/kblrvp: Update devicetree.cb
by Naresh Solanki 06 Nov '16

06 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17247 -gerrit commit fb566a6ee472e8b4593bc7c4f82c160d80179b94 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 13:37:34 2016 +0530 mainboard/intel/kblrvp: Update devicetree.cb Update devicetree.cb as per RVP3 mainboard. Disable pull down for power button in gpio.h. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/devicetree.cb | 192 ++++++++++--------------------- src/mainboard/intel/kblrvp/gpio.h | 4 +- 2 files changed, 64 insertions(+), 132 deletions(-) diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb index 8dded98..ad4d877 100644 --- a/src/mainboard/intel/kblrvp/devicetree.cb +++ b/src/mainboard/intel/kblrvp/devicetree.cb @@ -1,14 +1,14 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable" = "1" + register "deep_s5_enable" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -23,9 +23,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" @@ -63,23 +60,10 @@ chip soc/intel/skylake register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ + .psi2threshold = 0x14, \ .psi3threshold = 0x4, \ .psi3enable = 1, \ .psi4enable = 1, \ @@ -124,7 +108,7 @@ chip soc/intel/skylake .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .voltage_limit = 0x5F0, \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -142,29 +126,56 @@ chip soc/intel/skylake register "FspSkipMpInit" = "1" - # Enable Root port 1 and 5. + # Enable Root ports. + # PCIE Port 1 x4 -> SLOT1 register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpClkReqNumber[0]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card) - register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera - register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - - register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # PCIE Port 5 x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + + # PCIE Port 6 x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + # PCIE Port 9 x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + + # PCIE Port 10 x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "1" # Enable SSIC for WWAN # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ @@ -181,9 +192,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # PL2 override 25W - register "tdp_pl2_override" = "25" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" @@ -191,7 +199,7 @@ chip soc/intel/skylake register "VmxEnable" = "0" # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio_default" = "GPP_D10" device cpu_cluster 0 on device lapic 0 on end @@ -202,23 +210,8 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 @@ -229,61 +222,14 @@ chip soc/intel/skylake device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "1" - register "jkdet_pull_up" = "1" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - register "device_present_gpio" = "GPP_E3" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - register "device_present_gpio" = "GPP_E3" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 19.2 on end + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.0 on end # PCI Express Port 9 x1 WLAN + device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 @@ -291,24 +237,10 @@ chip soc/intel/skylake device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface + device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "device_present_gpio" = "GPP_E3" - register "device_present_gpio_invert" = "1" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h index f8ee994..5e251d8 100644 --- a/src/mainboard/intel/kblrvp/gpio.h +++ b/src/mainboard/intel/kblrvp/gpio.h @@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), @@ -204,4 +204,4 @@ static const struct pad_config early_gpio_table[] = { #endif -#endif \ No newline at end of file +#endif

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coreboot-gerrit November 2016