coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: riscv: change payload() to pass the config string pointer as arg0
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17254 -gerrit commit 97458df34c3ca8329fc8e564fac19e0d8f04c748 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 16:13:52 2016 -0800 riscv: change payload() to pass the config string pointer as arg0 The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. A pointer to this string is available at a platform-dependent location, default 0x100c on all extant platforms. Define a new config variable, ARCH_CONFIGSTRING_RISCV, to contain this location and change payload() arguments so arg0 is this pointer and arg1 is the pointer to the payload. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Kconfig | 5 +++++ src/arch/riscv/boot.c | 4 ++-- src/arch/riscv/payload.S | 4 +++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb70..7c43da4 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -19,3 +19,8 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + +config ARCH_CONFIGSTRING_RISCV + hex "Location of pointer to RISCV config string" + default 0x100c + depends on ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ff1844e..598377c 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -22,12 +22,12 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); - void riscvpayload(void *); + void riscvpayload(void *configstring, void *payload); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(doit); + riscvpayload((void *)CONFIG_ARCH_CONFIGSTRING_RISCV, doit); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index 3261a80..e50a589 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -11,10 +11,12 @@ * GNU General Public License for more details. */ +// "return" to a payload pointed to by a1 with +// a pointer to the config string in a0. .global riscvpayload riscvpayload: /* Jump to a0 in S-mode */ - mv t0,a0 + mv t0,a1 csrw mepc, t0 csrr t0, mstatus li t1, ~(3<<11)

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Patch set updated for coreboot: riscv: map first 2GiB of physical memory at the top of virtual address space
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17233 -gerrit commit 6779d7f56aac30d8e4baa682a8cd3309453862fa Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Nov 4 11:27:25 2016 -0700 riscv: map first 2GiB of physical memory at the top of virtual address space We were mapping physical to virtual 1:1, which makes no sense; most kernels want to start at high negative address space. Doing it this way ensures that we're following the intent of the RISCV designers, i.e that virtual addresses are correct at the start; and that the kernel does not have to unmap the low physical addresses once it starts. Change-Id: I8c577ad885891b4c33c20077995abbd90f355f1c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/virtual_memory.c | 43 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 999d73c..7091f02 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -168,12 +168,40 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, pte_t *sbi_pt) // IO space. root_pt[0] = pte_create(0, PTE_W|PTE_R, 0); - root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + root_pt[1] = pte_create(0x40000000 >> RISCV_PGSHIFT, PTE_W|PTE_R, 0); // Start of RAM - root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, - PTE_W|PTE_R, 0); + // + // A RISCV goal is that Machine or Hypervisor modes be able + // start a Supervisor (kernel) at the C entry point. The + // intent is that firmware creates the virtual memory maps for + // the kernel to use. + // + // Question: what is the virtual address of physical memory + // for a kernel? Hey, glad you asked! In most kernels out + // there, physical memory is mapped at the top of the virtual + // address space. The express intent of the RISCV designers + // (I asked them) is that we be able to enter a kernel at + // main() in C, with no assembly needed. + // + // This is a neat idea that may not quite work out. For + // example: where's the stack go? Once you start in + // Supervisor mode, you are using virtual addresses set up by + // coreboot. So you can't use the coreboot stack, it's mapped + // to low physical addresses. You *should* not use the + // coreboot stack, your kernel may need it in a different + // place. So the kernel needs to change the stack, in ... a + // bit of startup assembly code, what else? Oh well. Map + // physical to high virtual. It's the most common way to + // go. Kernels that want to put kernel virtual addresses based + // at 0 will need to fixup page tables in ... a bit of startup + // assembly code :-) + // + // TODO: use a constant for the number of PTEs per page, when + // (hopefully) newer RISCV toolchains define that constant. + root_pt[0x1ff] = pte_create(0x80000000 >> RISCV_PGSHIFT, + PTE_R | PTE_W | PTE_X, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -198,9 +226,14 @@ void initVirtualMemory(void) { } // TODO: Figure out how to grab this from cbfs + // N.B. We used to map phsyical from 0x81000000, + // but since kernels need to be able to see the page tables + // created by firmware, we're going to map from start of RAM. + // All this is subject to change as we learn more. Much + // about RISCV is still in flux. printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x81000000; - uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t physicalStart = 0x80000000; + uintptr_t virtualStart = 0xffffffff80000000; init_vm(virtualStart, physicalStart, (pte_t *)_pagetables); mb(); flush_tlb();

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Patch set updated for coreboot: google/chromeec: Sync ec_commands.h host events with ec codebase
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17240 -gerrit commit 322f747c6a474ba40aba15a0d4c48af432d0cad0 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Nov 6 00:12:23 2016 -0700 google/chromeec: Sync ec_commands.h host events with ec codebase BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully Change-Id: Ibfa5681e16a97e342633104d2aae1fb0402939b8 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/ec/google/chromeec/ec_commands.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 4a551c2..ec404f0 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -471,9 +471,21 @@ enum host_event_code { /* Emulate MKBP event */ EC_HOST_EVENT_MKBP = 27, + /* EC desires to change state of host-controlled USB mux */ + EC_HOST_EVENT_USB_MUX = 28, + /* TABLET/LAPTOP mode event*/ EC_HOST_EVENT_MODE_CHANGE = 29, + /* Keyboard recovery combo with hardware reinitialization */ + EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30, + + /* + * Reserve this last bit to indicate that at least one bit in a + * secondary host event word is set. See crbug.com/633646. + */ + EC_HOST_EVENT_EXTENDED = 31, + /* * The high bit of the event mask is not used as a host event code. If * it reads back as set, then the entire event mask should be

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Patch set updated for coreboot: vboot: Add support for recovery mode with forced memory retraining
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17241 -gerrit commit 30745ed7463b66ef5f0b2c3817d278f092987027 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:52:08 2016 -0700 vboot: Add support for recovery mode with forced memory retraining 1. Add new function vboot_recovery_mode_memory_retrain that indicates if recovery mode requires memory retraining to be performed. 2. Add helper functions {get,clear}_recovery_mode_retrain_switch to read memory retrain switch. These are provided as weak functions which should be implemented by mainboard just like {get,clear}_recovery_mode_switch. 3. Additionally, the switch for recovery mode with forced memory training should be cleared when recovery mode switch is cleared. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified behavior of recovery mode with forced memory retraining on reef. Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/include/bootmode.h | 2 ++ src/vboot/bootmode.c | 15 +++++++++++++++ src/vboot/vboot_common.h | 1 + src/vboot/vboot_handoff.c | 1 + 4 files changed, 19 insertions(+) diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 21aa386..012bc39 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -22,7 +22,9 @@ int get_write_protect_state(void); int get_sw_write_protect_state(void); int get_developer_mode_switch(void); int get_recovery_mode_switch(void); +int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); +int clear_recovery_mode_retrain_switch(void); int get_wipeout_mode_switch(void); int get_lid_switch(void); diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 12a4dc0..34377e1 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -162,6 +162,21 @@ int vboot_recovery_mode_enabled(void) return !!vboot_check_recovery_request(); } +int __attribute__((weak)) get_recovery_mode_retrain_switch(void) +{ + return 0; +} + +int __attribute__((weak)) clear_recovery_mode_retrain_switch(void) +{ + return 0; +} + +int vboot_recovery_mode_memory_retrain(void) +{ + return get_recovery_mode_retrain_switch(); +} + int vboot_developer_mode_enabled(void) { if (!IS_ENABLED(CONFIG_VBOOT)) diff --git a/src/vboot/vboot_common.h b/src/vboot/vboot_common.h index 59fd44c..956b54c 100644 --- a/src/vboot/vboot_common.h +++ b/src/vboot/vboot_common.h @@ -107,5 +107,6 @@ void verstage_mainboard_init(void); /* Check boot modes */ int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); +int vboot_recovery_mode_memory_retrain(void); #endif /* __VBOOT_VBOOT_COMMON_H__ */ diff --git a/src/vboot/vboot_handoff.c b/src/vboot/vboot_handoff.c index b0bd04c..a2409cf 100644 --- a/src/vboot/vboot_handoff.c +++ b/src/vboot/vboot_handoff.c @@ -163,6 +163,7 @@ void vboot_fill_handoff(void) * is known to be up. */ clear_recovery_mode_switch(); + clear_recovery_mode_retrain_switch(); } /*

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Patch set updated for coreboot: mrc: Add support for separate training cache in recovery mode
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17242 -gerrit commit 6fbd53a4cfcd43b6dc8b81928afdd5b97d6329c2 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:57:02 2016 -0700 mrc: Add support for separate training cache in recovery mode 1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RECOVERY_MRC_CACHE before jumping from RO to RW in recovery mode. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/fsp2_0/memory_init.c | 21 +---- src/include/elog.h | 1 + src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/mrc_cache.c | 168 +++++++++++++++++++++++---------- src/soc/intel/common/mrc_cache.h | 3 + 5 files changed, 128 insertions(+), 69 deletions(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index d0a22ce..a561d76 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -55,13 +55,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) printk(BIOS_ERR, "Failed to stash MRC data\n"); } -/* - * On every trip to recovery, newly generated MRC data is stored with this - * version since it is not expected to be a legit version. This ensures that on - * next normal boot, memory re-training occurs and new MRC data is stored. - */ -#define MRC_DEAD_VERSION (0xdeaddead) - static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -89,10 +82,6 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request!\n"); - /* Now that CBMEM is up, save the list so ramstage can use it */ - if (vboot_recovery_mode_enabled()) - fsp_version = MRC_DEAD_VERSION; - save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ @@ -113,16 +102,8 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) return; - /* Don't use saved training data when recovery mode is enabled. */ - if (vboot_recovery_mode_enabled()) { - printk(BIOS_SPEW, "Recovery mode. Not using MRC cache.\n"); + if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) return; - } - - if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { - printk(BIOS_SPEW, "MRC cache was not found\n"); - return; - } /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; diff --git a/src/include/elog.h b/src/include/elog.h index 7fdcda7..fec9d09 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -152,6 +152,7 @@ struct elog_event_data_me_extended { /* Memory Cache Update */ #define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa #define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 #define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 #define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 struct elog_event_mem_cache_update { diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index affec55..5d8bf66 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -27,6 +27,10 @@ config MRC_SETTINGS_PROTECT bool "Enable protection on MRC settings" default n +config HAS_RECOVERY_MRC_CACHE + bool + default n + endif # CACHE_MRC_SETTINGS config DISPLAY_MTRRS diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index bef3ba2..cecdfbe 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -35,13 +35,37 @@ struct mrc_data_region { uint32_t size; }; +/* Protect RW_MRC_CACHE region with a Protected Range Register */ +static int protect_mrc_cache(const struct mrc_data_region *region, + const char *name) +{ +#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) + if (nvm_is_write_protected() <= 0) { + printk(BIOS_INFO, "MRC: NOT enabling PRR for %s.\n", name); + return 1; + } + + if (nvm_protect(region->base, region->size) < 0) { + printk(BIOS_ERR, "MRC: ERROR setting PRR for %s.\n", name); + return -1; + } + + printk(BIOS_INFO, "MRC: Enabled Protected Range on %s.\n", name); +#endif + return 0; +} + /* common code */ -static int mrc_cache_get_region(struct mrc_data_region *region) +static int mrc_cache_get_region(const char *name, + struct mrc_data_region *region) { bool located_by_fmap = true; struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev)) + region->base = NULL; + region->size = 0; + + if (fmap_locate_area_as_rdev(name, &rdev)) located_by_fmap = false; /* CHROMEOS builds must get their MRC cache from FMAP. */ @@ -62,6 +86,19 @@ static int mrc_cache_get_region(struct mrc_data_region *region) return 0; } +/* + * Check if RECOVERY_MRC_CACHE exists on this device. + * Returns 1 if region exists, 0 otherwise. + */ +static int mrc_recovery_cache_exists(void) +{ + if (!IS_ENABLED(CONFIG_CHROMEOS) || + !IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE)) + return 0; + + return fmap_region_exists(RECOVERY_MRC_CACHE); +} + static int mrc_cache_in_region(const struct mrc_data_region *region, const struct mrc_saved_data *cache) { @@ -149,22 +186,65 @@ static int __mrc_cache_get_current(const struct mrc_data_region *region, return -1; if (verified_cache->version != version) { - printk(BIOS_DEBUG, "MRC cache version mismatch: %x vs %x\n", + printk(BIOS_DEBUG, "MRC: cache version mismatch: %x vs %x\n", verified_cache->version, version); return -1; } - printk(BIOS_DEBUG, "MRC cache slot %d @ %p\n", slot-1, verified_cache); + printk(BIOS_DEBUG, "MRC: cache slot %d @ %p\n", slot-1, verified_cache); return 0; } +static const char *mrc_cache_get_region_name(void) +{ + struct mrc_data_region region; + + /* + * In recovery mode: + * 1. If recovery cache does not exist, retrain memory. + * 2. Else if memory retrain switch is set, retrain memory. + * 3. Else use RECOVERY_MRC_CACHE. + */ + if (vboot_recovery_mode_enabled()) { + if (!mrc_recovery_cache_exists()) + return NULL; + + if (vboot_recovery_mode_memory_retrain()) + return NULL; + + return RECOVERY_MRC_CACHE; + } + + /* + * In normal mode: + * 1. If recovery mrc cache exists, protect it. + * 2. Use DEFAULT_MRC_CACHE. + */ + if (mrc_recovery_cache_exists() && + !mrc_cache_get_region(RECOVERY_MRC_CACHE, &region)) { + printk(BIOS_ERR, "MRC: Protecting recovery cache.\n"); + protect_mrc_cache(&region, RECOVERY_MRC_CACHE); + } + + return DEFAULT_MRC_CACHE; +} + int mrc_cache_get_current_with_version(const struct mrc_saved_data **cache, - uint32_t version) + uint32_t version) { struct mrc_data_region region; + const char *region_name = NULL; + + region_name = mrc_cache_get_region_name(); + if (!region_name) { + printk(BIOS_ERR, "MRC: Requires memory retraining\n"); + return -1; + } + + printk(BIOS_ERR, "MRC: Using data from %s\n", region_name); - if (mrc_cache_get_region(&region) < 0) + if (mrc_cache_get_region(region_name, &region) < 0) return -1; return __mrc_cache_get_current(&region, cache, version); @@ -197,14 +277,14 @@ int mrc_cache_stash_data_with_version(const void *data, size_t size, cache = cbmem_add(CBMEM_ID_MRCDATA, cbmem_size); if (cache == NULL) { - printk(BIOS_ERR, "No space in cbmem for MRC data.\n"); + printk(BIOS_ERR, "MRC: No space in cbmem for training data.\n"); return -1; } /* Clear alignment padding bytes at end of data. */ memset(&cache->data[size], 0, cbmem_size - size - sizeof(*cache)); - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%zu bytes)\n", + printk(BIOS_DEBUG, "MRC: Relocate data from %p to %p (%zu bytes)\n", data, cache, size); mrc_cache_fill(cache, data, size, version); @@ -263,25 +343,6 @@ mrc_cache_next_slot(const struct mrc_data_region *region, return next_slot; } -/* Protect RW_MRC_CACHE region with a Protected Range Register */ -static int protect_mrc_cache(const struct mrc_data_region *region) -{ -#if IS_ENABLED(CONFIG_MRC_SETTINGS_PROTECT) - if (nvm_is_write_protected() <= 0) { - printk(BIOS_INFO, "NOT enabling PRR for RW_MRC_CACHE region\n"); - return 1; - } - - if (nvm_protect(region->base, region->size) < 0) { - printk(BIOS_ERR, "ERROR setting PRR for RW_MRC_CACHE region\n"); - return -1; - } - - printk(BIOS_INFO, "Enabled Protected Range on RW_MRC_CACHE region\n"); -#endif - return 0; -} - static void log_event_cache_update(uint8_t slot, uint8_t status) { const int type = ELOG_TYPE_MEM_CACHE_UPDATE; @@ -300,23 +361,32 @@ static void update_mrc_cache(void *unused) const struct mrc_saved_data *current_saved; const struct mrc_saved_data *next_slot; struct mrc_data_region region; + const char *region_name = DEFAULT_MRC_CACHE; + uint8_t slot = ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL; - printk(BIOS_DEBUG, "Updating MRC cache data.\n"); + printk(BIOS_DEBUG, "MRC: Updating cache data.\n"); - current_boot = cbmem_find(CBMEM_ID_MRCDATA); - if (!current_boot) { - printk(BIOS_ERR, "No MRC cache in cbmem.\n"); - return; + if (vboot_recovery_mode_enabled() && mrc_recovery_cache_exists()) { + region_name = RECOVERY_MRC_CACHE; + slot = ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY; } - if (mrc_cache_get_region(&region)) { - printk(BIOS_ERR, "Could not obtain MRC cache region.\n"); + printk(BIOS_ERR, "MRC: Cache region selected - %s\n", region_name); + + if (mrc_cache_get_region(region_name, &region)) { + printk(BIOS_ERR, "MRC: Could not obtain cache region.\n"); return; } + current_boot = cbmem_find(CBMEM_ID_MRCDATA); + if (!current_boot) { + printk(BIOS_ERR, "MRC: No cache in cbmem.\n"); + goto out; + } + if (!mrc_cache_valid(&region, current_boot)) { - printk(BIOS_ERR, "MRC cache data in cbmem invalid.\n"); - return; + printk(BIOS_ERR, "MRC: Cache data in cbmem invalid.\n"); + goto out; } current_saved = NULL; @@ -326,20 +396,20 @@ static void update_mrc_cache(void *unused) if (current_saved->size == current_boot->size && !memcmp(&current_saved->data[0], &current_boot->data[0], current_saved->size)) { - printk(BIOS_DEBUG, "MRC cache up to date.\n"); - protect_mrc_cache(&region); - return; + printk(BIOS_DEBUG, "MRC: Cache up to date.\n"); + goto out; } } next_slot = mrc_cache_next_slot(&region, current_saved); if (!mrc_slot_valid(&region, next_slot, current_boot)) { - printk(BIOS_DEBUG, "Slot @ %p is invalid.\n", next_slot); + printk(BIOS_DEBUG, "MRC: Slot @ %p is invalid.\n", next_slot); if (!nvm_is_erased(region.base, region.size)) { if (nvm_erase(region.base, region.size) < 0) { - printk(BIOS_DEBUG, "Failure erasing region.\n"); - return; + printk(BIOS_DEBUG, "MRC: Failure erasing " + "region %s.\n", region_name); + goto out; } } next_slot = region.base; @@ -347,16 +417,16 @@ static void update_mrc_cache(void *unused) if (nvm_write((void *)next_slot, current_boot, current_boot->size + sizeof(*current_boot))) { - printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n", - next_slot); - log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, - ELOG_MEM_CACHE_UPDATE_STATUS_FAIL); + printk(BIOS_DEBUG, "MRC: Failure writing MRC cache to %s:%p\n", + region_name, next_slot); + log_event_cache_update(slot, ELOG_MEM_CACHE_UPDATE_STATUS_FAIL); } else { - log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, - ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS); + log_event_cache_update(slot, + ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS); } - protect_mrc_cache(&region); +out: + protect_mrc_cache(&region, region_name); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); diff --git a/src/soc/intel/common/mrc_cache.h b/src/soc/intel/common/mrc_cache.h index 9b14c1e..09ab306 100644 --- a/src/soc/intel/common/mrc_cache.h +++ b/src/soc/intel/common/mrc_cache.h @@ -19,6 +19,9 @@ #include <stddef.h> #include <stdint.h> +#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" +#define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" + /* Wrapper object to save MRC information. */ struct mrc_saved_data { uint32_t signature;

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Patch set updated for coreboot: mainboard/google/reef: Add support for RECOVERY_MRC_CACHE
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17243 -gerrit commit e1006eae7d54897e27764de42571578c15fc83e6 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Nov 6 00:07:08 2016 -0700 mainboard/google/reef: Add support for RECOVERY_MRC_CACHE 1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper functions for getting and clearing event for recovery mode with memory retraining. 3. Select HAS_RECOVERY_MRC_CACHE. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 1 + src/mainboard/google/reef/chromeos.c | 24 ++++++++++++++++++++++-- src/mainboard/google/reef/chromeos.fmd | 3 ++- 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 6045f47..bb7a531 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -33,6 +33,7 @@ config DRIVER_TPM_I2C_IRQ config CHROMEOS select LID_SWITCH if BASEBOARD_REEF_LAPTOP + select HAS_RECOVERY_MRC_CACHE config DRIVERS_I2C_DA7219 default y diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 58c2cd8..ddb0cc4 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -50,9 +50,23 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check if the EC has posted the keyboard recovery event. */ + /* + * Check if the EC has posted the keyboard recovery event with/without + * memory retrain. + */ return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))); +} + +int get_recovery_mode_retrain_switch(void) +{ + /* + * Check if the EC has posted the keyboard recovery event with memory + * retrain. + */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } int clear_recovery_mode_switch(void) @@ -62,6 +76,12 @@ int clear_recovery_mode_switch(void) EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } +int clear_recovery_mode_retrain_switch(void) +{ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); +} + int get_write_protect_state(void) { /* Read PCH_WP GPIO. */ diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index d25a9b2..c6a413d 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -13,7 +13,8 @@ FLASH 16M { } } MISC_RW@0x400000 0x4a000 { - RW_MRC_CACHE@0x0 0x40000 + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x30000 RW_ELOG@0x40000 0x4000 RW_SHARED@0x44000 0x4000 { SHARED_DATA@0x0 0x2000

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Patch set updated for coreboot: fmap: Add support for checking existence of region
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17238 -gerrit commit ad7ad5bdf672f4a3802fa6262c65af2808de81fc Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:37:11 2016 -0700 fmap: Add support for checking existence of region Implement fmap_region_exists which acts as a wrapper for checking if a region name exists in FMAP. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that fmap_exists returns existence of region names present in FMAP. Change-Id: I288ea8c7c57d3b0f237cdece42c4f5fe9c2c066a Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/include/fmap.h | 3 +++ src/lib/fmap.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/src/include/fmap.h b/src/include/fmap.h index 5834831..774fbfe 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -36,6 +36,9 @@ int fmap_locate_area_as_rdev_rw(const char *name, struct region_device *area); * < 0 on error. */ int fmap_locate_area(const char *name, struct region *r); +/* Check if region exists in fmap. Return 1 on success, 0 on error. */ +int fmap_region_exists(const char *name); + /* Find fmap area name by offset and size. * Return 0 on success, < 0 on error. */ int fmap_find_region_name(const struct region * const ar, diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 9602134..8cb7267 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -131,6 +131,12 @@ int fmap_locate_area(const char *name, struct region *ar) return -1; } +int fmap_region_exists(const char *name) +{ + struct region ar; + return !fmap_locate_area(name, &ar); +} + int fmap_find_region_name(const struct region * const ar, char name[FMAP_STRLEN]) {

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Patch set updated for coreboot: soc/intel/common: Enable SPI and NVM drivers in pre-ram stages
by Furquan Shaikh 06 Nov '16

06 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17239 -gerrit commit 12f349c1f9da9de2b4101cca4e77082b8622ac61 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Nov 5 23:46:10 2016 -0700 soc/intel/common: Enable SPI and NVM drivers in pre-ram stages BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that spi region can be protected in romstage using nvm functions. Change-Id: Iba32b0828b7f2078ee3dbaeb0c6abd2157307fb2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/common/Makefile.inc | 2 ++ src/soc/intel/common/nvm.c | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0..4abe524 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -10,7 +10,9 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 6b86faf..b0ca814 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <stdint.h> #include <stddef.h> #include <bootmode.h> @@ -28,10 +29,12 @@ * address space for reading. Also this module assumes an area it erased * when all bytes read as all 0xff's. */ -static struct spi_flash *flash; +static struct spi_flash *gflash CAR_GLOBAL; static int nvm_init(void) { + struct spi_flash *flash = car_get_var(gflash); + if (flash != NULL) return 0; @@ -41,6 +44,7 @@ static int nvm_init(void) printk(BIOS_DEBUG, "Could not find SPI device\n"); return -1; } + car_set_var(gflash, flash); return 0; } @@ -81,6 +85,9 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; + + struct spi_flash *flash = car_get_var(gflash); + return flash->erase(flash, nvm_mmio_to_flash_offset(start), size); } @@ -89,6 +96,9 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; + + struct spi_flash *flash = car_get_var(gflash); + return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data); } @@ -98,6 +108,8 @@ int nvm_is_write_protected(void) if (nvm_init() < 0) return -1; + struct spi_flash *flash = car_get_var(gflash); + if (IS_ENABLED(CONFIG_CHROMEOS)) { u8 sr1; u8 wp_gpio;

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New patch to review for coreboot: nb/intel/i945: Clean up native VGA graphic init
by Arthur Heymans 06 Nov '16

06 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17253 -gerrit commit 2b76ce07e483c48b1dd42e901b7dd8a9b34555e7 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Nov 6 18:34:34 2016 +0100 nb/intel/i945: Clean up native VGA graphic init This code was simply copied from the Pineview northbridge and many writes to registers are not necessary. TESTED on Thinkpad X60 with VGA display connected. Change-Id: I68cf6c71670ed1050416c57369b0bf1a18b9f65c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index bb0bb73..7e57d0f 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -417,11 +417,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, write32(pmmio + VGA0, 0x200074); write32(pmmio + VGA1, 0x200074); - write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); - write32(pmmio + DSPCLK_GATE_D, 0); - write32(pmmio + FW_BLC, 0x03060106); - write32(pmmio + FW_BLC2, 0x00000306); - write32(pmmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_USE_VGA_HVPOLARITY @@ -430,13 +425,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, | ADPA_DPMS_ON ); - write32(pmmio + 0x7041c, 0x0); - - write32(pmmio + DPLL_MD(0), 0x3); - write32(pmmio + DPLL_MD(1), 0x3); - write32(pmmio + DSPCNTR(1), 0x1000000); - write32(pmmio + PIPESRC(1), 0x027f01df); - vga_misc_write(0x67); const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, @@ -503,12 +491,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x00002040); - mdelay(1); - write32(pmmio + FDI_RX_CTL(0), 0x80002050); - write32(pmmio + FDI_TX_CTL(0), 0x00044000); - mdelay(1); - write32(pmmio + FDI_TX_CTL(0), 0x80044000); write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(pmmio + VGACNTRL, 0x0); @@ -525,8 +507,6 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, write32(pmmio + DSPFW3, 0x7f3f00c1); write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); - write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); - write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); /* Set up GTT. */

1 0

Patch merged into coreboot/master: soc/intel/common: log event when MRC cache is updated
by gerrit＠coreboot.org 06 Nov '16

06 Nov '16

the following patch was just integrated into master: commit 7d9068fe0b5d87fe3fe075d5d9a5f7493f5b1eac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 10:07:14 2016 -0500 soc/intel/common: log event when MRC cache is updated Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17231 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17231 for details. -gerrit

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coreboot-gerrit November 2016