coreboot-gerrit November 2016

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Patch set updated for coreboot: riscv: bring in the configstring parsing functions from UCB
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17255 -gerrit commit beef8164d3cc63e68ef6f5f0e13922c4c194dd4f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 20:51:18 2016 -0800 riscv: bring in the configstring parsing functions from UCB I've tested this with commits to come later. This is from the lowrisc bbl distribution, 87588c4, with fixes so it builds. Change-Id: I87893638872259c94d6972e1971578b633155e7e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/commonlib/configstring.c | 54 +++++++ src/commonlib/include/commonlib/configstring.h | 209 +++++++++++++++++++++++++ 2 files changed, 263 insertions(+) diff --git a/src/commonlib/configstring.c b/src/commonlib/configstring.c new file mode 100644 index 0000000..40beb16 --- /dev/null +++ b/src/commonlib/configstring.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2016, The Regents of the University of California + *(Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, + * ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <config.h> +#include <assert.h> +#include <string.h> +#include <commonlib/configstring.h> + +void query_mem(const char *config_string, uintptr_t *base, size_t *size) +{ + query_result res = query_config_string(config_string, "ram{0{addr"); + *base = get_uint(res); + res = query_config_string(config_string, "ram{0{size"); + *size = get_uint(res); +} + +/* query_rtc returns the physical address of the rtc. */ +void query_rtc(const char *config_string, uintptr_t *mtime) +{ + query_result res = query_config_string(config_string, "rtc{addr"); + *mtime = (uintptr_t)get_uint(res); +} + +const char *configstring(void) +{ + uint32_t addr = *(uint32_t *)CONFIG_ARCH_CONFIGSTRING_RISCV; + return (const char *)(uintptr_t)addr; +} diff --git a/src/commonlib/include/commonlib/configstring.h b/src/commonlib/include/commonlib/configstring.h new file mode 100644 index 0000000..8aacbda --- /dev/null +++ b/src/commonlib/include/commonlib/configstring.h @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2013-2016, The Regents of the University of California + *(Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, + * ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef RISCV_CONFIG_STRING_H +#define RISCV_CONFIG_STRING_H + +#include <stddef.h> +#include <stdint.h> + +static const char *skip_whitespace(const char *str) +{ + while (*str && *str <= ' ') + str++; + return str; +} + +static const char *skip_string(const char *str) +{ + while (*str && *str++ != '"') + ; + return str; +} + +static int is_hex(char ch) +{ + return (ch >= '0' && ch <= '9') || (ch >= 'a' && ch <= 'f') || + (ch >= 'A' && ch <= 'F'); +} + +static int parse_hex(char ch) +{ + return (ch >= '0' && ch <= '9') ? ch - '0' : (ch >= 'a' && ch <= 'f') + ? ch - 'a' + 10 + : ch - 'A' + 10; +} + +static const char *skip_key(const char *str) +{ + while (*str >= 35 && *str <= 122 && *str != ';') + str++; + return str; +} + +typedef struct { + const char *start; + const char *end; +} query_result; + +static inline query_result query_config_string(const char *str, const char *k) +{ + size_t ksize = 0; + while (k[ksize] && k[ksize] != '{') + ksize++; + int last = !k[ksize]; + + query_result res = {0, 0}; + while (1) { + const char *key_start = str = skip_whitespace(str); + const char *key_end = str = skip_key(str); + int match = (size_t)(key_end - key_start) == ksize; + if (match) + for (size_t i = 0; i < ksize; i++) + if (key_start[i] != k[i]) + match = 0; + const char *value_start = str = skip_whitespace(str); + while (*str != ';') { + if (!*str) { + return res; + } else if (*str == '"') { + str = skip_string(str + 1); + } else if (*str == '{') { + const char *search_key = + match && !last ? k + ksize + 1 : ""; + query_result inner_res = + query_config_string(str + 1, search_key); + if (inner_res.start) + return inner_res; + str = inner_res.end + 1; + } else { + str = skip_key(str); + } + str = skip_whitespace(str); + } + res.end = str; + if (match && last) { + res.start = value_start; + return res; + } + str = skip_whitespace(str + 1); + if (*str == '}') { + res.end = str; + return res; + } + } +} + +static void parse_string(query_result r, char *buf) +{ + if (r.start < r.end) { + if (*r.start == '"') { + for (const char *p = r.start + 1; + p < r.end && *p != '"'; p++) { + char ch = p[0]; + if (ch == '\\' && p[1] == 'x' && is_hex(p[2])) { + ch = parse_hex(p[2]); + if (is_hex(p[3])) { + ch = + (ch << 4) + parse_hex(p[3]); + p++; + } + p += 2; + } + *buf++ = ch; + } + } else { + for (const char *p = r.start; p < r.end && *p > ' '; + p++) + *buf++ = *p; + } + } + *buf = 0; +} + +static uint64_t __get_uint_hex(const char *s) +{ + uint64_t res = 0; + while (*s) { + if (is_hex(*s)) + res = (res << 4) + parse_hex(*s); + else if (*s != '_') + break; + s++; + } + return res; +} + +static uint64_t __get_uint_dec(const char *s) +{ + uint64_t res = 0; + while (*s) { + if (*s >= '0' && *s <= '9') + res = res * 10 + (*s - '0'); + else + break; + s++; + } + return res; +} + +static uint64_t __get_uint(const char *s) +{ + if (s[0] == '0' && s[1] == 'x') + return __get_uint_hex(s + 2); + return __get_uint_dec(s); +} + +// This is nasty. But the original code used a much nastier thing, +// an array declared as an automatic, which triggered gcc warnings +// as it was sized by the res.end - res.start. We'll need a better +// solution, long term. Malloc is probably not it. +static char name[1024]; +static inline uint64_t get_uint(query_result res) +{ + uint64_t v; + parse_string(res, name); + v = __get_uint(name); + return v; +} + +static inline int64_t get_sint(query_result res) +{ + int64_t v; + parse_string(res, name); + if (name[0] == '-') + return -__get_uint(name + 1); + v = __get_uint(name); + return v; +} + +const char *configstring(void); +void query_mem(const char *config_string, uintptr_t *base, size_t *size); +void query_rtc(const char *config_string, uintptr_t *mtime); +#endif

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New patch to review for coreboot: riscv: start to use the configstring functions
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17256 -gerrit commit c5135bda156304f312153af2ff21f7165f0fea4b Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 20:54:20 2016 -0800 riscv: start to use the configstring functions These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 9 ++++++--- src/arch/riscv/boot.c | 8 ++++---- src/mainboard/emulation/spike-riscv/romstage.c | 7 +++++++ 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index cf6ce99..f5b0958 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -42,7 +42,8 @@ bootblock-y += \ $(top)/src/lib/memcmp.c \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c + $(top)/src/lib/memset.c \ + $(top)/src/commonlib/configstring.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -68,7 +69,8 @@ romstage-y += \ $(top)/src/lib/memcmp.c \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c + $(top)/src/lib/memset.c \ + $(top)/src/commonlib/configstring.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -102,7 +104,8 @@ ramstage-y += \ $(top)/src/lib/memcmp.c \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c + $(top)/src/lib/memset.c \ + $(top)/src/commonlib/configstring.c $(eval $(call create_class_compiler,rmodules,riscv)) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 0fa4d5f..9483c48 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -18,19 +18,19 @@ #include <arch/encoding.h> #include <rules.h> #include <console/console.h> +#include <commonlib/configstring.h> void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); void riscvpayload(const char *configstring, void *payload); - uint32_t addr = *(uint32_t *)CONFIG_ARCH_CONFIGSTRING_RISCV; - const char *configstring = (const char *)(uintptr_t)addr; + const char *config = configstring(); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { - printk(BIOS_SPEW, "Config string: '%s'\n", configstring); + printk(BIOS_SPEW, "Config string: '%s'\n", config); initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(configstring, doit); + riscvpayload(config, doit); } doit(prog_entry_arg(prog)); diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c index b6314ccd..1317b00 100644 --- a/src/mainboard/emulation/spike-riscv/romstage.c +++ b/src/mainboard/emulation/spike-riscv/romstage.c @@ -15,9 +15,16 @@ #include <console/console.h> #include <program_loading.h> +#include <string.h> +#include <commonlib/configstring.h> void main(void) { + uintptr_t base; + size_t size; + console_init(); + query_mem(configstring(), &base, &size); + printk(BIOS_SPEW, "0x%lx bytes of memory at 0x%llx\n", size, base); run_ramstage(); }

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New patch to review for coreboot: riscv: bring in the configstring parsing functions from UCB
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17255 -gerrit commit f8c4a631f19221173cf74df1c958eb63a87542f9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 20:51:18 2016 -0800 riscv: bring in the configstring parsing functions from UCB I've tested this with commits to come later. This is from the lowrisc bbl distribution, 87588c4, with fixes so it builds. Change-Id: I87893638872259c94d6972e1971578b633155e7e Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/commonlib/configstring.c | 54 +++++++ src/commonlib/include/commonlib/configstring.h | 211 +++++++++++++++++++++++++ 2 files changed, 265 insertions(+) diff --git a/src/commonlib/configstring.c b/src/commonlib/configstring.c new file mode 100644 index 0000000..40beb16 --- /dev/null +++ b/src/commonlib/configstring.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2016, The Regents of the University of California + *(Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, + * ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <config.h> +#include <assert.h> +#include <string.h> +#include <commonlib/configstring.h> + +void query_mem(const char *config_string, uintptr_t *base, size_t *size) +{ + query_result res = query_config_string(config_string, "ram{0{addr"); + *base = get_uint(res); + res = query_config_string(config_string, "ram{0{size"); + *size = get_uint(res); +} + +/* query_rtc returns the physical address of the rtc. */ +void query_rtc(const char *config_string, uintptr_t *mtime) +{ + query_result res = query_config_string(config_string, "rtc{addr"); + *mtime = (uintptr_t)get_uint(res); +} + +const char *configstring(void) +{ + uint32_t addr = *(uint32_t *)CONFIG_ARCH_CONFIGSTRING_RISCV; + return (const char *)(uintptr_t)addr; +} diff --git a/src/commonlib/include/commonlib/configstring.h b/src/commonlib/include/commonlib/configstring.h new file mode 100644 index 0000000..0796260 --- /dev/null +++ b/src/commonlib/include/commonlib/configstring.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2013-2016, The Regents of the University of California + *(Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, + * ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef RISCV_CONFIG_STRING_H +#define RISCV_CONFIG_STRING_H + +#include <stddef.h> +#include <stdint.h> + +static const char *skip_whitespace(const char *str) +{ + while (*str && *str <= ' ') + str++; + return str; +} + +static const char *skip_string(const char *str) +{ + while (*str && *str++ != '"') + ; + return str; +} + +static int is_hex(char ch) +{ + return (ch >= '0' && ch <= '9') || (ch >= 'a' && ch <= 'f') || + (ch >= 'A' && ch <= 'F'); +} + +static int parse_hex(char ch) +{ + return (ch >= '0' && ch <= '9') ? ch - '0' : (ch >= 'a' && ch <= 'f') + ? ch - 'a' + 10 + : ch - 'A' + 10; +} + +static const char *skip_key(const char *str) +{ + while (*str >= 35 && *str <= 122 && *str != ';') + str++; + return str; +} + +typedef struct { + const char *start; + const char *end; +} query_result; + +static inline query_result query_config_string(const char *str, const char *k) +{ + size_t ksize = 0; + while (k[ksize] && k[ksize] != '{') + ksize++; + int last = !k[ksize]; + + query_result res = {0, 0}; + while (1) { + const char *key_start = str = skip_whitespace(str); + const char *key_end = str = skip_key(str); + int match = (size_t)(key_end - key_start) == ksize; + if (match) + for (size_t i = 0; i < ksize; i++) + if (key_start[i] != k[i]) + match = 0; + const char *value_start = str = skip_whitespace(str); + while (*str != ';') { + if (!*str) { + return res; + } else if (*str == '"') { + str = skip_string(str + 1); + } else if (*str == '{') { + const char *search_key = + match && !last ? k + ksize + 1 : ""; + query_result inner_res = + query_config_string(str + 1, search_key); + if (inner_res.start) + return inner_res; + str = inner_res.end + 1; + } else { + str = skip_key(str); + } + str = skip_whitespace(str); + } + res.end = str; + if (match && last) { + res.start = value_start; + return res; + } + str = skip_whitespace(str + 1); + if (*str == '}') { + res.end = str; + return res; + } + } +} + +static void parse_string(query_result r, char *buf) +{ + if (r.start < r.end) { + if (*r.start == '"') { + for (const char *p = r.start + 1; + p < r.end && *p != '"'; p++) { + char ch = p[0]; + if (ch == '\\' && p[1] == 'x' && is_hex(p[2])) { + ch = parse_hex(p[2]); + if (is_hex(p[3])) { + ch = + (ch << 4) + parse_hex(p[3]); + p++; + } + p += 2; + } + *buf++ = ch; + } + } else { + for (const char *p = r.start; p < r.end && *p > ' '; + p++) + *buf++ = *p; + } + } + *buf = 0; +} + +static uint64_t __get_uint_hex(const char *s) +{ + uint64_t res = 0; + while (*s) { + if (is_hex(*s)) + res = (res << 4) + parse_hex(*s); + else if (*s != '_') + break; + s++; + } + return res; +} + +static uint64_t __get_uint_dec(const char *s) +{ + uint64_t res = 0; + while (*s) { + if (*s >= '0' && *s <= '9') + res = res * 10 + (*s - '0'); + else + break; + s++; + } + return res; +} + +static uint64_t __get_uint(const char *s) +{ + if (s[0] == '0' && s[1] == 'x') + return __get_uint_hex(s + 2); + return __get_uint_dec(s); +} + +// This is nasty. But the original code used a much nastier thing, +// an array declared as an automatic, which triggered gcc warnings +// as it was sized by the res.end - res.start. We'll need a better +// solution, long term. Malloc is probably not it. +static char name[1024]; +static inline uint64_t get_uint(query_result res) +{ + uint64_t v; + parse_string(res, name); + v = __get_uint(name); + free(name); + return v; +} + +static inline int64_t get_sint(query_result res) +{ + int64_t v; + parse_string(res, name); + if (name[0] == '-') + return -__get_uint(name + 1); + v = __get_uint(name); + free(name); + return v; +} + +const char *configstring(void); +void query_mem(const char *config_string, uintptr_t *base, size_t *size); +void query_rtc(const char *config_string, uintptr_t *mtime); +#endif

1 0

Patch set updated for coreboot: intel/kblrvp: Update mainboard configuration
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17247 -gerrit commit 11c75ee1bfeb8c713060f2336f6ee4902e9f1a45 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 13:37:34 2016 +0530 intel/kblrvp: Update mainboard configuration Update devicetree.cb as per RVP3 mainboard. Disable pull down for power button in gpio.h. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/devicetree.cb | 192 ++++++++++--------------------- src/mainboard/intel/kblrvp/gpio.h | 4 +- 2 files changed, 64 insertions(+), 132 deletions(-) diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb index 8dded98..ad4d877 100644 --- a/src/mainboard/intel/kblrvp/devicetree.cb +++ b/src/mainboard/intel/kblrvp/devicetree.cb @@ -1,14 +1,14 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable" = "1" + register "deep_s5_enable" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -23,9 +23,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" @@ -63,23 +60,10 @@ chip soc/intel/skylake register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ + .psi2threshold = 0x14, \ .psi3threshold = 0x4, \ .psi3enable = 1, \ .psi4enable = 1, \ @@ -124,7 +108,7 @@ chip soc/intel/skylake .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .voltage_limit = 0x5F0, \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -142,29 +126,56 @@ chip soc/intel/skylake register "FspSkipMpInit" = "1" - # Enable Root port 1 and 5. + # Enable Root ports. + # PCIE Port 1 x4 -> SLOT1 register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpClkReqNumber[0]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card) - register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera - register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - - register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # PCIE Port 5 x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + + # PCIE Port 6 x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + # PCIE Port 9 x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + + # PCIE Port 10 x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "1" # Enable SSIC for WWAN # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ @@ -181,9 +192,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # PL2 override 25W - register "tdp_pl2_override" = "25" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" @@ -191,7 +199,7 @@ chip soc/intel/skylake register "VmxEnable" = "0" # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" + register "sdcard_cd_gpio_default" = "GPP_D10" device cpu_cluster 0 on device lapic 0 on end @@ -202,23 +210,8 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 @@ -229,61 +222,14 @@ chip soc/intel/skylake device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "1" - register "jkdet_pull_up" = "1" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - register "device_present_gpio" = "GPP_E3" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - register "device_present_gpio" = "GPP_E3" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 19.2 on end + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.0 on end # PCI Express Port 9 x1 WLAN + device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 @@ -291,24 +237,10 @@ chip soc/intel/skylake device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface + device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "device_present_gpio" = "GPP_E3" - register "device_present_gpio_invert" = "1" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h index f8ee994..5e251d8 100644 --- a/src/mainboard/intel/kblrvp/gpio.h +++ b/src/mainboard/intel/kblrvp/gpio.h @@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), @@ -204,4 +204,4 @@ static const struct pad_config early_gpio_table[] = { #endif -#endif \ No newline at end of file +#endif

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Patch set updated for coreboot: soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17245 -gerrit commit d645d4f432f70f4290ba31b9dbe1957180a9df4c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:42:30 2016 +0530 soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl Avoid use of Local0 variable in TEVT acpi method. If mainboard doesn't exposes any thermal sensor, then warning is generated for variable Local0 not been used. Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/acpi/dptf/thermal.asl | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 97484e5..d9bd9c0 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -17,25 +17,24 @@ /* Thermal Threshold Event Handler */ Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR0_SENSOR_ID)) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR1_SENSOR_ID)) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR2_SENSOR_ID)) { Notify (^TSR2, 0x90) } #endif #ifdef DPTF_TSR3_SENSOR_ID - If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR3_SENSOR_ID)) { Notify (^TSR3, 0x90) } #endif

1 0

Patch set updated for coreboot: soc/intel/skylake: Add device id for PCH-Y
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17244 -gerrit commit 5b0df703f040c77d0626248bd14a5026fe6389fc Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:36:31 2016 +0530 soc/intel/skylake: Add device id for PCH-Y Add device id for PCH-Y used in Kaby Lake RVP3 board. Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/bootblock/report_platform.c | 13 +++++++------ src/soc/intel/skylake/include/soc/pch.h | 1 + src/soc/intel/skylake/lpc.c | 1 + 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index f10159f..c3a0392 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -51,12 +51,13 @@ static struct { u16 lpcid; const char *name; } pch_table[] = { - { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, - { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, - { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, - { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, - { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, - { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, + { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, + { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, + { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, + { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, + { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, + { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, + { PCH_KBL_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium"}, }; static struct { diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 37fe1f9..701a6f5 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -26,6 +26,7 @@ #define PCH_SPT_LP_U_BASE 0x9d43 #define PCH_SPT_LP_U_PREMIUM 0x9d48 #define PCH_SPT_LP_Y_PREMIUM 0x9d46 +#define PCH_KBL_LP_Y_PREMIUM_HDCP22 0x9d4b #define PCH_KBL_LP_U_PREMIUM 0x9d58 #define PCH_KBL_LP_Y_PREMIUM 0x9d56 diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 3b5ccfe..1355c80 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -319,6 +319,7 @@ static const unsigned short pci_device_ids[] = { PCH_SPT_LP_Y_PREMIUM, PCH_KBL_LP_U_PREMIUM, PCH_KBL_LP_Y_PREMIUM, + PCH_KBL_LP_Y_PREMIUM_HDCP22, 0 };

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Patch set updated for coreboot: vboot: No vboot verification when Chrome EC disabled
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17246 -gerrit commit 7aa4bb3ea746754b51762c4eba789a43c861884f Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:51:14 2016 +0530 vboot: No vboot verification when Chrome EC disabled When Chrome EC is disabled, vboot hash is not available during S3 resume. Hence disable vboot verification when Chrome EC is not available. Change-Id: I665f5f0e2e53da7b735de30443d323572d8a1a9c Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/vboot/vboot_logic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/vboot/vboot_logic.c b/src/vboot/vboot_logic.c index bc6ab48..e565cb6 100644 --- a/src/vboot/vboot_logic.c +++ b/src/vboot/vboot_logic.c @@ -119,6 +119,12 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) int is_resume; /* + * If Chrome EC is not enabled then return + */ + if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return 0; + + /* * Nothing to do since resuming on the platform doesn't require * vboot verification again. */

1 0

Patch set updated for coreboot: riscv: change payload() to pass the config string pointer as arg0
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17254 -gerrit commit 032057b4a06bad2fc0e20b4fa0ae626733d36fee Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 16:13:52 2016 -0800 riscv: change payload() to pass the config string pointer as arg0 The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. A pointer to this string is available at a platform-dependent location, default 0x100c on all extant platforms. Define a new config variable, ARCH_CONFIGSTRING_RISCV, to contain this location and change payload() arguments so arg0 is this pointer and arg1 is the pointer to the payload. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Kconfig | 5 +++++ src/arch/riscv/boot.c | 7 +++++-- src/arch/riscv/payload.S | 4 +++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb70..7c43da4 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -19,3 +19,8 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + +config ARCH_CONFIGSTRING_RISCV + hex "Location of pointer to RISCV config string" + default 0x100c + depends on ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ff1844e..0fa4d5f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -22,12 +22,15 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); - void riscvpayload(void *); + void riscvpayload(const char *configstring, void *payload); + uint32_t addr = *(uint32_t *)CONFIG_ARCH_CONFIGSTRING_RISCV; + const char *configstring = (const char *)(uintptr_t)addr; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + printk(BIOS_SPEW, "Config string: '%s'\n", configstring); initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(doit); + riscvpayload(configstring, doit); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index 3261a80..e50a589 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -11,10 +11,12 @@ * GNU General Public License for more details. */ +// "return" to a payload pointed to by a1 with +// a pointer to the config string in a0. .global riscvpayload riscvpayload: /* Jump to a0 in S-mode */ - mv t0,a0 + mv t0,a1 csrw mepc, t0 csrr t0, mstatus li t1, ~(3<<11)

1 0

Patch set updated for coreboot: riscv: change payload() to pass the config string pointer as arg0
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17254 -gerrit commit a50f219fc5d3523c086d6f73100ead82fbe108e7 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 16:13:52 2016 -0800 riscv: change payload() to pass the config string pointer as arg0 The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. A pointer to this string is available at a platform-dependent location, default 0x100c on all extant platforms. Define a new config variable, ARCH_CONFIGSTRING_RISCV, to contain this location and change payload() arguments so arg0 is this pointer and arg1 is the pointer to the payload. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Kconfig | 5 +++++ src/arch/riscv/boot.c | 7 +++++-- src/arch/riscv/payload.S | 4 +++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb70..7c43da4 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -19,3 +19,8 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + +config ARCH_CONFIGSTRING_RISCV + hex "Location of pointer to RISCV config string" + default 0x100c + depends on ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ff1844e..8e1be97 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -22,12 +22,15 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); - void riscvpayload(void *); + void riscvpayload(void *configstring, void *payload); + uint32_t addr = *(uint32_t *)CONFIG_ARCH_CONFIGSTRING_RISCV; + const char *configstring = (const char *)(uintptr_t)addr; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + printk(BIOS_SPEW, "Config string: '%s'\n", configstring); initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(doit); + riscvpayload(configstring, doit); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index 3261a80..e50a589 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -11,10 +11,12 @@ * GNU General Public License for more details. */ +// "return" to a payload pointed to by a1 with +// a pointer to the config string in a0. .global riscvpayload riscvpayload: /* Jump to a0 in S-mode */ - mv t0,a0 + mv t0,a1 csrw mepc, t0 csrr t0, mstatus li t1, ~(3<<11)

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Patch set updated for coreboot: riscv: change payload() to pass the config string pointer as arg0
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17254 -gerrit commit 6b19021b75bc3cd48587c8805e9e5f6ed0c35299 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 16:13:52 2016 -0800 riscv: change payload() to pass the config string pointer as arg0 The riscv 1.9 standard defines a textual config string to be passed to kernels and hypervisors. A pointer to this string is available at a platform-dependent location, default 0x100c on all extant platforms. Define a new config variable, ARCH_CONFIGSTRING_RISCV, to contain this location and change payload() arguments so arg0 is this pointer and arg1 is the pointer to the payload. Change-Id: I3be7f1712accf2d726704e4c970f22749d3c3f36 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Kconfig | 5 +++++ src/arch/riscv/boot.c | 6 ++++-- src/arch/riscv/payload.S | 4 +++- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb70..7c43da4 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -19,3 +19,8 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + +config ARCH_CONFIGSTRING_RISCV + hex "Location of pointer to RISCV config string" + default 0x100c + depends on ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index ff1844e..f9cc54f 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -22,12 +22,14 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); - void riscvpayload(void *); + void riscvpayload(void *configstring, void *payload); + char *configstring = *(char **)CONFIG_ARCH_CONFIGSTRING_RISCV; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + printk(BIOS_SPEW, "Config string: '%s'\n", configstring); initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(doit); + riscvpayload(configstring, doit); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index 3261a80..e50a589 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -11,10 +11,12 @@ * GNU General Public License for more details. */ +// "return" to a payload pointed to by a1 with +// a pointer to the config string in a0. .global riscvpayload riscvpayload: /* Jump to a0 in S-mode */ - mv t0,a0 + mv t0,a1 csrw mepc, t0 csrr t0, mstatus li t1, ~(3<<11)

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coreboot-gerrit November 2016