coreboot-gerrit November 2016

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Patch merged into coreboot/master: mb/lowrisc/nexys4ddr: Actually fix the UART clock setup
by gerrit＠coreboot.org 07 Nov '16

07 Nov '16

the following patch was just integrated into master: commit 7ca9b8ae5014a745855296903682ae803235cb35 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sat Oct 29 21:48:18 2016 +0200 mb/lowrisc/nexys4ddr: Actually fix the UART clock setup Ron's code calculated the DLL and DLM registers of the 8250 UART, but that's the job of the UART driver. uart_input_clock_divider isn't needed anymore because the default value of 16 works. As a bonus, the baud rate can now be selected in Kconfig, instead of being hardcoded at 115200. TEST=Booted the board at 9600 and 115200 baud. Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/17188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/17188 for details. -gerrit

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Patch set updated for coreboot: i2c/wacom_ts: Update WACOM touchscreen ACPI HID
by Kevin Chiu 07 Nov '16

07 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17257 -gerrit commit 77b66d5ff0ad789f36786afc58ce79dbae5a3625 Author: Janice Li <janice.li(a)quantatw.com> Date: Mon Nov 7 17:49:44 2016 +0800 i2c/wacom_ts: Update WACOM touchscreen ACPI HID Modify WACOM ACPI HID WCOMNTN2 for Pyro to support touch screen FW update BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li(a)quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 --- src/drivers/i2c/wacom_ts/chip.h | 1 + src/drivers/i2c/wacom_ts/ts.c | 1 + src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h index b59f630..268d212 100644 --- a/src/drivers/i2c/wacom_ts/chip.h +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -23,6 +23,7 @@ #define WCOM_TS_DESC "WCOM Touchscreen" struct drivers_i2c_wacom_ts_config { + const char *hid; /* ACPI _HID (required) */ struct drivers_i2c_generic_config generic; uint8_t hid_desc_reg_offset; }; diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c index ebc8883..96d4853 100644 --- a/src/drivers/i2c/wacom_ts/ts.c +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -21,6 +21,7 @@ static void i2c_wacom_ts_fill_dsm(struct device *dev) { struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + config->generic.hid = config->hid; struct dsm_i2c_hid_config dsm_config = { .hid_desc_reg_offset = config->hid_desc_reg_offset, }; diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index a0ba584..50107ce 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -132,8 +132,8 @@ chip soc/intel/apollolake end # - I2C 2 device pci 16.3 on chip drivers/i2c/wacom_ts + register "hid" = ""WCOMNTN2""; register "generic" = "{ - .hid = WCOM50C1_HID, .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_EDGE_LOW(GPIO_21_IRQ),

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Patch set updated for coreboot: Pyro: WACOM touchscreen ACPI HID update
by Kevin Chiu 07 Nov '16

07 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17257 -gerrit commit d868df369c6ff8436b648148f6f2e469ca1ffa20 Author: Janice Li <janice.li(a)quantatw.com> Date: Mon Nov 7 17:49:44 2016 +0800 Pyro: WACOM touchscreen ACPI HID update update WACOM ACPI HID WCOMNTN2 BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by:Janice Li <janice.li(a)quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 --- src/drivers/i2c/wacom_ts/chip.h | 1 + src/drivers/i2c/wacom_ts/ts.c | 1 + src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h index b59f630..268d212 100644 --- a/src/drivers/i2c/wacom_ts/chip.h +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -23,6 +23,7 @@ #define WCOM_TS_DESC "WCOM Touchscreen" struct drivers_i2c_wacom_ts_config { + const char *hid; /* ACPI _HID (required) */ struct drivers_i2c_generic_config generic; uint8_t hid_desc_reg_offset; }; diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c index ebc8883..96d4853 100644 --- a/src/drivers/i2c/wacom_ts/ts.c +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -21,6 +21,7 @@ static void i2c_wacom_ts_fill_dsm(struct device *dev) { struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + config->generic.hid = config->hid; struct dsm_i2c_hid_config dsm_config = { .hid_desc_reg_offset = config->hid_desc_reg_offset, }; diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index a0ba584..50107ce 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -132,8 +132,8 @@ chip soc/intel/apollolake end # - I2C 2 device pci 16.3 on chip drivers/i2c/wacom_ts + register "hid" = ""WCOMNTN2""; register "generic" = "{ - .hid = WCOM50C1_HID, .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_EDGE_LOW(GPIO_21_IRQ),

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Patch set updated for coreboot: mainboard/intel/kblrvp: Remove unused code in dptf.asl
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17249 -gerrit commit 0be0db90b1f87f7f26e2071b170242444c67d00e Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:07:53 2016 +0530 mainboard/intel/kblrvp: Remove unused code in dptf.asl Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/acpi/dptf.asl | 74 -------------------------------- 1 file changed, 74 deletions(-) diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl index e011c97..c33bb06 100644 --- a/src/mainboard/intel/kblrvp/acpi/dptf.asl +++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl @@ -22,86 +22,12 @@ #define DPTF_CPU_ACTIVE_AC3 60 #define DPTF_CPU_ACTIVE_AC4 50 -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -#ifdef DPTF_ENABLE_FAN_CONTROL -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, - Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, - Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, - Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, - Package () {60, 0xFFFFFFFF, 3838, 90, 900}, - Package () {50, 0xFFFFFFFF, 3402, 65, 650}, - Package () {40, 0xFFFFFFFF, 2904, 45, 450}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, - 0, 0, 0 - } -}) -#endif Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package ()

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Patch set updated for coreboot: intel/kblrvp: Update mainboard configuration
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17247 -gerrit commit 2a327a6625d6b5989e245de44a5e6cb7b2ad70d7 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 13:37:34 2016 +0530 intel/kblrvp: Update mainboard configuration Update devicetree.cb as per RVP3 mainboard. Disable pull down for power button in gpio.h. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/devicetree.cb | 193 ++++++++++--------------------- src/mainboard/intel/kblrvp/gpio.h | 4 +- 2 files changed, 63 insertions(+), 134 deletions(-) diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb index 8dded98..5683a1a 100644 --- a/src/mainboard/intel/kblrvp/devicetree.cb +++ b/src/mainboard/intel/kblrvp/devicetree.cb @@ -1,14 +1,14 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable" = "1" + register "deep_s5_enable" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -23,9 +23,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" @@ -63,23 +60,10 @@ chip soc/intel/skylake register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ + .psi2threshold = 0x14, \ .psi3threshold = 0x4, \ .psi3enable = 1, \ .psi4enable = 1, \ @@ -124,7 +108,7 @@ chip soc/intel/skylake .imon_slope = 0x0, \ .imon_offset = 0x0, \ .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ + .voltage_limit = 0x5F0, \ }" register "domain_vr_config[VR_GT_SLICED]" = "{ @@ -142,29 +126,56 @@ chip soc/intel/skylake register "FspSkipMpInit" = "1" - # Enable Root port 1 and 5. + # Enable Root ports. + # PCIE Port 1 x4 -> SLOT1 register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 - register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card) - register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera - register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board) + register "PcieRpClkReqNumber[0]" = "2" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - - register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # PCIE Port 5 x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + + # PCIE Port 6 x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + # PCIE Port 9 x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + + # PCIE Port 10 x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "1" # Enable SSIC for WWAN # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ @@ -181,18 +192,12 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # PL2 override 25W - register "tdp_pl2_override" = "25" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" # Enable/Disable VMX feature register "VmxEnable" = "0" - # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" - device cpu_cluster 0 on device lapic 0 on end end @@ -202,23 +207,8 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)" - device i2c 10 on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "wake" = "GPE0_DW0_05" - device i2c 15 on end - end - end # I2C #1 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 @@ -229,61 +219,14 @@ chip soc/intel/skylake device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on - chip drivers/i2c/nau8825 - register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" - register "jkdet_enable" = "1" - register "jkdet_pull_enable" = "1" - register "jkdet_pull_up" = "1" - register "jkdet_polarity" = "1" # ActiveLow - register "vref_impedance" = "2" # 125kOhm - register "micbias_voltage" = "6" # 2.754 - register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x08" - register "sar_threshold[1]" = "0x12" - register "sar_threshold[2]" = "0x26" - register "sar_threshold[3]" = "0x73" - register "sar_hysteresis" = "0" - register "sar_voltage" = "6" - register "sar_compare_time" = "1" # 1us - register "sar_sampling_time" = "1" # 4us - register "short_key_debounce" = "3" # 30ms - register "jack_insert_debounce" = "7" # 512ms - register "jack_eject_debounce" = "0" - device i2c 1a on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Left Speaker Amp"" - register "uid" = "0" - register "device_present_gpio" = "GPP_E3" - device i2c 34 on end - end - chip drivers/i2c/generic - register "hid" = ""INT343B"" - register "desc" = ""SSM4567 Right Speaker Amp"" - register "uid" = "1" - register "device_present_gpio" = "GPP_E3" - device i2c 35 on end - end - end # I2C #4 - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 + device pci 19.2 on end + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.0 on end # PCI Express Port 9 x1 WLAN + device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 @@ -291,24 +234,10 @@ chip soc/intel/skylake device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface + device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" - register "device_present_gpio" = "GPP_E3" - register "device_present_gpio_invert" = "1" - device generic 0 on end - end - end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h index f8ee994..5e251d8 100644 --- a/src/mainboard/intel/kblrvp/gpio.h +++ b/src/mainboard/intel/kblrvp/gpio.h @@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = { /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), @@ -204,4 +204,4 @@ static const struct pad_config early_gpio_table[] = { #endif -#endif \ No newline at end of file +#endif

1 0

Patch set updated for coreboot: mainboard/roda: Use C89 comments style & remove commented code
by HAOUAS Elyes 07 Nov '16

07 Nov '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16929 -gerrit commit 284826b3de3da2ee1dc3d3da57d8041f32fecb63 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Oct 7 18:22:44 2016 +0200 mainboard/roda: Use C89 comments style & remove commented code Change-Id: I4ce2705a8a07d0388bbdb459b63b59fc10a3aa39 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/roda/rk886ex/irq_tables.c | 20 +-- src/mainboard/roda/rk886ex/m3885.c | 219 ++++++++++++++------------------ src/mainboard/roda/rk886ex/mainboard.c | 14 -- src/mainboard/roda/rk886ex/mptable.c | 6 +- src/mainboard/roda/rk886ex/romstage.c | 106 ++++++++-------- src/mainboard/roda/rk9/hda_verb.c | 6 +- src/mainboard/roda/rk9/romstage.c | 2 +- 7 files changed, 165 insertions(+), 208 deletions(-) diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c index f6d02f8..29331fc 100644 --- a/src/mainboard/roda/rk886ex/irq_tables.c +++ b/src/mainboard/roda/rk886ex/irq_tables.c @@ -30,22 +30,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf, /* u8 checksum. */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? - {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA - {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge - {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC - {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1 - {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device - {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge - {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire - {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge + {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */ + {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */ + {0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */ + {0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */ + {0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */ + {0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */ + {0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */ + {0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */ + {0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */ {0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0}, {0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0}, {0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0}, {0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0}, {0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0}, {0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0}, - {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 + {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */ {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, } diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index d5a2b70..60a4f48 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -31,79 +31,79 @@ static u8 variables[] = { /* Offs, AND, OR */ - 0x08, 0x48, 0x6C, // Keyboard ScanCode Set & LED Data (kState1) - 0x0a, 0x01, 0x00, // Keyboard Shift flags (kState3) - 0x0c, 0x80, 0x08, // Keyboard State flags (kState5) - 0x11, 0xff, 0x06, // Make/Break Debounce #'s (debounce) - 0x13, 0xff, 0x00, // HotKey1 ScanCode (hotKey1) - 0x14, 0xff, 0x00, // HotKey2 ScanCode (hotKey2) - 0x15, 0xff, 0x3f, // HotKey3 ScanCode (hotKey3) - 0x16, 0xff, 0x00, // HotKey4 ScanCode (hotKey4) - 0x17, 0xff, 0x00, // HotKey5 ScanCode (hotKey5) - 0x18, 0xff, 0x0e, // HotKey6 ScanCode (hotKey6) - 0x19, 0xff, 0x9f, // HotKey1 Task = c5 Command Data (keyTsk1) - 0x1a, 0xff, 0x9f, // HotKey2 Task = c5 Command Data (keyTsk2) - 0x1b, 0xff, 0x6a, // HotKey3 Task = c5 Command Data (keyTsk3) - 0x1c, 0xff, 0x9f, // HotKey4 Task = c5 Command Data (keyTsk4) - 0x1d, 0xff, 0x9f, // HotKey5 Task = c5 Command Data (keyTsk5) - 0x1e, 0xff, 0x87, // FuncKey Task = c5 Command Data (funcTsk) - 0x1f, 0xff, 0x9f, // Delayed Task = c5 Command Data (dlyTsk1) - 0x20, 0xff, 0x9f, // Wake-Up Task = c5 Command Data (wakeTsk) - // - 0x21, 0xff, 0x08, // WigglePin Pulse Width * 2.4ms (tmPulse) - 0x24, 0xff, 0x30, // Keyboard State Flags (kState7) - // - 0x2b, 0xff, 0x00, // - 0x2c, 0xff, 0x80, // Set Fn-Key 8 - 0x2d, 0xff, 0x02, // Set Fn-Key 9 - 0x2e, 0xff, 0x00, // Set Fn-Key 1-8 task (0 = SMI) - 0x2f, 0xff, 0x00, // Set Fn-Key 9-12 task (1 = SCI) + 0x08, 0x48, 0x6C, /* Keyboard ScanCode Set & LED Data (kState1) */ + 0x0a, 0x01, 0x00, /* Keyboard Shift flags (kState3) */ + 0x0c, 0x80, 0x08, /* Keyboard State flags (kState5) */ + 0x11, 0xff, 0x06, /* Make/Break Debounce #'s (debounce) */ + 0x13, 0xff, 0x00, /* HotKey1 ScanCode (hotKey1) */ + 0x14, 0xff, 0x00, /* HotKey2 ScanCode (hotKey2) */ + 0x15, 0xff, 0x3f, /* HotKey3 ScanCode (hotKey3) */ + 0x16, 0xff, 0x00, /* HotKey4 ScanCode (hotKey4) */ + 0x17, 0xff, 0x00, /* HotKey5 ScanCode (hotKey5) */ + 0x18, 0xff, 0x0e, /* HotKey6 ScanCode (hotKey6) */ + 0x19, 0xff, 0x9f, /* HotKey1 Task = c5 Command Data (keyTsk1) */ + 0x1a, 0xff, 0x9f, /* HotKey2 Task = c5 Command Data (keyTsk2) */ + 0x1b, 0xff, 0x6a, /* HotKey3 Task = c5 Command Data (keyTsk3) */ + 0x1c, 0xff, 0x9f, /* HotKey4 Task = c5 Command Data (keyTsk4) */ + 0x1d, 0xff, 0x9f, /* HotKey5 Task = c5 Command Data (keyTsk5) */ + 0x1e, 0xff, 0x87, /* FuncKey Task = c5 Command Data (funcTsk) */ + 0x1f, 0xff, 0x9f, /* Delayed Task = c5 Command Data (dlyTsk1) */ + 0x20, 0xff, 0x9f, /* Wake-Up Task = c5 Command Data (wakeTsk) */ + + 0x21, 0xff, 0x08, /* WigglePin Pulse Width * 2.4ms (tmPulse) */ + 0x24, 0xff, 0x30, /* Keyboard State Flags (kState7) */ + + 0x2b, 0xff, 0x00, + 0x2c, 0xff, 0x80, /* Set Fn-Key 8 */ + 0x2d, 0xff, 0x02, /* Set Fn-Key 9 */ + 0x2e, 0xff, 0x00, /* Set Fn-Key 1-8 task (0 = SMI) */ + 0x2f, 0xff, 0x00, /* Set Fn-Key 9-12 task (1 = SCI) */ }; static u8 matrix[] = { - 0xc1,0xc0,0xd8,0xdb,0xbf,0x05,0x76,0xbf, // (0x00-0x07) - 0xbf,0x80,0x78,0xbf,0xbf,0x07,0x88,0xc2, // (0x08-0x0f) - 0x03,0x09,0xd9,0x16,0xbf,0x06,0x0e,0x81, // (0x10-0x17) - 0xbf,0xbf,0xee,0xbf,0xbf,0x55,0x9a,0x89, // (0x18-0x1f) - 0x1e,0x15,0x36,0xda,0xe8,0xbf,0x0d,0xbf, // (0x20-0x27) - 0xbf,0xbf,0xbf,0xa3,0xbf,0x4e,0x66,0x8b, // (0x28-0x2f) - 0x1d,0x2e,0xe6,0xe7,0xe5,0x1c,0x58,0xbf, // (0x30-0x37) - 0x82,0xbf,0xf0,0xbf,0xbf,0x5b,0x5d,0x8c, // (0x38-0x3f) - 0x22,0x25,0x2c,0x35,0xe1,0x1a,0x96,0xbf, // (0x40-0x47) - 0xbf,0xbf,0xec,0xbf,0xbf,0x54,0xf1,0x8f, // (0x48-0x4f) - 0x1b,0x2a,0x2b,0x32,0xe9,0x31,0x29,0x61, // (0x50-0x57) - 0xbf,0xbf,0x8d,0xbf,0x86,0xc3,0x92,0x93, // (0x58-0x5f) - 0x21,0x23,0x34,0x33,0x41,0xe0,0xbf,0xbf, // (0x60-0x67) - 0xbf,0x85,0xeb,0xbf,0xb6,0xbf,0x91,0xbf, // (0x68-0x6f) - 0x26,0x24,0x2d,0xe3,0xe2,0xe4,0xbf,0xbf, // (0x70-0x77) - 0x87,0xbf,0xea,0xbf,0xbf,0x52,0x90,0x8e, // (0x78-0x7f) + 0xc1,0xc0,0xd8,0xdb,0xbf,0x05,0x76,0xbf, /* (0x00-0x07) */ + 0xbf,0x80,0x78,0xbf,0xbf,0x07,0x88,0xc2, /* (0x08-0x0f) */ + 0x03,0x09,0xd9,0x16,0xbf,0x06,0x0e,0x81, /* (0x10-0x17) */ + 0xbf,0xbf,0xee,0xbf,0xbf,0x55,0x9a,0x89, /* (0x18-0x1f) */ + 0x1e,0x15,0x36,0xda,0xe8,0xbf,0x0d,0xbf, /* (0x20-0x27) */ + 0xbf,0xbf,0xbf,0xa3,0xbf,0x4e,0x66,0x8b, /* (0x28-0x2f) */ + 0x1d,0x2e,0xe6,0xe7,0xe5,0x1c,0x58,0xbf, /* (0x30-0x37) */ + 0x82,0xbf,0xf0,0xbf,0xbf,0x5b,0x5d,0x8c, /* (0x38-0x3f) */ + 0x22,0x25,0x2c,0x35,0xe1,0x1a,0x96,0xbf, /* (0x40-0x47) */ + 0xbf,0xbf,0xec,0xbf,0xbf,0x54,0xf1,0x8f, /* (0x48-0x4f) */ + 0x1b,0x2a,0x2b,0x32,0xe9,0x31,0x29,0x61, /* (0x50-0x57) */ + 0xbf,0xbf,0x8d,0xbf,0x86,0xc3,0x92,0x93, /* (0x58-0x5f) */ + 0x21,0x23,0x34,0x33,0x41,0xe0,0xbf,0xbf, /* (0x60-0x67) */ + 0xbf,0x85,0xeb,0xbf,0xb6,0xbf,0x91,0xbf, /* (0x68-0x6f) */ + 0x26,0x24,0x2d,0xe3,0xe2,0xe4,0xbf,0xbf, /* (0x70-0x77) */ + 0x87,0xbf,0xea,0xbf,0xbf,0x52,0x90,0x8e, /* (0x78-0x7f) */ }; static u8 function_ram[] = { - 0x04,0xbd,0x0c,0xbe,0x7e,0x9a,0x8a,0xb6, // (0xc0-0xc3) - 0x92,0x8f,0x93,0x8e,0x81,0x86,0x82,0x87, // (0xc4-0xc7) - 0x8a,0x9a,0x8d,0x7e,0x88,0x84,0x7e,0x78, // (0xc8-0xcb) - 0x77,0x07,0x77,0x98,0x89,0xb2,0x05,0x9b, // (0xcc-0xcf) - 0x78,0x84,0x07,0x88,0x8a,0x7e,0x05,0xa6, // (0xd0-0xd3) - 0x06,0xa7,0x04,0xa8,0x0c,0xa9,0x03,0xaa, // (0xd4-0xd7) - 0x0b,0xc1,0x83,0xc0,0x0a,0xad,0x01,0xae, // (0xd8-0xdb) - 0x09,0xaf,0x78,0xb0,0x07,0xb1,0x1a,0x61, // (0xdc-0xdf) - 0x3b,0x69,0x42,0x72,0x4b,0x7a,0x3c,0x6b, // (0xe0-0xe3) - 0x43,0x73,0x44,0x74,0x3d,0x6c,0x3e,0x75, // (0xe4-0xe7) - 0x46,0x7d,0x3a,0x70,0x49,0x71,0x4a,0x94, // (0xe8-0xeb) - 0x4c,0x79,0x4c,0x7c,0x45,0x7c,0x45,0x79, // (0xec-0xef) - 0x4d,0x7b,0x5a,0x95,0x4c,0x7b,0x45,0x7b, // (0xf0-0xf3) - 0x4d,0x79,0x4d,0x7c,0x4e,0x7b,0x54,0x95, // (0xf4-0xf7) - 0x52,0x7c,0x45,0x94,0x4a,0x79,0xb3,0x95, // (0xf8-0xfb) - 0xb4,0x7b,0xb5,0x7c,0x00,0x00,0x55,0x79, // (0xfc-0xff) + 0x04,0xbd,0x0c,0xbe,0x7e,0x9a,0x8a,0xb6, /* (0xc0-0xc3) */ + 0x92,0x8f,0x93,0x8e,0x81,0x86,0x82,0x87, /* (0xc4-0xc7) */ + 0x8a,0x9a,0x8d,0x7e,0x88,0x84,0x7e,0x78, /* (0xc8-0xcb) */ + 0x77,0x07,0x77,0x98,0x89,0xb2,0x05,0x9b, /* (0xcc-0xcf) */ + 0x78,0x84,0x07,0x88,0x8a,0x7e,0x05,0xa6, /* (0xd0-0xd3) */ + 0x06,0xa7,0x04,0xa8,0x0c,0xa9,0x03,0xaa, /* (0xd4-0xd7) */ + 0x0b,0xc1,0x83,0xc0,0x0a,0xad,0x01,0xae, /* (0xd8-0xdb) */ + 0x09,0xaf,0x78,0xb0,0x07,0xb1,0x1a,0x61, /* (0xdc-0xdf) */ + 0x3b,0x69,0x42,0x72,0x4b,0x7a,0x3c,0x6b, /* (0xe0-0xe3) */ + 0x43,0x73,0x44,0x74,0x3d,0x6c,0x3e,0x75, /* (0xe4-0xe7) */ + 0x46,0x7d,0x3a,0x70,0x49,0x71,0x4a,0x94, /* (0xe8-0xeb) */ + 0x4c,0x79,0x4c,0x7c,0x45,0x7c,0x45,0x79, /* (0xec-0xef) */ + 0x4d,0x7b,0x5a,0x95,0x4c,0x7b,0x45,0x7b, /* (0xf0-0xf3) */ + 0x4d,0x79,0x4d,0x7c,0x4e,0x7b,0x54,0x95, /* (0xf4-0xf7) */ + 0x52,0x7c,0x45,0x94,0x4a,0x79,0xb3,0x95, /* (0xf8-0xfb) */ + 0xb4,0x7b,0xb5,0x7c,0x00,0x00,0x55,0x79, /* (0xfc-0xff) */ }; #define KBD_DATA 0x60 #define KBD_SC 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) /* 1: input buffer full (data ready for ec) */ +#define KBD_OBF (1 << 0) /* 1: output buffer full (data ready for host) */ static int send_kbd_command(u8 command) { @@ -118,7 +118,6 @@ static int send_kbd_command(u8 command) if (!timeout) { printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n", command); - // return -1; } outb(command, KBD_SC); @@ -130,7 +129,7 @@ static int send_kbd_data(u8 data) int timeout; timeout = 0x7ff; - while ((inb(KBD_SC) & KBD_IBF) && --timeout) { // wait for IBF = 0 + while ((inb(KBD_SC) & KBD_IBF) && --timeout) { /* wait for IBF = 0 */ udelay(10); if ((timeout & 0xff) == 0) printk(BIOS_SPEW, "."); @@ -138,7 +137,6 @@ static int send_kbd_data(u8 data) if (!timeout) { printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n", data); - // return -1; } outb(data, KBD_DATA); @@ -153,7 +151,7 @@ static u8 recv_kbd_data(void) u8 data; timeout = 0x7fff; - while (--timeout) { // Wait for OBF = 1 + while (--timeout) { /* Wait for OBF = 1 */ if (inb(KBD_SC) & KBD_OBF) { break; } @@ -163,7 +161,6 @@ static u8 recv_kbd_data(void) } if (!timeout) { printk(BIOS_DEBUG, "\nTimeout while receiving data from EC!\n"); - // return -1; } data = inb(KBD_DATA); @@ -210,7 +207,6 @@ static u8 m3885_get_proc_ram(u8 index) send_kbd_command(0xb8); send_kbd_data(index); send_kbd_command(0xba); - // send_kbd_command(0xff); ret = recv_kbd_data(); printk(BIOS_SPEW, "m3885: get procram %02x = %02x\n", index, ret); return ret; @@ -222,7 +218,7 @@ static u8 m3885_read_port(void) reg8 = m3885_get_variable(0x0c); reg8 &= ~(7 << 4); - reg8 |= (4 << 4); // bank 4 + reg8 |= (4 << 4); /* bank 4 */ m3885_set_variable(0x0c, reg8); /* P6YSTATE */ @@ -265,7 +261,7 @@ void m3885_configure_multikey(void) printk(BIOS_DEBUG, "Could not load Function-RAM (%d).\n", maxvars); } - // restore original bank + /* restore original bank */ m3885_set_variable(0x0c, kstate5_flags); maxvars = m3885_get_variable(0x00); printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars); @@ -274,7 +270,7 @@ void m3885_configure_multikey(void) continue; reg8 = m3885_get_variable(variables[i + 0]); reg8 &= ~(variables[i + 1]); - reg8 |= variables[i + 2]; // & ~variables[i + 1]; + reg8 |= variables[i + 2]; m3885_set_variable(variables[i + 0], reg8); } @@ -303,108 +299,87 @@ void m3885_configure_multikey(void) m3885_set_proc_ram(0xf9, 0x0a); /* ReadPort */ - // m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (4 << 4)); /* AC PRESN# */ if (m3885_read_port() & (1 << 0)) reg8 = 0x8a; else reg8 = 0x9a; - m3885_set_proc_ram(0xd0, reg8); // P60SPEC + m3885_set_proc_ram(0xd0, reg8); /* P60SPEC */ /* SENSE1# */ if (m3885_read_port() & (1 << 2)) reg8 = 0x8a; else reg8 = 0x9a; - m3885_set_proc_ram(0xd2, reg8); // P62SPEC + m3885_set_proc_ram(0xd2, reg8); /* P62SPEC */ /* SENSE2# */ if (m3885_read_port() & (1 << 3)) reg8 = 0x8a; else reg8 = 0x9a; - m3885_set_proc_ram(0xd3, reg8); // P63SPEC + m3885_set_proc_ram(0xd3, reg8); /* P63SPEC */ /* Low Active Port */ - m3885_set_proc_ram(0xd1, 0x88); // P61SPEC - m3885_set_proc_ram(0xd6, 0x88); // P66SPEC - m3885_set_proc_ram(0xd7, 0x88); // P67SPEC + m3885_set_proc_ram(0xd1, 0x88); /* P61SPEC */ + m3885_set_proc_ram(0xd6, 0x88); /* P66SPEC */ + m3885_set_proc_ram(0xd7, 0x88); /* P67SPEC */ /* High Active Port */ - m3885_set_proc_ram(0xd4, 0x98); // P64SPEC - m3885_set_proc_ram(0xd5, 0x98); // P65SPEC + m3885_set_proc_ram(0xd4, 0x98); /* P64SPEC */ + m3885_set_proc_ram(0xd5, 0x98); /* P65SPEC */ /* Set P60TASK-P67TASK */ /* SCI */ - m3885_set_proc_ram(0xda, 0x80); // P62TASK SENSE1# - m3885_set_proc_ram(0xdb, 0x80); // P63TASK SENSE2# - m3885_set_proc_ram(0xdd, 0x80); // P65TASK PROCHOT - m3885_set_proc_ram(0xde, 0x80); // P65TASK THERMTRIP# - m3885_set_proc_ram(0xdf, 0x80); // P65TASK PME# + m3885_set_proc_ram(0xda, 0x80); /* P62TASK SENSE1# */ + m3885_set_proc_ram(0xdb, 0x80); /* P63TASK SENSE2# */ + m3885_set_proc_ram(0xdd, 0x80); /* P65TASK PROCHOT */ + m3885_set_proc_ram(0xde, 0x80); /* P65TASK THERMTRIP# */ + m3885_set_proc_ram(0xdf, 0x80); /* P65TASK PME# */ /* SMI/SCI */ - m3885_set_proc_ram(0xd8, 0x81); // P60TASK, AC_PRESN# - m3885_set_proc_ram(0xd9, 0x81); // P61TASK, LID# - m3885_set_proc_ram(0xdc, 0x81); // P64TASK, FDD/LPT# + m3885_set_proc_ram(0xd8, 0x81); /* P60TASK, AC_PRESN# */ + m3885_set_proc_ram(0xd9, 0x81); /* P61TASK, LID# */ + m3885_set_proc_ram(0xdc, 0x81); /* P64TASK, FDD/LPT# */ /* Thermal */ /* Bank 5 */ m3885_set_variable(0x0c, (kstate5_flags & ~(7 << 4)) | (5 << 4)); /* Thermal 0: Active cooling, Speed Step Down */ - m3885_set_proc_ram(0x81, 0x9c); // THRM0 - m3885_set_proc_ram(0x82, 0x01); // THRM0 CMD - m3885_set_proc_ram(0x84, TH0LOW); // THRM0 LOW - m3885_set_proc_ram(0x85, TH0HIGH); // THRM0 HIGH - m3885_set_proc_ram(0x86, 0x81); // Set Task SMI#/SCI - m3885_set_proc_ram(0x87, TH0CRIT); // THRM0 CRIT + m3885_set_proc_ram(0x81, 0x9c); /* THRM0 */ + m3885_set_proc_ram(0x82, 0x01); /* THRM0 CMD */ + m3885_set_proc_ram(0x84, TH0LOW); /* THRM0 LOW */ + m3885_set_proc_ram(0x85, TH0HIGH); /* THRM0 HIGH */ + m3885_set_proc_ram(0x86, 0x81); /* Set Task SMI#/SCI */ + m3885_set_proc_ram(0x87, TH0CRIT); /* THRM0 CRIT */ /* Thermal 1: Passive cooling, Fan On */ - m3885_set_proc_ram(0x89, 0x9c); // THRM1 - m3885_set_proc_ram(0x8a, 0x01); // THRM1 CMD - m3885_set_proc_ram(0x8c, TH1LOW); // THRM1 LOW - m3885_set_proc_ram(0x8d, TH1HIGH); // THRM1 HIGH - m3885_set_proc_ram(0x8e, 0x81); // Set Task SMI#/SCI + m3885_set_proc_ram(0x89, 0x9c); /* THRM1 */ + m3885_set_proc_ram(0x8a, 0x01); /* THRM1 CMD */ + m3885_set_proc_ram(0x8c, TH1LOW); /* THRM1 LOW */ + m3885_set_proc_ram(0x8d, TH1HIGH); /* THRM1 HIGH */ + m3885_set_proc_ram(0x8e, 0x81); /* Set Task SMI#/SCI */ /* Switch Task to SMI */ - udelay(100 * 1000); // 100ms + udelay(100 * 1000); /* 100ms */ outb(KBD_SC, 0xca); - udelay(100 * 1000); // 100ms + udelay(100 * 1000); /* 100ms */ outb(KBD_DATA, 0x17); /* Set P22 to high level, keyboard backlight default off */ - udelay(100 * 1000); // 100ms + udelay(100 * 1000); /* 100ms */ outb(KBD_SC, 0xc5); - udelay(100 * 1000); // 100ms + udelay(100 * 1000); /* 100ms */ outb(KBD_DATA, 0x4a); } u8 m3885_gpio(u8 value) { -#if 0 - int timeout; -#endif - /* First write data */ ec_write(M3885_CMDAT1, value); /* Issue command: ACCESS GPIO */ ec_write(M3885_CMCMD, 0xc5); - -#if 0 - /* CMCMD is 0 when the command is completed */ - timeout = 0xf; - while (ec_read(M3885_CMCMD) && --timeout) { - udelay(10); - printk(BIOS_DEBUG, "."); - } - if (!timeout) { - printk(BIOS_DEBUG, "\nTimeout while waiting for M3885 command!\n"); - } - - /* If it was a read function: Pin state */ - return ec_read(M3885_CMDAT1); -#else return 0; -#endif } diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 1959c32..c9712db 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -28,18 +28,6 @@ static void backlight_enable(void) { -#if 0 -// Disabled, don't let the X9511 burn out - int i; - - /* P56 is Brightness Up, and it needs a Pulse instead of a - * Level - */ - for (i = 0; i < 28; i++) { - //m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_SET|M3885_GPIO_P56); - m3885_gpio(M3885_GPIO_PULSE|M3885_GPIO_TOGGLE|M3885_GPIO_P56); - } -#endif printk(BIOS_DEBUG, "Display I/O: 0x%02x\n", inb(0x60f)); } @@ -68,7 +56,6 @@ static void mainboard_final(device_t dev) static void mainboard_enable(device_t dev) { /* Configure the MultiKey controller */ - // m3885_configure_multikey(); /* Enable LCD Backlight */ backlight_enable(); @@ -77,7 +64,6 @@ static void mainboard_enable(device_t dev) outb(inb(0x60f) | (1 << 5), 0x60f); /* LCD panel type is SIO GPIO40-43 */ - // display_id = inb(0x60f) & 0x0f; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); #if DUMP_RUNTIME_REGISTERS diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index a9e8a26..59ab0c4 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -55,11 +55,11 @@ static void *smp_write_config_table(void *v) /* Firewire 4:0.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); - // riser slot top 5:8.0 + /* riser slot top 5:8.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); - // riser slot middle 5:9.0 + /* riser slot middle 5:9.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); - // riser slot bottom 5:a.0 + /* riser slot bottom 5:a.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); /* Onboard Ethernet */ diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 8de4665..9b77afa 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h> @@ -41,47 +41,48 @@ void setup_ich7_gpios(void) /* General Registers */ outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - // ------------------------------------------------------------ - // 0 - GPO6 - Enable power of SATA channel 0 - // 0 - GPO9 - Wireless LAN power on - // 0 - GPO15 - FAN on - // 1 - GPO22 - FWH WP - // 1 - GPO24 - GPS on - // 0 - GPO25 - External Antenna Mux on - // 0 - GPO26 - BT on - // 0 - GPO27 - GSM on + /* ------------------------------------------------------------ + * 0 - GPO6 - Enable power of SATA channel 0 + * 0 - GPO9 - Wireless LAN power on + * 0 - GPO15 - FAN on + * 1 - GPO22 - FWH WP + * 1 - GPO24 - GPS on + * 0 - GPO25 - External Antenna Mux on + * 0 - GPO26 - BT on + * 0 - GPO27 - GSM on + */ outl(0x01400000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - // ------------------------------------------------------------ + /* ------------------------------------------------------------ */ /* Output Control Registers */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ /* Input Control Registers */ outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000100e8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - // ------------------------------------------------------------ - // 1 - GPO48 - FWH TBL# + /* ------------------------------------------------------------ */ + /* 1 - GPO48 - FWH TBL# */ outl(0x00010000, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ - // ------------------------------------------------------------ + /* ------------------------------------------------------------ */ } static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1 << 2; // enable LPT + lpt_en = 1 << 2; /* enable LPT */ } - // Enable Serial IRQ + /* Enable Serial IRQ */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range + /* decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range + /* decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 + /* Enable 0x02e0 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); - // COM3 decode + /* COM3 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // COM4 decode + /* COM4 decode */ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); } @@ -116,30 +117,30 @@ static void early_superio_config(void) dev = PNP_DEV(0x2e, 0x00); pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes - pnp_write_register(dev, 0x02, 0x88); // UART power on - pnp_write_register(dev, 0x03, 0x72); // Floppy - pnp_write_register(dev, 0x04, 0x01); // EPP + SPP - pnp_write_register(dev, 0x14, 0x03); // Floppy - pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy - pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base - pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base - pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA - pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA - pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ + pnp_write_register(dev, 0x01, 0x94); /* Extended Parport modes */ + pnp_write_register(dev, 0x02, 0x88); /* UART power on */ + pnp_write_register(dev, 0x03, 0x72); /* Floppy */ + pnp_write_register(dev, 0x04, 0x01); /* EPP + SPP */ + pnp_write_register(dev, 0x14, 0x03); /* Floppy */ + pnp_write_register(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ + pnp_write_register(dev, 0x23, (0x378 >> 2)); /* PP base */ + pnp_write_register(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ + pnp_write_register(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ + pnp_write_register(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ + pnp_write_register(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ + pnp_write_register(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ /* These are the SMI status registers in the SIO: */ - pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base - - pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR - pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL - pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR - pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL - pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR - pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL - pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR - pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL - pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL + pnp_write_register(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ + + pnp_write_register(dev, 0x31, 0x00); /* GPIO1 DIR */ + pnp_write_register(dev, 0x32, 0x00); /* GPIO1 POL */ + pnp_write_register(dev, 0x33, 0x40); /* GPIO2 DIR */ + pnp_write_register(dev, 0x34, 0x00); /* GPIO2 POL */ + pnp_write_register(dev, 0x35, 0xff); /* GPIO3 DIR */ + pnp_write_register(dev, 0x36, 0x00); /* GPIO3 POL */ + pnp_write_register(dev, 0x37, 0xe0); /* GPIO4 DIR */ + pnp_write_register(dev, 0x38, 0x00); /* GPIO4 POL */ + pnp_write_register(dev, 0x39, 0x80); /* GPIO4 POL */ pnp_exit_ext_func_mode(dev); } @@ -147,8 +148,6 @@ static void early_superio_config(void) static void rcba_config(void) { /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042220; @@ -168,10 +167,7 @@ static void rcba_config(void) /* Disable unused devices */ RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 | FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA; - RCBA32(0x3418) |= (1 << 0); // Required. - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; + RCBA32(0x3418) |= (1 << 0); /* Required. */ /* This should probably go into the ACPI OS Init trap */ @@ -189,15 +185,15 @@ static void early_ich7_init(void) uint8_t reg8; uint32_t reg32; - // program secondary mlt XXX byte? + /* program secondary mlt XXX byte? */ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - // reset rtc power status + /* reset rtc power status */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - // usb transient disconnect + /* usb transient disconnect */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); reg8 |= (3 << 0); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); @@ -231,7 +227,7 @@ static void early_ich7_init(void) RCBA32(0x3e0e) |= (1 << 7); RCBA32(0x3e4e) |= (1 << 7); - // next step only on ich7m b0 and later: + /* next step only on ich7m b0 and later: */ reg32 = RCBA32(0x2034); reg32 &= ~(0x0f << 16); reg32 |= (5 << 16); @@ -240,7 +236,7 @@ static void early_ich7_init(void) static void init_artec_dongle(void) { - // Enable 4MB decoding + /* Enable 4MB decoding */ outb(0xf1, 0x88); outb(0xf4, 0x88); } diff --git a/src/mainboard/roda/rk9/hda_verb.c b/src/mainboard/roda/rk9/hda_verb.c index 8a102ea..a7d2698 100644 --- a/src/mainboard/roda/rk9/hda_verb.c +++ b/src/mainboard/roda/rk9/hda_verb.c @@ -18,9 +18,9 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 - 0x43528986, // Subsystem ID - 0x0000000c, // Number of entries + 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */ + 0x43528986, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ /* Pin Widget Verb Table */ diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index fc0c8d3..df749b9 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> #include <string.h>

1 0

New patch to review for coreboot: Pyro: WACOM touchscreen ACPI HID update
by Janice Li 07 Nov '16

07 Nov '16

Janice Li (Janice.Li(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17257 -gerrit commit 6a1c53198397b75c29823c4c905d4c27df735dcd Author: Janice Li <janice.li(a)quantatw.com> Date: Mon Nov 7 17:49:44 2016 +0800 Pyro: WACOM touchscreen ACPI HID update update WACOM ACPI HID WCOMNTN2 BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by:Janice Li <janice.li(a)quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 --- src/drivers/i2c/wacom_ts/chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h index b59f630..a52e418 100644 --- a/src/drivers/i2c/wacom_ts/chip.h +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -18,7 +18,7 @@ #include <drivers/i2c/generic/chip.h> -#define WCOM50C1_HID "WCOM50C1" +#define WCOM50C1_HID "WCOMNTN2" #define PNP0C50_CID "PNP0C50" #define WCOM_TS_DESC "WCOM Touchscreen"

1 0

Patch set updated for coreboot: ec/lenovo/h8: Add USB Always On
by Nicola Corna 07 Nov '16

07 Nov '16

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17252 -gerrit commit 923d461064494bb470ba6bb49a4cdc92660eec8f Author: Nicola Corna <nicola(a)corna.info> Date: Sat Nov 5 16:06:59 2016 +0100 ec/lenovo/h8: Add USB Always On USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN (bit 0) is internal name for enabling this feature while AOCF (bits 2 and 3) is the configuration field. According to Peter Stuge, AOCF can be configured in this way: 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also adds a new configuration field in the CMOS of the X220 and the X201 to activate this feature. It probably can be also added to all the Thinkpads that support this functionality. With this functionality USB devices are able to negotiate full power from the dedicated port (usually the yellow one) even in S3. Tested on a X201 and X220 with an Android smartphone: with this feature enabled it shows "Charging" when connected during S3, without it it shows "Charging slowly" (or it doesn't charge at all on the X201). Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/ec/lenovo/h8/Makefile.inc | 1 + src/ec/lenovo/h8/h8.c | 1 + src/ec/lenovo/h8/h8.h | 5 ++++ src/ec/lenovo/h8/smm.c | 43 ++++++++++++++++++++++++++++++++++ src/ec/lenovo/h8/smm.h | 17 ++++++++++++++ src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 6 +++-- src/mainboard/lenovo/x201/smihandler.c | 4 ++++ src/mainboard/lenovo/x220/cmos.default | 1 + src/mainboard/lenovo/x220/cmos.layout | 5 +++- src/mainboard/lenovo/x220/smihandler.c | 4 ++++ 11 files changed, 85 insertions(+), 3 deletions(-) diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 4829e7b..da9cee1 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) ramstage-y += h8.c +smm-y += smm.c endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 703acad..c703a6e 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -313,6 +313,7 @@ static void h8_enable(struct device *dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + ec_write(H8_USB_ALWAYS_ON, ec_read(H8_USB_ALWAYS_ON) & ~(0x0d)); h8_trackpoint_enable(1); h8_usb_power_enable(1); diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index d3803c0..c893396 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -64,6 +64,11 @@ void h8_mainboard_init_dock (void); #define H8_LED_CONTROL_ON 0x80 #define H8_LED_CONTROL_BLINK 0xc0 +#define H8_USB_ALWAYS_ON 0x0d +#define H8_USB_ALWAYS_ON_DISABLE 0x00 +#define H8_USB_ALWAYS_ON_AC_ONLY 0x0d +#define H8_USB_ALWAYS_ON_AC_BAT 0x01 + #define H8_LED_CONTROL_POWER_LED 0x00 #define H8_LED_CONTROL_BAT0_LED 0x01 #define H8_LED_CONTROL_BAT1_LED 0x02 diff --git a/src/ec/lenovo/h8/smm.c b/src/ec/lenovo/h8/smm.c new file mode 100644 index 0000000..7d7967b --- /dev/null +++ b/src/ec/lenovo/h8/smm.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> + +#include "smm.h" + +void h8_usb_always_on(void) +{ + u8 val; + u8 reg; + + if (get_option(&val, "usb_always_on") != CB_SUCCESS) + val = 0; + + reg = ec_read(H8_USB_ALWAYS_ON); + + if (val == 2) + { + reg &= ~(0x0c); + reg |= 0x01; + } + else if (val == 1) + reg |= 0x0d; + else + reg &= ~(0x0d); + + ec_write(H8_USB_ALWAYS_ON, reg); +} diff --git a/src/ec/lenovo/h8/smm.h b/src/ec/lenovo/h8/smm.h new file mode 100644 index 0000000..5b02450 --- /dev/null +++ b/src/ec/lenovo/h8/smm.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void h8_usb_always_on(void); + diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 50d17ae..9f1e31d 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +usb_always_on=Disable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 2a91eb7..36b09f2 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -70,8 +70,7 @@ entries 419 1 e 1 power_management_beeps 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode - -#422 2 r 0 unused +422 2 e 11 usb_always_on # coreboot config options: northbridge 424 3 e 10 gfx_uma_size @@ -123,6 +122,9 @@ enumerations 10 3 128M 10 5 96M 10 6 160M +11 0 Disable +11 1 AC only +11 2 AC and battery # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 591a521..538ca00 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,6 +26,7 @@ #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> +#include <ec/lenovo/h8/smm.h> #include <delay.h> #include "dock.h" #include "smi.h" @@ -178,6 +180,8 @@ int mainboard_smi_apmc(u8 data) void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 1b8e212..91331ab 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -10,6 +10,7 @@ wwan=Enable wlan=Enable touchpad=Enable sata_mode=AHCI +usb_always_on=Disable fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 143ee80..bc506f1 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -69,7 +69,7 @@ entries 418 1 e 1 sticky_fn 419 1 e 1 power_management_beeps 421 1 e 9 sata_mode -#422 2 r 1 unused +422 2 e 12 usb_always_on # coreboot config options: cpu 424 1 e 2 hyper_threading @@ -134,6 +134,9 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Disable +12 1 AC only +12 2 AC and battery # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 08554c9..a98cd82 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,6 +22,7 @@ #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> +#include <ec/lenovo/h8/smm.h> #include <delay.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -133,6 +135,8 @@ int mainboard_smi_apmc(u8 data) void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */

1 0

Patch set updated for coreboot: ec/lenovo/h8: Add USB Always On
by Nicola Corna 07 Nov '16

07 Nov '16

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17252 -gerrit commit 92a0feba53cadc6b3c75005f42ce18fad7e4338c Author: Nicola Corna <nicola(a)corna.info> Date: Sat Nov 5 16:06:59 2016 +0100 ec/lenovo/h8: Add USB Always On USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN (bit 0) is internal name for enabling this feature while AOCF (bits 2 and 3) is the configuration field. According to Peter Stuge, AOCF can be configured in this way: 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also adds a new configuration field in the CMOS of the X220 and the X201 to activate this feature. It probably can be also added to all the Thinkpads that support this functionality. With this functionality USB devices are able to negotiate full power from the dedicated port (usually the yellow one) even in S3. Tested on a X201 and X220 with an Android smartphone: with this feature enabled it shows "Charging" when connected during S3, without it it shows "Charging slowly" (or it doesn't charge at all on the X201). Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/ec/lenovo/h8/Makefile.inc | 1 + src/ec/lenovo/h8/h8.c | 1 + src/ec/lenovo/h8/h8.h | 5 ++++ src/ec/lenovo/h8/smm.c | 43 ++++++++++++++++++++++++++++++++++ src/ec/lenovo/h8/smm.h | 17 ++++++++++++++ src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 6 +++-- src/mainboard/lenovo/x201/smihandler.c | 3 +++ src/mainboard/lenovo/x220/cmos.default | 1 + src/mainboard/lenovo/x220/cmos.layout | 5 +++- src/mainboard/lenovo/x220/smihandler.c | 4 ++++ 11 files changed, 84 insertions(+), 3 deletions(-) diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 4829e7b..da9cee1 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) ramstage-y += h8.c +smm-y += smm.c endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 703acad..c703a6e 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -313,6 +313,7 @@ static void h8_enable(struct device *dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + ec_write(H8_USB_ALWAYS_ON, ec_read(H8_USB_ALWAYS_ON) & ~(0x0d)); h8_trackpoint_enable(1); h8_usb_power_enable(1); diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index d3803c0..c893396 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -64,6 +64,11 @@ void h8_mainboard_init_dock (void); #define H8_LED_CONTROL_ON 0x80 #define H8_LED_CONTROL_BLINK 0xc0 +#define H8_USB_ALWAYS_ON 0x0d +#define H8_USB_ALWAYS_ON_DISABLE 0x00 +#define H8_USB_ALWAYS_ON_AC_ONLY 0x0d +#define H8_USB_ALWAYS_ON_AC_BAT 0x01 + #define H8_LED_CONTROL_POWER_LED 0x00 #define H8_LED_CONTROL_BAT0_LED 0x01 #define H8_LED_CONTROL_BAT1_LED 0x02 diff --git a/src/ec/lenovo/h8/smm.c b/src/ec/lenovo/h8/smm.c new file mode 100644 index 0000000..7d7967b --- /dev/null +++ b/src/ec/lenovo/h8/smm.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> + +#include "smm.h" + +void h8_usb_always_on(void) +{ + u8 val; + u8 reg; + + if (get_option(&val, "usb_always_on") != CB_SUCCESS) + val = 0; + + reg = ec_read(H8_USB_ALWAYS_ON); + + if (val == 2) + { + reg &= ~(0x0c); + reg |= 0x01; + } + else if (val == 1) + reg |= 0x0d; + else + reg &= ~(0x0d); + + ec_write(H8_USB_ALWAYS_ON, reg); +} diff --git a/src/ec/lenovo/h8/smm.h b/src/ec/lenovo/h8/smm.h new file mode 100644 index 0000000..5b02450 --- /dev/null +++ b/src/ec/lenovo/h8/smm.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void h8_usb_always_on(void); + diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 50d17ae..9f1e31d 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +usb_always_on=Disable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 2a91eb7..36b09f2 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -70,8 +70,7 @@ entries 419 1 e 1 power_management_beeps 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode - -#422 2 r 0 unused +422 2 e 11 usb_always_on # coreboot config options: northbridge 424 3 e 10 gfx_uma_size @@ -123,6 +122,9 @@ enumerations 10 3 128M 10 5 96M 10 6 160M +11 0 Disable +11 1 AC only +11 2 AC and battery # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 591a521..9ff391d 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -178,6 +179,8 @@ int mainboard_smi_apmc(u8 data) void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 1b8e212..91331ab 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -10,6 +10,7 @@ wwan=Enable wlan=Enable touchpad=Enable sata_mode=AHCI +usb_always_on=Disable fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 143ee80..bc506f1 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -69,7 +69,7 @@ entries 418 1 e 1 sticky_fn 419 1 e 1 power_management_beeps 421 1 e 9 sata_mode -#422 2 r 1 unused +422 2 e 12 usb_always_on # coreboot config options: cpu 424 1 e 2 hyper_threading @@ -134,6 +134,9 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Disable +12 1 AC only +12 2 AC and battery # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 08554c9..a98cd82 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Nicola Corna <nicola(a)corna.info> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,6 +22,7 @@ #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> +#include <ec/lenovo/h8/smm.h> #include <delay.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -133,6 +135,8 @@ int mainboard_smi_apmc(u8 data) void mainboard_smi_sleep(u8 slp_typ) { + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */

1 0

Patch set updated for coreboot: riscv: start to use the configstring functions
by Ronald G. Minnich 07 Nov '16

07 Nov '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17256 -gerrit commit b5a8ddce99becfa374c74bfc33aa7452ab115b73 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sun Nov 6 20:54:20 2016 -0800 riscv: start to use the configstring functions These functions will allow us to remove hardcodes, as long as we can verify the qemu and lowrisc targets implement the configstring correctly. Hence, for the most part, we'll start with mainboard changes first. Change-Id: I7dd3f553d3e61f1c49752fb04402b134fdfdf979 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 9 ++++++--- src/arch/riscv/boot.c | 8 ++++---- src/mainboard/emulation/spike-riscv/romstage.c | 7 +++++++ 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index cf6ce99..f5b0958 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -42,7 +42,8 @@ bootblock-y += \ $(top)/src/lib/memcmp.c \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c + $(top)/src/lib/memset.c \ + $(top)/src/commonlib/configstring.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -68,7 +69,8 @@ romstage-y += \ $(top)/src/lib/memcmp.c \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c + $(top)/src/lib/memset.c \ + $(top)/src/commonlib/configstring.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -102,7 +104,8 @@ ramstage-y += \ $(top)/src/lib/memcmp.c \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ - $(top)/src/lib/memset.c + $(top)/src/lib/memset.c \ + $(top)/src/commonlib/configstring.c $(eval $(call create_class_compiler,rmodules,riscv)) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 0fa4d5f..9483c48 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -18,19 +18,19 @@ #include <arch/encoding.h> #include <rules.h> #include <console/console.h> +#include <commonlib/configstring.h> void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); void riscvpayload(const char *configstring, void *payload); - uint32_t addr = *(uint32_t *)CONFIG_ARCH_CONFIGSTRING_RISCV; - const char *configstring = (const char *)(uintptr_t)addr; + const char *config = configstring(); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { - printk(BIOS_SPEW, "Config string: '%s'\n", configstring); + printk(BIOS_SPEW, "Config string: '%s'\n", config); initVirtualMemory(); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(configstring, doit); + riscvpayload(config, doit); } doit(prog_entry_arg(prog)); diff --git a/src/mainboard/emulation/spike-riscv/romstage.c b/src/mainboard/emulation/spike-riscv/romstage.c index b6314ccd..1317b00 100644 --- a/src/mainboard/emulation/spike-riscv/romstage.c +++ b/src/mainboard/emulation/spike-riscv/romstage.c @@ -15,9 +15,16 @@ #include <console/console.h> #include <program_loading.h> +#include <string.h> +#include <commonlib/configstring.h> void main(void) { + uintptr_t base; + size_t size; + console_init(); + query_mem(configstring(), &base, &size); + printk(BIOS_SPEW, "0x%lx bytes of memory at 0x%llx\n", size, base); run_ramstage(); }

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coreboot-gerrit November 2016