coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch set updated for coreboot: soc/intel/apollolake: Provide chipset value for ifdtool
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17259 -gerrit commit 49f111cfba521f6be9e81d4f0880db31ac5f0fd2 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Nov 6 23:43:57 2016 -0800 soc/intel/apollolake: Provide chipset value for ifdtool Change-Id: I99454a9fca3b677a389bcaf7693ff4e18415c9ad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..4e61cf3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -260,4 +260,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config IFD_CHIPSET + string "Let ifdtool know what chipset to use" + default "aplk" + endif

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Patch set updated for coreboot: southbridge/intel: Set chipset in ifdtool invocations
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17258 -gerrit commit 13dfca11be6979eae98ae87b9cc26ddd7b2928c6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Nov 6 23:43:16 2016 -0800 southbridge/intel: Set chipset in ifdtool invocations Since IFD format is floating, ifdtool needs to be parameterized with a chipset it is dealing with. Add -p <chipset> argument to ifdtool invocations if chipset provides it. Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/southbridge/intel/common/firmware/Makefile.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index fa28ccf..8307697 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -33,6 +33,9 @@ IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +ifneq ($(CONFIG_IFD_CHIPSET),"") +IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) +endif endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) @@ -50,6 +53,7 @@ endif ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre @@ -57,23 +61,27 @@ endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) printf " IFDTOOL gbe.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ -i GbE:$(CONFIG_GBE_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_EM100),y) printf " IFDTOOL Setting EM100 mode\n" - $(objutil)/ifdtool/ifdtool --em100 $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) --em100 $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif

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Patch set updated for coreboot: ifdtool: Add option to specify platform (-p) quirks
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17202 -gerrit commit 2fa932ecfd2a3d49e872f4f75760adc3a0ba1e0e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 31 19:31:54 2016 -0700 ifdtool: Add option to specify platform (-p) quirks Apollo Lake uses yet another descriptor format where only two masters are used: CPU/BIOS and CSE/TXE. CSE stores data in a region number 5 that has not been used previously and CPU must not write it. Add quirk (-p aplk) that locks descriptor according to recommended values. BUG=chrome-os-partner:58974 TEST=ifdtool -p aplk -l bios.bin; ifdtool -d bios.bin.new. Make sure FLMSTR1 and FLMSTR2 are set correctly. unlock with -l and make sure FLMSTRs are restored. Change-Id: I3f33372bef3ff75d0e34030694c79cd07d5540de Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- util/ifdtool/ifdtool.c | 51 +++++++++++++++++++++++++++++++++++++------------- util/ifdtool/ifdtool.h | 4 ++++ 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 74588e1..c858fee 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -30,6 +30,7 @@ static int ifd_version; static int max_regions = 0; static int selected_chip = 0; +static int platform = -1; static const struct region_name region_names[MAX_REGIONS] = { { "Flash Descriptor", "fd" }, @@ -832,18 +833,31 @@ static void lock_descriptor(char *filename, char *image, int size) fmba->flmstr3 = 0x118; } - /* CPU/BIOS can read descriptor, BIOS, and GbE. */ - fmba->flmstr1 |= 0xb << rd_shift; - /* CPU/BIOS can write BIOS and GbE. */ - fmba->flmstr1 |= 0xa << wr_shift; - /* ME can read descriptor, ME, and GbE. */ - fmba->flmstr2 |= 0xd << rd_shift; - /* ME can write ME and GbE. */ - fmba->flmstr2 |= 0xc << wr_shift; - /* GbE can write only GbE. */ - fmba->flmstr3 |= 0x8 << rd_shift; - /* GbE can read only GbE. */ - fmba->flmstr3 |= 0x8 << wr_shift; + switch (platform) { + case PLATFORM_APOLLOLAKE: + /* CPU/BIOS can read descriptor and BIOS */ + fmba->flmstr1 |= 0x3 << rd_shift; + /* CPU/BIOS can write BIOS */ + fmba->flmstr1 |= 0x2 << wr_shift; + /* TXE can read descriptor, BIOS and Device Expansion */ + fmba->flmstr2 |= 0x23 << rd_shift; + /* TXE can only write Device Expansion */ + fmba->flmstr2 |= 0x20 << wr_shift; + break; + default: + /* CPU/BIOS can read descriptor, BIOS, and GbE. */ + fmba->flmstr1 |= 0xb << rd_shift; + /* CPU/BIOS can write BIOS and GbE. */ + fmba->flmstr1 |= 0xa << wr_shift; + /* ME can read descriptor, ME, and GbE. */ + fmba->flmstr2 |= 0xd << rd_shift; + /* ME can write ME and GbE. */ + fmba->flmstr2 |= 0xc << wr_shift; + /* GbE can write only GbE. */ + fmba->flmstr3 |= 0x8 << rd_shift; + /* GbE can read only GbE. */ + fmba->flmstr3 |= 0x8 << wr_shift; + } write_image(filename, image, size); } @@ -1140,6 +1154,8 @@ static void print_usage(const char *name) " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" " -u | --unlock Unlock firmware descriptor and ME region\n" + " -p | --platform Add platform-specific quirks\n" + " aplk - Apollo Lake\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" @@ -1171,10 +1187,11 @@ int main(int argc, char *argv[]) {"unlock", 0, NULL, 'u'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, + {"platform", 0, NULL, 'p'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:D:C:xi:n:s:eluvh?", + while ((opt = getopt_long(argc, argv, "df:D:C:xi:n:s:p:eluvh?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1325,6 +1342,14 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } break; + case 'p': + if (!strcmp(optarg, "aplk")) { + platform = PLATFORM_APOLLOLAKE; + } else { + fprintf(stderr, "Unknown platform: %s\n", optarg); + exit(EXIT_FAILURE); + } + break; case 'v': print_version(); exit(EXIT_SUCCESS); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 7878712..fe98d6a 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -21,6 +21,10 @@ enum ifd_version { IFD_VERSION_2, }; +enum platform { + PLATFORM_APOLLOLAKE +}; + #define LAYOUT_LINELEN 80 enum spi_frequency {

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Patch merged into coreboot/master: soc/intel/skylake: Add device id for PCH-Y
by gerrit＠coreboot.org 07 Nov '16

07 Nov '16

the following patch was just integrated into master: commit 50bb67eea0cd704dd575f3f9ec9d8fe65942311d Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:36:31 2016 +0530 soc/intel/skylake: Add device id for PCH-Y Add device id for PCH-Y used in Kaby Lake RVP3 board. Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17244 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17244 for details. -gerrit

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Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 07 Nov '16

07 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit b1580f8041cc8aed83defbbf0539636e192c3379 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN) and 19 (BKLT_CTRL_SEL), were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. This also adds a IDG disable op, since it is used here to uncleam the VGA from the IGD. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 8 -------- src/drivers/lenovo/chip.h | 24 ++++++++++++++++++++++++ src/drivers/lenovo/hybrid_graphics.c | 22 ++++++++++++++++++++-- src/mainboard/lenovo/t400/devicetree.cb | 7 +++++++ src/mainboard/lenovo/t400/romstage.c | 2 +- src/mainboard/lenovo/t420s/devicetree.cb | 5 +++++ src/mainboard/lenovo/t520/devicetree.cb | 5 +++++ src/mainboard/lenovo/t530/devicetree.cb | 5 +++++ src/northbridge/intel/gm45/gma.c | 13 +++++++++++++ 9 files changed, 80 insertions(+), 11 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..fe1ea6e 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -31,11 +31,3 @@ endif config DRIVERS_LENOVO_HYBRID_GRAPHICS bool default n - -config HYBRID_GRAPHICS_GPIO_NUM - depends on DRIVERS_LENOVO_HYBRID_GRAPHICS - int - default 52 - help - Set a default GPIO that sets the panel LVDS signal routing to - integrated or discrete GPU. diff --git a/src/drivers/lenovo/chip.h b/src/drivers/lenovo/chip.h new file mode 100644 index 0000000..36a25bf --- /dev/null +++ b/src/drivers/lenovo/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DRIVERS_LENOVO_CHIP_H +#define DRIVERS_LENOVO_CHIP_H + +struct drivers_lenovo_config { + u32 hybrid_gpio; + u8 discrete_is_high; + u32 bcl_ctl_gpio; + u32 gfx_pwr_gpio; +}; + +#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..33958c2 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <southbridge/intel/common/gpio.h> +#include "chip.h" /* Hybrid graphics allows to connect LVDS interface to either iGPU * or dGPU depending on GPIO level. @@ -42,10 +43,19 @@ static void hybrid_graphics_disable_peg(struct device *dev) { + struct drivers_lenovo_config *config = dev->chip_info; struct device *peg_dev; + u8 disable_lvl = config->discrete_is_high ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + if (config->hybrid_gpio) + set_gpio(config->hybrid_gpio, disable_lvl); + if (config->bcl_ctl_gpio) + set_gpio(config->bcl_ctl_gpio, disable_lvl); + if (config->gfx_pwr_gpio) + set_gpio(config->gfx_pwr_gpio, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -61,14 +71,22 @@ static void hybrid_graphics_disable_peg(struct device *dev) * is present. Enable/disable VGA devices here. */ static void hybrid_graphics_enable_peg(struct device *dev) { + struct drivers_lenovo_config *config = dev->chip_info; u8 hybrid_graphics_mode; + u8 enable_lvl = config->discrete_is_high ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + if(config->hybrid_gpio) + set_gpio(config->hybrid_gpio, enable_lvl); + if (config->bcl_ctl_gpio) + set_gpio(config->bcl_ctl_gpio, enable_lvl); + if (config->gfx_pwr_gpio) + set_gpio(config->gfx_pwr_gpio, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 9940bb7..9ae08fc 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -42,6 +42,13 @@ chip northbridge/intel/gm45 device pci 03.1 off end # ME device pci 03.2 off end # ME device pci 03.3 off end # ME + + chip drivers/lenovo + register hybrid_gpio = "22" + register discrete_is_high = "1" + register bcl_ctl_gpio = "19" + register gfx_pwr_gpio = "49" + end chip southbridge/intel/i82801ix register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index bba53d1..7307f8f 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -101,7 +101,7 @@ void mainboard_romstage_entry(unsigned long bist) sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; + sysinfo.enable_peg = 1; get_gmch_info(&sysinfo); raminit(&sysinfo, s3resume); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 24f9ebd..fc0f47c 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -49,6 +49,11 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 6c638e5..b12d60a 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -46,6 +46,11 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on end # vga controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 0731251..035e225 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -46,6 +46,11 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # vga controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..a42a7e3 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -736,6 +736,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static void gma_func0_disable(struct device *dev) +{ + u16 reg16; + device_t dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); + + reg16 = pci_read_config16(dev_host, D0F0_GGC); + reg16 |= (1 << 1); /* disable VGA decode */ + pci_write_config16(dev_host, D0F0_GGC, reg16); + + dev->enabled = 0; +} + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -744,6 +756,7 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .scan_bus = 0, .enable = 0, + .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, };

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Patch set updated for coreboot: vboot: Disable vboot verification when Chrome EC disabled
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17246 -gerrit commit 0642efaf1733b42831a193c1e5089e16c69f88c5 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:51:14 2016 +0530 vboot: Disable vboot verification when Chrome EC disabled When Chrome EC is disabled, vboot hash is not available during S3 resume Hence disable vboot verification when Chrome EC is not available. Change-Id: I665f5f0e2e53da7b735de30443d323572d8a1a9c Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/vboot/vboot_logic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/vboot/vboot_logic.c b/src/vboot/vboot_logic.c index bc6ab48..41896e1 100644 --- a/src/vboot/vboot_logic.c +++ b/src/vboot/vboot_logic.c @@ -119,6 +119,13 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) int is_resume; /* + * Chrome EC is the only support for vboot_save_hash()/vboot_retrieve_hash(), if Chrome EC + * is not enabled then return. + */ + if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return 0; + + /* * Nothing to do since resuming on the platform doesn't require * vboot verification again. */

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Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 07 Nov '16

07 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit aa742b3e918784f83e9871625138e5660bdf67e5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN) and 19 (BKLT_CTRL_SEL), were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. This also adds a IDG disable op, since it is used here to uncleam the VGA from the IGD. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 8 -------- src/drivers/lenovo/hybrid_graphics.c | 22 ++++++++++++++++++++-- src/mainboard/lenovo/t400/devicetree.cb | 7 +++++++ src/mainboard/lenovo/t400/romstage.c | 2 +- src/mainboard/lenovo/t420s/devicetree.cb | 5 +++++ src/mainboard/lenovo/t520/devicetree.cb | 5 +++++ src/mainboard/lenovo/t530/devicetree.cb | 5 +++++ src/northbridge/intel/gm45/gma.c | 13 +++++++++++++ 8 files changed, 56 insertions(+), 11 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..fe1ea6e 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -31,11 +31,3 @@ endif config DRIVERS_LENOVO_HYBRID_GRAPHICS bool default n - -config HYBRID_GRAPHICS_GPIO_NUM - depends on DRIVERS_LENOVO_HYBRID_GRAPHICS - int - default 52 - help - Set a default GPIO that sets the panel LVDS signal routing to - integrated or discrete GPU. diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..33958c2 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <southbridge/intel/common/gpio.h> +#include "chip.h" /* Hybrid graphics allows to connect LVDS interface to either iGPU * or dGPU depending on GPIO level. @@ -42,10 +43,19 @@ static void hybrid_graphics_disable_peg(struct device *dev) { + struct drivers_lenovo_config *config = dev->chip_info; struct device *peg_dev; + u8 disable_lvl = config->discrete_is_high ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + if (config->hybrid_gpio) + set_gpio(config->hybrid_gpio, disable_lvl); + if (config->bcl_ctl_gpio) + set_gpio(config->bcl_ctl_gpio, disable_lvl); + if (config->gfx_pwr_gpio) + set_gpio(config->gfx_pwr_gpio, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -61,14 +71,22 @@ static void hybrid_graphics_disable_peg(struct device *dev) * is present. Enable/disable VGA devices here. */ static void hybrid_graphics_enable_peg(struct device *dev) { + struct drivers_lenovo_config *config = dev->chip_info; u8 hybrid_graphics_mode; + u8 enable_lvl = config->discrete_is_high ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + if(config->hybrid_gpio) + set_gpio(config->hybrid_gpio, enable_lvl); + if (config->bcl_ctl_gpio) + set_gpio(config->bcl_ctl_gpio, enable_lvl); + if (config->gfx_pwr_gpio) + set_gpio(config->gfx_pwr_gpio, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 9940bb7..9ae08fc 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -42,6 +42,13 @@ chip northbridge/intel/gm45 device pci 03.1 off end # ME device pci 03.2 off end # ME device pci 03.3 off end # ME + + chip drivers/lenovo + register hybrid_gpio = "22" + register discrete_is_high = "1" + register bcl_ctl_gpio = "19" + register gfx_pwr_gpio = "49" + end chip southbridge/intel/i82801ix register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index bba53d1..7307f8f 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -101,7 +101,7 @@ void mainboard_romstage_entry(unsigned long bist) sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; + sysinfo.enable_peg = 1; get_gmch_info(&sysinfo); raminit(&sysinfo, s3resume); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 24f9ebd..fc0f47c 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -49,6 +49,11 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 6c638e5..b12d60a 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -46,6 +46,11 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on end # vga controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 0731251..035e225 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -46,6 +46,11 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # vga controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..a42a7e3 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -736,6 +736,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static void gma_func0_disable(struct device *dev) +{ + u16 reg16; + device_t dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); + + reg16 = pci_read_config16(dev_host, D0F0_GGC); + reg16 |= (1 << 1); /* disable VGA decode */ + pci_write_config16(dev_host, D0F0_GGC, reg16); + + dev->enabled = 0; +} + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -744,6 +756,7 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .scan_bus = 0, .enable = 0, + .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, };

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Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 07 Nov '16

07 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit 3be9cc31d05728cd8039b1f942736d16091ea050 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN) and 19 (BKLT_CTRL_SEL), were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. This also adds a IDG disable op, since it is used here to uncleam the VGA from the IGD. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 10 +--------- src/drivers/lenovo/hybrid_graphics.c | 22 ++++++++++++++++++++-- src/mainboard/lenovo/t400/devicetree.cb | 7 +++++++ src/mainboard/lenovo/t400/romstage.c | 2 +- src/mainboard/lenovo/t420s/devicetree.cb | 5 +++++ src/mainboard/lenovo/t520/devicetree.cb | 5 +++++ src/mainboard/lenovo/t530/devicetree.cb | 5 +++++ src/northbridge/intel/gm45/gma.c | 13 +++++++++++++ 8 files changed, 57 insertions(+), 12 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..a34878d 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -30,12 +30,4 @@ endif config DRIVERS_LENOVO_HYBRID_GRAPHICS bool - default n - -config HYBRID_GRAPHICS_GPIO_NUM - depends on DRIVERS_LENOVO_HYBRID_GRAPHICS - int - default 52 - help - Set a default GPIO that sets the panel LVDS signal routing to - integrated or discrete GPU. + default n \ No newline at end of file diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..33958c2 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <southbridge/intel/common/gpio.h> +#include "chip.h" /* Hybrid graphics allows to connect LVDS interface to either iGPU * or dGPU depending on GPIO level. @@ -42,10 +43,19 @@ static void hybrid_graphics_disable_peg(struct device *dev) { + struct drivers_lenovo_config *config = dev->chip_info; struct device *peg_dev; + u8 disable_lvl = config->discrete_is_high ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + if (config->hybrid_gpio) + set_gpio(config->hybrid_gpio, disable_lvl); + if (config->bcl_ctl_gpio) + set_gpio(config->bcl_ctl_gpio, disable_lvl); + if (config->gfx_pwr_gpio) + set_gpio(config->gfx_pwr_gpio, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -61,14 +71,22 @@ static void hybrid_graphics_disable_peg(struct device *dev) * is present. Enable/disable VGA devices here. */ static void hybrid_graphics_enable_peg(struct device *dev) { + struct drivers_lenovo_config *config = dev->chip_info; u8 hybrid_graphics_mode; + u8 enable_lvl = config->discrete_is_high ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + if(config->hybrid_gpio) + set_gpio(config->hybrid_gpio, enable_lvl); + if (config->bcl_ctl_gpio) + set_gpio(config->bcl_ctl_gpio, enable_lvl); + if (config->gfx_pwr_gpio) + set_gpio(config->gfx_pwr_gpio, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 9940bb7..9ae08fc 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -42,6 +42,13 @@ chip northbridge/intel/gm45 device pci 03.1 off end # ME device pci 03.2 off end # ME device pci 03.3 off end # ME + + chip drivers/lenovo + register hybrid_gpio = "22" + register discrete_is_high = "1" + register bcl_ctl_gpio = "19" + register gfx_pwr_gpio = "49" + end chip southbridge/intel/i82801ix register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index bba53d1..7307f8f 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -101,7 +101,7 @@ void mainboard_romstage_entry(unsigned long bist) sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; + sysinfo.enable_peg = 1; get_gmch_info(&sysinfo); raminit(&sysinfo, s3resume); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 24f9ebd..fc0f47c 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -49,6 +49,11 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 6c638e5..b12d60a 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -46,6 +46,11 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on end # vga controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 0731251..035e225 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -46,6 +46,11 @@ chip northbridge/intel/sandybridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # vga controller + chip drivers/lenovo + register hybrid_gpio = "52" + register discrete_is_high = "0" + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8938197..a42a7e3 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -736,6 +736,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static void gma_func0_disable(struct device *dev) +{ + u16 reg16; + device_t dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); + + reg16 = pci_read_config16(dev_host, D0F0_GGC); + reg16 |= (1 << 1); /* disable VGA decode */ + pci_write_config16(dev_host, D0F0_GGC, reg16); + + dev->enabled = 0; +} + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -744,6 +756,7 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .scan_bus = 0, .enable = 0, + .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, };

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Patch set updated for coreboot: i2c/wacom_ts: Update WACOM touchscreen ACPI _HID
by Kevin Chiu 07 Nov '16

07 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17257 -gerrit commit 0e08aa8ceee445b32cb54225cd5206d91e5785f7 Author: Janice Li <janice.li(a)quantatw.com> Date: Mon Nov 7 17:49:44 2016 +0800 i2c/wacom_ts: Update WACOM touchscreen ACPI _HID Wacom request ACPI _HID WCOMNTN2 in FW to support touchscreen FW update for Pyro specifically BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li(a)quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 --- src/drivers/i2c/wacom_ts/chip.h | 1 + src/drivers/i2c/wacom_ts/ts.c | 1 + src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h index b59f630..268d212 100644 --- a/src/drivers/i2c/wacom_ts/chip.h +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -23,6 +23,7 @@ #define WCOM_TS_DESC "WCOM Touchscreen" struct drivers_i2c_wacom_ts_config { + const char *hid; /* ACPI _HID (required) */ struct drivers_i2c_generic_config generic; uint8_t hid_desc_reg_offset; }; diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c index ebc8883..96d4853 100644 --- a/src/drivers/i2c/wacom_ts/ts.c +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -21,6 +21,7 @@ static void i2c_wacom_ts_fill_dsm(struct device *dev) { struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + config->generic.hid = config->hid; struct dsm_i2c_hid_config dsm_config = { .hid_desc_reg_offset = config->hid_desc_reg_offset, }; diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index a0ba584..50107ce 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -132,8 +132,8 @@ chip soc/intel/apollolake end # - I2C 2 device pci 16.3 on chip drivers/i2c/wacom_ts + register "hid" = ""WCOMNTN2""; register "generic" = "{ - .hid = WCOM50C1_HID, .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_EDGE_LOW(GPIO_21_IRQ),

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Patch set updated for coreboot: soc/intel/skylake: Add device id for PCH-Y
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17244 -gerrit commit a0c1b09fddff4a9984d6b4ac9725b44ff3a82948 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:36:31 2016 +0530 soc/intel/skylake: Add device id for PCH-Y Add device id for PCH-Y used in Kaby Lake RVP3 board. Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/bootblock/report_platform.c | 13 +++++++------ src/soc/intel/skylake/include/soc/pch.h | 1 + src/soc/intel/skylake/lpc.c | 1 + 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index f10159f..e2f4441 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -51,12 +51,13 @@ static struct { u16 lpcid; const char *name; } pch_table[] = { - { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, - { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, - { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, - { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, - { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, - { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, + { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" }, + { PCH_SPT_LP_U_BASE, "Skylake-U Base" }, + { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, + { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, + { PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" }, + { PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" }, + { PCH_KBL_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium" }, }; static struct { diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 37fe1f9..701a6f5 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -26,6 +26,7 @@ #define PCH_SPT_LP_U_BASE 0x9d43 #define PCH_SPT_LP_U_PREMIUM 0x9d48 #define PCH_SPT_LP_Y_PREMIUM 0x9d46 +#define PCH_KBL_LP_Y_PREMIUM_HDCP22 0x9d4b #define PCH_KBL_LP_U_PREMIUM 0x9d58 #define PCH_KBL_LP_Y_PREMIUM 0x9d56 diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 3b5ccfe..1355c80 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -319,6 +319,7 @@ static const unsigned short pci_device_ids[] = { PCH_SPT_LP_Y_PREMIUM, PCH_KBL_LP_U_PREMIUM, PCH_KBL_LP_Y_PREMIUM, + PCH_KBL_LP_Y_PREMIUM_HDCP22, 0 };

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coreboot-gerrit November 2016