coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/skylake: Fix SATA booting to OS issue
by gerrit＠coreboot.org 07 Nov '16

07 Nov '16

the following patch was just integrated into master: commit cb8849b68671c54ea2521cd8fb1ba289136b5b85 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Nov 4 13:26:41 2016 +0530 soc/intel/skylake: Fix SATA booting to OS issue SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/17229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17229 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Provide chipset value for ifdtool
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17259 -gerrit commit 3be00fac25121df9c0fdd6a404bae1cd44b6ec60 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Nov 6 23:43:57 2016 -0800 soc/intel/apollolake: Provide chipset value for ifdtool Change-Id: I99454a9fca3b677a389bcaf7693ff4e18415c9ad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..4e61cf3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -260,4 +260,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config IFD_CHIPSET + string "Let ifdtool know what chipset to use" + default "aplk" + endif

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Patch set updated for coreboot: southbridge/intel: Set chipset in ifdtool invocations
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17258 -gerrit commit 93105b2b31fd221347018ea72ee5ec4808ec7e70 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Nov 6 23:43:16 2016 -0800 southbridge/intel: Set chipset in ifdtool invocations Since IFD format is floating, ifdtool needs to be parameterized with a chipset it is dealing with. Add -p <chipset> argument to ifdtool invocations if chipset provides it. Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/southbridge/intel/common/firmware/Makefile.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index fa28ccf..17e53b5 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -33,6 +33,9 @@ IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) +IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) +endif endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) @@ -50,6 +53,7 @@ endif ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre @@ -57,23 +61,27 @@ endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) printf " IFDTOOL gbe.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ -i GbE:$(CONFIG_GBE_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_EM100),y) printf " IFDTOOL Setting EM100 mode\n" - $(objutil)/ifdtool/ifdtool --em100 $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) --em100 $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif

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Patch set updated for coreboot: soc/intel/apollolake: Provide chipset value for ifdtool
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17259 -gerrit commit e73a36d95235ac12d987bd6359438f2034bbdf63 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Nov 6 23:43:57 2016 -0800 soc/intel/apollolake: Provide chipset value for ifdtool Change-Id: I99454a9fca3b677a389bcaf7693ff4e18415c9ad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 187214a..4e61cf3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -260,4 +260,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config IFD_CHIPSET + string "Let ifdtool know what chipset to use" + default "aplk" + endif

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Patch set updated for coreboot: southbridge/intel: Set chipset in ifdtool invocations
by Andrey Petrov 07 Nov '16

07 Nov '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17258 -gerrit commit 61976023f4096e238d8acf23b48d674cbcdfda43 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Nov 6 23:43:16 2016 -0800 southbridge/intel: Set chipset in ifdtool invocations Since IFD format is floating, ifdtool needs to be parameterized with a chipset it is dealing with. Add -p <chipset> argument to ifdtool invocations if chipset provides it. Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/southbridge/intel/common/firmware/Makefile.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index fa28ccf..84b7318 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -33,6 +33,9 @@ IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +ifneq($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) +IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) +endif endif add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) @@ -50,6 +53,7 @@ endif ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre @@ -57,23 +61,27 @@ endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) printf " IFDTOOL gbe.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ -i GbE:$(CONFIG_GBE_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_EM100),y) printf " IFDTOOL Setting EM100 mode\n" - $(objutil)/ifdtool/ifdtool --em100 $(obj)/coreboot.pre + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) --em100 $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif

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New patch to review for coreboot: vboot: Fix line greater than 80 columns
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17265 -gerrit commit 24364ea5c35d437fdf0c8818c17c346f0468aad9 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Nov 8 00:27:41 2016 +0530 vboot: Fix line greater than 80 columns Fix comment greater than 80 columns. Change-Id: Ie0be96868e8a99f79781c6bafc8991a955f37ffa Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/vboot/vboot_logic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vboot/vboot_logic.c b/src/vboot/vboot_logic.c index 41896e1..57d83a0 100644 --- a/src/vboot/vboot_logic.c +++ b/src/vboot/vboot_logic.c @@ -119,8 +119,8 @@ static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) int is_resume; /* - * Chrome EC is the only support for vboot_save_hash()/vboot_retrieve_hash(), if Chrome EC - * is not enabled then return. + * Chrome EC is the only support for vboot_save_hash() & + * vboot_retrieve_hash(), if Chrome EC is not enabled then return. */ if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) return 0;

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Patch set updated for coreboot: mainboard/intel/kblrvp: Add Chrome EC switch
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17248 -gerrit commit a7c14bf9666d916a49f379138e40b753940fa734 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 14:05:35 2016 +0530 mainboard/intel/kblrvp: Add Chrome EC switch Add Chrome EC switch to enable building with/without Chrome EC. Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/acpi/ec.asl | 3 +- src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 ++ src/mainboard/intel/kblrvp/chromeos.c | 41 +++++++++++++++++---------- 3 files changed, 30 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index 2203e2f..7d7ff2f 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -22,6 +22,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE - +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> +#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 1b8fe43..5d2b307 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -16,6 +16,7 @@ #include "../gpio.h" +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (LID0) @@ -34,6 +35,7 @@ Scope (\_SB) Name (_HID, EisaId ("PNP0C0C")) } } +#endif /* * LPC Trusted Platform Module diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index a9704da..fc1bcd2 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -40,8 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -49,8 +47,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - /* Read lid switch state from the EC. */ - return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + + /* Lid always open */ + return 1; } int get_developer_mode_switch(void) @@ -61,31 +63,40 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check for dedicated recovery switch first. */ - if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & + EC_SWITCH_DEDICATED_RECOVERY) return 1; - /* Otherwise check if the EC has posted the keyboard recovery event. */ - return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + /* Otherwise check if the EC has posted the keyboard recovery + * event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + } + + return 0; } int clear_recovery_mode_switch(void) { - /* Clear keyboard recovery event. */ - return google_chromeec_clear_events_b( - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + + return 0; } int get_write_protect_state(void) { - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); + /* No write protect */ + return 0; } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void)

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Patch merged into coreboot/master: vboot: Disable vboot verification when Chrome EC disabled
by gerrit＠coreboot.org 07 Nov '16

07 Nov '16

the following patch was just integrated into master: commit 3d44d69f93693b44758465244d7e58770fc4918c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:51:14 2016 +0530 vboot: Disable vboot verification when Chrome EC disabled When Chrome EC is disabled, vboot hash is not available during S3 resume Hence disable vboot verification when Chrome EC is not available. Change-Id: I665f5f0e2e53da7b735de30443d323572d8a1a9c Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17246 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17246 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl
by gerrit＠coreboot.org 07 Nov '16

07 Nov '16

the following patch was just integrated into master: commit 8d353afe08f01f0864b30848ac70f81e43e1de17 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:42:30 2016 +0530 soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl Avoid use of Local0 variable in TEVT acpi method. If mainboard doesn't expose any thermal sensor, then warning is generated for variable Local0 not been used. Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17245 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17245 for details. -gerrit

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Patch set updated for coreboot: soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl
by Naresh Solanki 07 Nov '16

07 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17245 -gerrit commit 1c15da3cb978c010a8e0bc93f8bfc9fa0b19c94e Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Sun Nov 6 12:42:30 2016 +0530 soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.asl Avoid use of Local0 variable in TEVT acpi method. If mainboard doesn't expose any thermal sensor, then warning is generated for variable Local0 not been used. Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/acpi/dptf/thermal.asl | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 97484e5..d9bd9c0 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -17,25 +17,24 @@ /* Thermal Threshold Event Handler */ Method (TEVT, 1, NotSerialized) { - Store (ToInteger (Arg0), Local0) #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR0_SENSOR_ID)) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR1_SENSOR_ID)) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR2_SENSOR_ID)) { Notify (^TSR2, 0x90) } #endif #ifdef DPTF_TSR3_SENSOR_ID - If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) { + If (LEqual (ToInteger (Arg0), DPTF_TSR3_SENSOR_ID)) { Notify (^TSR3, 0x90) } #endif

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coreboot-gerrit November 2016