the following patch was just integrated into master:
commit bc6a3890499a7459d0592a872334a09d0514d78b
Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Date: Tue Oct 18 11:15:22 2016 +0530
intel/kunimitsu: Update DPTF settings
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for Kunimitsu board.
BUG=None
BRANCH=None
TEST=Built and booted on Kunimitsu boards. Verified these
updated DPTF settings with different workloads.
Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Reviewed-on: https://chromium-review.googlesource.com/350223
Reviewed-on: https://review.coreboot.org/17069
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17069 for details.
-gerrit
the following patch was just integrated into master:
commit 94f50dee63965a48ee70f80204076845cdc58d1d
Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Date: Tue Oct 18 11:07:39 2016 +0530
google/lars: Update DPTF settings
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for lars boards.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on lars DVT boards. Verified these
updated DPTF settings with different workloads.
Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Reviewed-on: https://chromium-review.googlesource.com/338877
Reviewed-on: https://review.coreboot.org/17068
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17068 for details.
-gerrit
the following patch was just integrated into master:
commit bc41ddd44eec93700d8aeffad1c9fc4b19cea9d8
Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Date: Tue Oct 18 10:57:58 2016 +0530
soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control
This patch updates below info,
[1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not
being used. Hence, removing unnecessary defines.
[2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0
external thermal sensor. These trip points are being used by _ACx
methods to control the fan speed on Skylake-U fan based Lars and
Kunimitsu platforms.
[3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip
points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to
control the fan speed as per the CPU temperature trip points.
[4] Newly added _ACx methods for thermal sensor TSR0 in this patch
has nothing to do with DPTF_CPU_ACTIVE_AC*.
We can control fan speed using various different thermal sensors.
In this patch, we have added new _ACx methods for TSR0 thermal sensor.
We run the fan at different speeds to cool down the system at different
TSR0 temperatures.
Similarly, we considered CPU sensor temperature values and ran the fan
at different speeds to cool down the system.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on kunimitsu and lars EVT boards.
Verified these _ACx methods with _ART table on these boards
with different workloads.
Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332368
Reviewed-on: https://review.coreboot.org/17067
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17067 for details.
-gerrit
the following patch was just integrated into master:
commit a87170b166aa20405be629c22fe6d54cc315e8e5
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Nov 3 10:43:14 2016 -0700
lpss_i2c: Increase transaction timeout
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17213
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17213 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17213
-gerrit
commit 5e32de883fa3b3d7d2c74a4516aececcbea715a8
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Nov 3 10:43:14 2016 -0700
lpss_i2c: Increase transaction timeout
When doing long transcations on an I2C bus at standard speed we saw
that long transactions could go over the 4ms limit while waiting for
it to complete on the bus.
Increase this so we can use standard speed for testing and debug in
firmware. (as there is no way to force standard speed in the kernel)
BUG=chrome-os-partner:58666
TEST=boot eve board with cr50 TPM and I2C bus at 100khz
Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/common/lpss_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c
index 0174792..58d44b8 100644
--- a/src/soc/intel/common/lpss_i2c.c
+++ b/src/soc/intel/common/lpss_i2c.c
@@ -73,8 +73,8 @@ struct lpss_i2c_regs {
uint32_t comp_type;
} __attribute__((packed));
-/* Use a ~4ms timeout for various operations */
-#define LPSS_I2C_TIMEOUT_US 4000
+/* Use a ~10ms timeout for various operations */
+#define LPSS_I2C_TIMEOUT_US 10000
/* High and low times in different speed modes (in ns) */
enum {
the following patch was just integrated into master:
commit 2f3736e7aceb289d51a54679747d65eb09c1e0f1
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Nov 3 10:33:43 2016 -0700
soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading
When reading+clearing a GPE for use as an interrupt we need to
re-read the status register and keep setting the clear bit until
it actually reads back clear. Also add a 1ms timeout in case the
status never clears.
This is needed if a device sends a longer interrupt pulse and it
is still asserted when the "ISR" goes to clear the status.
BUG=chrome-os-partner:59299
TEST=test cr50 TPM with 20us pulse to ensure it can successfully
communicate with the TPM and does not get confused due to seeing
interrupts that it should not.
Change-Id: I384f484a1728038d3a355586146deee089b22dd9
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17212
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17212 for details.
-gerrit
the following patch was just integrated into master:
commit ed4fa099d9583f33130eae97827e63d41d203ff9
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Nov 1 15:03:13 2016 -0700
drivers/i2c/tpm/cr50: Increase IRQ timeout
Increase the IRQ timeout to prevent issues if there is a delay
in the TPM responding to a command. Split the no-IRQ case out
so it doesn't suffer unnecessarily.
BUG=chrome-os-partner:59191
TEST=suspend/resume testing on eve board
Change-Id: I1ea7859bc7a056a450b2b0ee32153ae43ee8699f
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/17204
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/17204 for details.
-gerrit
the following patch was just integrated into master:
commit a84fa908e2f8c25b21cb0017ff6bc80ee2d22ff3
Author: Marc Jones <marcj303(a)gmail.com>
Date: Tue Sep 20 20:33:42 2016 -0600
southbridge/amd: Update Kconfig and makefiles for 00670F00
Add Stoney specific code subtree and fix Makefles and Kconfig files.
Author: Charles Marslett <charles(a)scarlettechnologies.com>
Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
(cherry picked from commit c3a469d11e4676b3b63d11a30955113291d00ec8)
Change-Id: Ic4d97a3745f7fc5a637ae6da17a9009b9757136e
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17217
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17217 for details.
-gerrit
the following patch was just integrated into master:
commit 6580408a7e0a19c68f9705884c1bcaf4638cc914
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Mon Oct 31 14:17:46 2016 -0400
amd/pi/hudson: Move audio to northbridge
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00)
locate the HD audio controller on the northbridge root complex at 9.2
instead of the FCH. This duplicates the existing ASL into the northbridge
directories and reports the correct address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438)
Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17216
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/17216 for details.
-gerrit