coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: TPM: Add TPM driver files to romstage
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17270 -gerrit commit ccc14eba93415e44172efeafec8c3dab66d99eb9 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:33:46 2016 -0800 TPM: Add TPM driver files to romstage This driver is needed for reading and updating TPM space for recovery MRC data hash in romstage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles successfully for reef. Change-Id: I8edb7af13285a7a192e3d55fc6a11cfe12654bf9 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/lib/Makefile.inc | 12 ++++++++++++ src/vboot/Makefile.inc | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 67f8364..513c62a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -52,10 +52,22 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ifeq ($(MOCK_TPM),1) libverstage-y += mocked_tlcl.c + +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +romstage-y += mocked_tlcl.c +endif # CONFIG_SEPARATE_VERSTAGE + else libverstage-$(CONFIG_TPM) += tlcl.c libverstage-$(CONFIG_TPM2) += tpm2_marshaling.c libverstage-$(CONFIG_TPM2) += tpm2_tlcl.c + +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +romstage-$(CONFIG_TPM) += tlcl.c +romstage-$(CONFIG_TPM2) += tpm2_marshaling.c +romstage-$(CONFIG_TPM2) += tpm2_tlcl.c +endif # CONFIG_SEPARATE_VERSTAGE + endif verstage-$(CONFIG_GENERIC_UDELAY) += timer.c diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index 82b4ac2..2e75d45 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -67,8 +67,14 @@ verstage-y += common.c verstage-y += verstage.c ifeq (${CONFIG_VBOOT_MOCK_SECDATA},y) libverstage-y += secdata_mock.c +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +romstage-y += secdata_mock.c +endif else libverstage-y += secdata_tpm.c +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +romstage-y += secdata_tpm.c +endif endif romstage-y += vboot_handoff.c common.c

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Patch set updated for coreboot: vboot: Add vboot library to romstage
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17271 -gerrit commit 6bc51afabcef3d011cfa29479f136dc2d7068067 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:47:11 2016 -0800 vboot: Add vboot library to romstage This library is needed for calculating sha-256 of recovery mrc data in romstage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles succesfully for reef. Change-Id: Ie257208c7b3ad07d00e4eb777debf19c42a2fc0c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/vboot/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index 2e75d45..9b91c35 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -111,6 +111,7 @@ $(VB2_LIB): $(obj)/config.h libverstage-srcs += $(VB2_LIB) ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +romstage-srcs += $(VB2_LIB) cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage

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New patch to review for coreboot: mainboard/google/reef: Select MRC recovery hash space in TPM
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17275 -gerrit commit 871b2cb4edd9c35b32c94817b730fb7532319f42 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:59:48 2016 -0800 mainboard/google/reef: Select MRC recovery hash space in TPM BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified use/update of MRC cache hash on reef. Change-Id: Ic7024101b5b9a6f805b44f2ea1b165a1ecbb4676 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index bb7a531..6ebdbe5 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -34,6 +34,7 @@ config DRIVER_TPM_I2C_IRQ config CHROMEOS select LID_SWITCH if BASEBOARD_REEF_LAPTOP select HAS_RECOVERY_MRC_CACHE + select VBOOT_HAS_REC_MRC_SPACE config DRIVERS_I2C_DA7219 default y

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New patch to review for coreboot: drivers/intel: Add support for recovery MRC space in TPM
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17274 -gerrit commit 0f4af46af57bf8f173f9576b07cf698578eb4d3e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:57:48 2016 -0800 drivers/intel: Add support for recovery MRC space in TPM This space is read/updated only in recovery mode. 1. During read phase, verify if the hash of MRC data read from RECOVERY_MRC_CACHE matches the hash stored in TPM. 2. During update phase, calculate hash of training data returned by MRC and save it in TPM. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified MRC data hash comparison and update operation on reef. Change-Id: Ifcbbf1bd22033767625ec55b659e05fa7a7afc16 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/intel/fsp2_0/memory_init.c | 106 +++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 3ea1897..240adb1 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -11,6 +11,8 @@ * (at your option) any later version. */ +#include <antirollback.h> +#include <arch/early_variables.h> #include <arch/io.h> #include <arch/cpu.h> #include <arch/symbols.h> @@ -28,7 +30,60 @@ #include <string.h> #include <symbols.h> #include <timestamp.h> +#include <tpm_lite/tlcl.h> #include <vboot/vboot_common.h> +#include <vb2_api.h> + +static uint8_t tpm_init_done CAR_GLOBAL; + +static int mrc_cache_tpm_init(void) +{ + uint8_t done = car_get_var(tpm_init_done); + + if (done) + return 0; + + if (tlcl_lib_init() != VB2_SUCCESS) + return -1; + + car_set_var(tpm_init_done, 1); + return 0; +} + +static void mrc_cache_update_tpm_hash(const uint8_t *data, size_t size) +{ + uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; + + /* We do not store normal mode data hash in TPM. */ + if (!vboot_recovery_mode_enabled()) + return; + + /* Bail out early if no mrc hash space is supported in TPM. */ + if (!IS_ENABLED(CONFIG_VBOOT_HAS_REC_MRC_SPACE)) + return; + + /* Initialize TPM driver. */ + if (mrc_cache_tpm_init()) { + printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); + return; + } + + /* Calculate hash of data generated by MRC. */ + if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, + sizeof(data_hash))) { + printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); + memset(data_hash, 0, sizeof(data_hash)); + } + + /* Write hash of data to TPM space. */ + if (antirollback_write_space_rec_mrc(data_hash, sizeof(data_hash)) + != TPM_SUCCESS) { + printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n"); + return; + } + + printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n"); +} static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { @@ -53,6 +108,8 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) if (mrc_cache_stash_data_with_version(mrc_data, mrc_data_size, fsp_version) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); + + mrc_cache_update_tpm_hash(mrc_data, mrc_data_size); } static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -110,6 +167,52 @@ static const char *mrc_cache_get_region_name(void) return RECOVERY_MRC_CACHE; } +static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size) +{ + uint8_t data_hash[VB2_SHA256_DIGEST_SIZE]; + uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE]; + + /* We do not store normal mode data hash in TPM. */ + if (!vboot_recovery_mode_enabled()) + return 1; + + /* + * If hash data storage in TPM is not supported, accept the data from + * RECOVERY_MRC_CACHE. + */ + if (!IS_ENABLED(CONFIG_VBOOT_HAS_REC_MRC_SPACE)) + return 1; + + /* Calculate hash of data read from RECOVERY_MRC_CACHE. */ + if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash, + sizeof(data_hash))) { + printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n"); + return 0; + } + + /* Initialize TPM driver. */ + if (mrc_cache_tpm_init()) { + printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n"); + return 0; + } + + /* Read hash of MRC data saved in TPM. */ + if (antirollback_read_space_rec_mrc(tpm_hash, sizeof(tpm_hash)) + != TPM_SUCCESS) { + printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n"); + return 0; + } + + if (memcmp(tpm_hash, data_hash, sizeof(tpm_hash))) { + printk(BIOS_ERR, "MRC: Hash comparison failed.\n"); + return 0; + } + + printk(BIOS_INFO, "MRC: Hash comparison successful. " + "Using data from RECOVERY_MRC_CACHE\n"); + return 1; +} + static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, uint32_t fsp_version) { @@ -126,6 +229,9 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, if (mrc_cache_get_current_from_region(&mrc_cache, fsp_version, name)) return; + if (!mrc_cache_verify_tpm_hash(mrc_cache->data, mrc_cache->size)) + return; + /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; arch_upd->BootMode = s3wake ?

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New patch to review for coreboot: vboot: Add support for recovery MRC data hash space in TPM
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17273 -gerrit commit 8ac73235d339e44d83caaa23333f6f577bab9f92 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:54:42 2016 -0800 vboot: Add support for recovery MRC data hash space in TPM 1. Add a new index for recovery MRC hash space in TPM - 0x100b 2. Add helper functions to read/write/lock recovery MRC space in TPM 3. Add Kconfig option that can be selected by mainboards that want to define this space. 4. Lock this new space while jumping from RO to RW. BUG=chrome-os-partner:59355 BRANCH=None TEST=Verified use of recovery MRC space on reef. Change-Id: I1cacd54f0a896d0f2af32d4b7c9ae581a918f9bb Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/include/antirollback.h | 9 +++++ src/vboot/Kconfig | 8 ++++ src/vboot/secdata_tpm.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++ src/vboot/vboot_logic.c | 9 +++++ 4 files changed, 120 insertions(+) diff --git a/src/include/antirollback.h b/src/include/antirollback.h index b8ba909..8d84b8e 100644 --- a/src/include/antirollback.h +++ b/src/include/antirollback.h @@ -21,6 +21,8 @@ enum vb2_pcr_digest; * want to use 0x1009 for something else. */ #define BACKUP_NV_INDEX 0x1009 #define FWMP_NV_INDEX 0x100a +#define REC_MRC_NV_INDEX 0x100b +#define REC_MRC_NV_SIZE VB2_SHA256_DIGEST_SIZE /* Structure definitions for TPM spaces */ @@ -46,6 +48,13 @@ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx); */ uint32_t antirollback_lock_space_firmware(void); +/* Read recovery MRC hash data from TPM. */ +uint32_t antirollback_read_space_rec_mrc(uint8_t *data, uint32_t size); +/* Write new hash data to recovery MRC space in TPM. */ +uint32_t antirollback_write_space_rec_mrc(const uint8_t *data, uint32_t size); +/* Lock down recovery MRC hash space in TPM. */ +uint32_t antirollback_lock_space_rec_mrc(void); + /****************************************************************************/ /* diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig index f3df7c5..07d827a 100644 --- a/src/vboot/Kconfig +++ b/src/vboot/Kconfig @@ -134,6 +134,14 @@ config VBOOT_OPROM_MATTERS it works functionally the same for other platforms that can skip their native display initialization code instead. +config VBOOT_HAS_REC_MRC_SPACE + bool + default n + depends on VBOOT + help + Set this option to indicate to vboot that recovery MRC data hash space + is present in TPM. + config VBOOT bool "Verify firmware with vboot." default n diff --git a/src/vboot/secdata_tpm.c b/src/vboot/secdata_tpm.c index b1f3197..fe36c6a 100644 --- a/src/vboot/secdata_tpm.c +++ b/src/vboot/secdata_tpm.c @@ -72,6 +72,13 @@ static uint32_t read_space_firmware(struct vb2_context *ctx) return TPM_E_CORRUPTED_STATE; } +static uint32_t read_space_rec_mrc(uint8_t *data) +{ + RETURN_ON_FAILURE(tlcl_read(REC_MRC_NV_INDEX, data, + REC_MRC_NV_SIZE)); + return TPM_SUCCESS; +} + static uint32_t write_secdata(uint32_t index, const uint8_t *secdata, uint32_t len) @@ -117,6 +124,8 @@ static const uint8_t secdata_kernel[] = { 0xE8, }; +static const uint8_t rec_mrc_data[REC_MRC_NV_SIZE] = { }; + #if IS_ENABLED(CONFIG_TPM2) /* Nothing special in the TPM2 path yet. */ @@ -143,11 +152,21 @@ static uint32_t set_kernel_space(const void *kernel_blob) return TPM_SUCCESS; } +static uint32_t set_rec_mrc_space(const uint8_t *data) +{ + if (!IS_ENABLED(CONFIG_VBOOT_HAS_REC_MRC_SPACE)) + return TPM_SUCCESS; + RETURN_ON_FAILURE(tlcl_define_space(REC_MRC_NV_INDEX, REC_MRC_NV_SIZE)); + RETURN_ON_FAILURE(safe_write(REC_MRC_NV_INDEX, data, REC_MRC_NV_SIZE)); + return TPM_SUCCESS; +} + static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { RETURN_ON_FAILURE(tlcl_force_clear()); RETURN_ON_FAILURE(set_firmware_space(ctx->secdata)); RETURN_ON_FAILURE(set_kernel_space(secdata_kernel)); + RETURN_ON_FAILURE(set_rec_mrc_space(rec_mrc_data)); return TPM_SUCCESS; } @@ -163,6 +182,14 @@ uint32_t antirollback_lock_space_firmware(void) return tlcl_lock_nv_write(FIRMWARE_NV_INDEX); } +uint32_t antirollback_lock_space_rec_mrc(void) +{ + if (!IS_ENABLED(CONFIG_VBOOT_HAS_REC_MRC_SPACE)) + return TPM_SUCCESS; + + return tlcl_lock_nv_write(REC_MRC_NV_INDEX); +} + #else uint32_t tpm_clear_and_reenable(void) @@ -210,6 +237,21 @@ static uint32_t safe_define_space(uint32_t index, uint32_t perm, uint32_t size) } } +static uin32_t set_rec_mrc_space(const uint8_t *data) +{ + if (!IS_ENABLED(CONFIG_VBOOT_HAS_REC_MRC_SPACE)) + return TPM_SUCCESS; + + RETURN_ON_FAILURE(safe_define_space(REC_MRC_NV_INDEX, + TPM_NV_PER_GLOBALLOCK | + TPM_NV_PER_PPWRITE, + REC_MRC_NV_SIZE)); + RETURN_ON_FAILURE(write_secdata(REC_MRC_NV_INDEX, data, + REC_MRC_NV_SIZE)); + + return TPM_SUCCESS; +} + static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { TPM_PERMANENT_FLAGS pflags; @@ -262,6 +304,10 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) RETURN_ON_FAILURE(write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE)); + + /* Define and set rec mrc space */ + set_rec_mrc_space(rec_mrc_data); + return TPM_SUCCESS; } @@ -269,6 +315,15 @@ uint32_t antirollback_lock_space_firmware(void) { return tlcl_set_global_lock(); } + +uint32_t antirollback_lock_space_rec_mrc(void) +{ + /* + * Nothing needs to be done here, since global lock is already set while + * locking firmware space. + */ + return TPM_SUCCESS; +} #endif uint32_t factory_initialize_tpm(struct vb2_context *ctx) @@ -430,3 +485,42 @@ uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) { return write_secdata(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE); } + +uint32_t antirollback_read_space_rec_mrc(uint8_t *data, uint32_t size) +{ + if (size != REC_MRC_NV_SIZE) { + VBDEBUG("TPM: Incorrect buffer size for rec MRC hash. " + "(Expected=0x%x Actual=0x%x).\n", REC_MRC_NV_SIZE, + size); + return TPM_E_READ_FAILURE; + } + return read_space_rec_mrc(data); +} + +uint32_t antirollback_write_space_rec_mrc(const uint8_t *data, uint32_t size) +{ + uint8_t mrc_hash[REC_MRC_NV_SIZE]; + uint32_t rv; + + if (size != REC_MRC_NV_SIZE) { + VBDEBUG("TPM: Incorrect buffer size for rec MRC hash. " + "(Expected=0x%x Actual=0x%x).\n", REC_MRC_NV_SIZE, + size); + return TPM_E_WRITE_FAILURE; + } + + rv = read_space_rec_mrc(mrc_hash); + if (rv == TPM_E_BADINDEX) { + /* + * If space is not defined already for recovery mrc hash, define + * new space. + */ + VBDEBUG("TPM: Initializing recovery MRC hash space.\n"); + return set_rec_mrc_space(data); + } + + if (rv != TPM_SUCCESS) + return rv; + + return write_secdata(REC_MRC_NV_INDEX, data, size); +} diff --git a/src/vboot/vboot_logic.c b/src/vboot/vboot_logic.c index 41896e1..57b7c10 100644 --- a/src/vboot/vboot_logic.c +++ b/src/vboot/vboot_logic.c @@ -416,6 +416,15 @@ void verstage_main(void) vboot_reboot(); } + /* Lock rec mrc space if available. */ + rv = antirollback_lock_space_rec_mrc(); + if (rv) { + printk(BIOS_INFO, "Failed to lock rec MRC space (%x)\n", rv); + vb2api_fail(&ctx, VB2_RECOVERY_RO_TPM_L_ERROR, 0); + save_if_needed(&ctx); + vboot_reboot(); + } + printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B'); vb2_set_selected_region(region_device_region(&fw_main)); timestamp_add_now(TS_END_VBOOT);

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New patch to review for coreboot: antirollback: Sync TPM space indices with vboot library
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17272 -gerrit commit 523cbd38bb49618967251d7fa01e3608d7083e49 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:50:12 2016 -0800 antirollback: Sync TPM space indices with vboot library BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles successfully for reef. Change-Id: I27f2e10556214598d479e4a84e8949465e7da7d6 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/include/antirollback.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/antirollback.h b/src/include/antirollback.h index 889ba9a..b8ba909 100644 --- a/src/include/antirollback.h +++ b/src/include/antirollback.h @@ -19,6 +19,8 @@ enum vb2_pcr_digest; #define KERNEL_NV_INDEX 0x1008 /* 0x1009 used to be used as a backup space. Think of conflicts if you * want to use 0x1009 for something else. */ +#define BACKUP_NV_INDEX 0x1009 +#define FWMP_NV_INDEX 0x100a /* Structure definitions for TPM spaces */

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New patch to review for coreboot: vboot: Add vboot library to romstage and ramstage
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17271 -gerrit commit 789f3ee5581c39c4af885af84d2130326e3049c9 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:47:11 2016 -0800 vboot: Add vboot library to romstage and ramstage This library is needed for calculating sha-256 of recovery mrc data in romstage and ramstage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles succesfully for reef. Change-Id: Ie257208c7b3ad07d00e4eb777debf19c42a2fc0c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/vboot/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index 3734245..36c7ed9 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -107,6 +107,8 @@ $(VB2_LIB): $(obj)/config.h fwlib20 libverstage-srcs += $(VB2_LIB) +romstage-srcs += $(VB2_LIB) +ramstage-srcs += $(VB2_LIB) ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage

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New patch to review for coreboot: TPM: Add TPM driver files to romstage and ramstage
by Furquan Shaikh 08 Nov '16

08 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17270 -gerrit commit 8df8340daa607e43c34c81ecfccc2fcd402554de Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 7 23:33:46 2016 -0800 TPM: Add TPM driver files to romstage and ramstage This driver is needed for reading and updating TPM space for recovery MRC data hash in romstage and ramstage. BUG=chrome-os-partner:59355 BRANCH=None TEST=Compiles successfully for reef. Change-Id: I8edb7af13285a7a192e3d55fc6a11cfe12654bf9 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/lib/Makefile.inc | 10 ++++++++++ src/vboot/Makefile.inc | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 67f8364..5b17add 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -52,10 +52,20 @@ verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ifeq ($(MOCK_TPM),1) libverstage-y += mocked_tlcl.c +romstage-y += mocked_tlcl.c +ramstage-y += mocked_tlcl.c else libverstage-$(CONFIG_TPM) += tlcl.c libverstage-$(CONFIG_TPM2) += tpm2_marshaling.c libverstage-$(CONFIG_TPM2) += tpm2_tlcl.c + +romstage-$(CONFIG_TPM) += tlcl.c +romstage-$(CONFIG_TPM2) += tpm2_marshaling.c +romstage-$(CONFIG_TPM2) += tpm2_tlcl.c + +ramstage-$(CONFIG_TPM) += tlcl.c +ramstage-$(CONFIG_TPM2) += tpm2_marshaling.c +ramstage-$(CONFIG_TPM2) += tpm2_tlcl.c endif verstage-$(CONFIG_GENERIC_UDELAY) += timer.c diff --git a/src/vboot/Makefile.inc b/src/vboot/Makefile.inc index 82b4ac2..3734245 100644 --- a/src/vboot/Makefile.inc +++ b/src/vboot/Makefile.inc @@ -67,8 +67,12 @@ verstage-y += common.c verstage-y += verstage.c ifeq (${CONFIG_VBOOT_MOCK_SECDATA},y) libverstage-y += secdata_mock.c +romstage-y += secdata_mock.c +ramstage-y += secdata_mock.c else libverstage-y += secdata_tpm.c +romstage-y += secdata_tpm.c +ramstage-y += secdata_tpm.c endif romstage-y += vboot_handoff.c common.c

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Patch set updated for coreboot: i2c/wacom_ts: Update WACOM touchscreen ACPI _HID
by Kevin Chiu 08 Nov '16

08 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17257 -gerrit commit 497868e6bf742c7b387056d8f9528c5d1f887850 Author: Janice Li <janice.li(a)quantatw.com> Date: Mon Nov 7 17:49:44 2016 +0800 i2c/wacom_ts: Update WACOM touchscreen ACPI _HID The WCOM50C1 was assigned to the combination with AUO LCD. Changes to 'WCOMNTN2' which is assigned for Pyro with all LCD combinations. BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li(a)quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 --- src/drivers/i2c/wacom_ts/chip.h | 1 + src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h index b59f630..3c748d5 100644 --- a/src/drivers/i2c/wacom_ts/chip.h +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -19,6 +19,7 @@ #include <drivers/i2c/generic/chip.h> #define WCOM50C1_HID "WCOM50C1" +#define WCOMNTN2_HID "WCOMNTN2" #define PNP0C50_CID "PNP0C50" #define WCOM_TS_DESC "WCOM Touchscreen" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index a0ba584..eb2f133 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -133,7 +133,7 @@ chip soc/intel/apollolake device pci 16.3 on chip drivers/i2c/wacom_ts register "generic" = "{ - .hid = WCOM50C1_HID, + .hid = WCOMNTN2_HID, .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_EDGE_LOW(GPIO_21_IRQ),

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Patch set updated for coreboot: i2c/wacom_ts: Update WACOM touchscreen ACPI _HID
by Kevin Chiu 08 Nov '16

08 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17257 -gerrit commit 3a739da1cb0d8e80f9c0e96f58c35e1050e2d434 Author: Janice Li <janice.li(a)quantatw.com> Date: Mon Nov 7 17:49:44 2016 +0800 i2c/wacom_ts: Update WACOM touchscreen ACPI _HID The WCOM50C1 was assigned to the combination with AUO LCD. Changes to 'WCOMNTN2' which is assigned for Pyro with all LCD combinations. BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li(a)quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 --- src/drivers/i2c/wacom_ts/chip.h | 1 + src/drivers/i2c/wacom_ts/ts.c | 1 + src/mainboard/google/reef/variants/pyro/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h index b59f630..268d212 100644 --- a/src/drivers/i2c/wacom_ts/chip.h +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -23,6 +23,7 @@ #define WCOM_TS_DESC "WCOM Touchscreen" struct drivers_i2c_wacom_ts_config { + const char *hid; /* ACPI _HID (required) */ struct drivers_i2c_generic_config generic; uint8_t hid_desc_reg_offset; }; diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c index ebc8883..96d4853 100644 --- a/src/drivers/i2c/wacom_ts/ts.c +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -21,6 +21,7 @@ static void i2c_wacom_ts_fill_dsm(struct device *dev) { struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + config->generic.hid = config->hid; struct dsm_i2c_hid_config dsm_config = { .hid_desc_reg_offset = config->hid_desc_reg_offset, }; diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index a0ba584..50107ce 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -132,8 +132,8 @@ chip soc/intel/apollolake end # - I2C 2 device pci 16.3 on chip drivers/i2c/wacom_ts + register "hid" = ""WCOMNTN2""; register "generic" = "{ - .hid = WCOM50C1_HID, .cid = PNP0C50_CID, .desc = WCOM_TS_DESC, .irq = IRQ_EDGE_LOW(GPIO_21_IRQ),

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coreboot-gerrit November 2016