coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: spi: Add a way to show SPI transfer speed for reads
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16701 -gerrit commit 3a91a3a676a9e71064ae33bcaf0fefd5917aa1ba Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 15:03:02 2016 -0600 spi: Add a way to show SPI transfer speed for reads SPI read speed directly impacts boot time and we do quite a lot of reading. Add a way to easily find out the speed of SPI flash reads within coreboot. Write speed is less important since there are very few writes and they are small. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages: read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82cb93f6be47efce3b0a3843bab89d2381baef89 Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376944 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/spi/cbfs_spi.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index 1895b9d..46e7346 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -23,14 +23,44 @@ #include <spi_flash.h> #include <symbols.h> #include <cbmem.h> +#include <timer.h> static struct spi_flash *spi_flash_info; +/* + * Set this to 1 to debug SPI speed, 0 to disable it + * The format is: + * + * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps + * + * The important number is the last one. It should roughly match your SPI + * clock. If it doesn't, your driver might need a little tuning. + */ +#define SPI_SPEED_DEBUG 0 + static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { + struct stopwatch sw; + bool show = SPI_SPEED_DEBUG && size >= 4 * KiB; + + if (show) + stopwatch_init(&sw); if (spi_flash_info->read(spi_flash_info, offset, size, b)) return -1; + if (show) { + long usecs; + + usecs = stopwatch_duration_usecs(&sw); + u64 speed; /* KiB/s */ + int bps; /* Bits per second */ + + speed = (u64)size * 1000 / usecs; + bps = speed * 8; + + printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", + offset, size, usecs, speed, bps / 1000, bps % 1000); + } return size; }

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Patch set updated for coreboot: google/gru: pass apio number to arm-trust-firmware
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16720 -gerrit commit a5d31e4d705cffb35ba9fb66e0198b0bb8c94a71 Author: Lin Huang <hl(a)rock-chips.com> Date: Tue Aug 30 15:34:42 2016 -0700 google/gru: pass apio number to arm-trust-firmware for save power consumption, some gpio2 ~ gpio4 need to set to input and pull none mode. It depend on these gpio should shut down there power supply, so pass apio number to ATF, to decide which gpio need to config. BRANCH=None BUG=chrome-os-partner:56423 TEST=run suspend_stress_test on kevin board Change-Id: Id57fe8f622ae3f9c2bc7e58be89518b2b846cd37 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c42082d1ca9a6baa735821382d3e83c1f8dc9ad Original-Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/378475 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 902228b..8b9f595 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,23 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_apio_suspend(void) +{ + static struct bl31_apio_param param_apio = { + .h = { + .type = PARAM_SUSPEND_APIO, + }, + .apio = { + .apio1 = 1, + .apio2 = 1, + .apio3 = 1, + .apio4 = 1, + .apio5 = 1, + }, + }; + register_bl31_param(&param_apio.h); +} + static void register_gpio_suspend(void) { /* @@ -227,6 +244,7 @@ static void mainboard_init(device_t dev) register_reset_to_bl31(); register_poweroff_to_bl31(); register_gpio_suspend(); + register_apio_suspend(); } static void enable_backlight_booster(void)

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Patch set updated for coreboot: google/gru: set W2W_DIFFCS_DLY to 5
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16721 -gerrit commit 116966a01c3638628445b3519f346260b8edb1df Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 17:05:43 2016 +0800 google/gru: set W2W_DIFFCS_DLY to 5 It will enable PHY_PER_CS_TRAINING when DDR DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time,there should be more cycles to switch delay line. So need increase W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index c877158..5330141 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x05050502, /* DENALI_CTL_215_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */ 0x02050202, /* DENALI_CTL_217_DATA */ - 0x02010202, /* DENALI_CTL_218_DATA */ - 0x00010202, /* DENALI_CTL_219_DATA */ + 0x02050202, /* DENALI_CTL_218_DATA */ + 0x00050202, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x02010200, /* DENALI_CTL_221_DATA */ 0x00010201, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 591924d..4b73cb0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x08080803, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */ - 0x02010303, /* DENALI_CTL_218_DATA */ - 0x00010203, /* DENALI_CTL_219_DATA */ + 0x02050303, /* DENALI_CTL_218_DATA */ + 0x00050203, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020400, /* DENALI_CTL_221_DATA */ 0x00020401, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index b738644..3056e55 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 362489b..3947881 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -278,9 +278,9 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02010103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_217_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x06030600, /* DENALI_CTL_221_DATA */ 0x00030603, /* DENALI_CTL_222_DATA */

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Patch set updated for coreboot: rockchip/rk3399: dram: improve dram stability when run high frequency
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16722 -gerrit commit e2d4588220d85dd61f0a6812d81e5bbfba93992a Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 18:19:24 2016 +0800 rockchip/rk3399: dram: improve dram stability when run high frequency there are two modify in the driver: 1. correctly set speeds base on DDR frequency. Controls the speeds in the predriver circuits to reduce power. SPEED[1:0] 2'b00:less than 800Mbps(400MHz) 2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz) 2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz) 2b11 : 3200Mbps and greater 2. config the number of cycles phy clock pll wait time after locking base on ddr config file. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2 Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387428 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9211895..1021c6b 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -322,6 +322,7 @@ static void phy_io_config(u32 channel, u32 mode_sel = 0; u32 reg_value; u32 drv_value, odt_value; + u32 speed; /* vref setting */ if (sdram_params->dramtype == LPDDR4) { @@ -436,22 +437,33 @@ static void phy_io_config(u32 channel, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + + /* speed setting */ + if (sdram_params->ddr_freq < 400*MHz) + speed = 0x0; + else if (sdram_params->ddr_freq < 800*MHz) + speed = 0x1; + else if (sdram_params->ddr_freq < 1200*MHz) + speed = 0x2; + else + speed = 0x3; + /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21); + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); } static void pctl_cfg(u32 channel, @@ -477,9 +489,10 @@ static void pctl_cfg(u32 channel, /* rank count need to set for init */ set_memory_map(channel, sdram_params); - write32(&denali_phy[910], 0x6400); - write32(&denali_phy[911], 0x01221102); - write32(&denali_phy[912], 0x0); + write32(&denali_phy[910], sdram_params->phy_regs.denali_phy[910]); + write32(&denali_phy[911], sdram_params->phy_regs.denali_phy[911]); + write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); + pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);

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New patch to review for coreboot: northbridge/amd/amdfam10: Remove commented code
by HAOUAS Elyes 04 Oct '16

04 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16880 -gerrit commit 3195af0b3af06f0637a4b4480a41f810c7cf0135 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Oct 4 20:58:03 2016 +0200 northbridge/amd/amdfam10: Remove commented code Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdfam10/amdfam10.h | 74 ----------------------- src/northbridge/amd/amdfam10/debug.c | 2 - src/northbridge/amd/amdfam10/get_pci1234.c | 2 - src/northbridge/amd/amdfam10/ht_config.c | 11 ---- src/northbridge/amd/amdfam10/northbridge.c | 2 - src/northbridge/amd/amdfam10/raminit.h | 26 -------- src/northbridge/amd/amdfam10/setup_resource_map.c | 48 +-------------- 7 files changed, 3 insertions(+), 162 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 2ef22ee..7ba91d7 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -211,14 +211,6 @@ #define DTH_TRFC_127_5_1G 2 #define DTH_TRFC_195_2G 3 #define DTH_TRFC_327_5_4G 4 -#if 0 -//DDR3 -#define DTH_TRFC_90_512M 1 -#define DTH_TRFC_110_5_1G 2 -#define DTH_TRFC_160_2G 3 -#define DTH_TRFC_300_4G 4 -#define DTH_TRFC_UNDEFINED_8G 5 -#endif #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ @@ -353,12 +345,6 @@ #define DODCC_ProcOdt_300_OHMS 0 #define DODCC_ProcOdt_150_OHMS 1 #define DODCC_ProcOdt_75_OHMS 2 -#if 0 -//DDR3 -#define DODCC_ProcOdt_240_OHMS 0 -#define DODCC_ProcOdt_120_OHMS 1 -#define DODCC_ProcOdt_60_OHMS 2 -#endif /* for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs @@ -527,66 +513,6 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 /* 04.06.2006 19:12 */ -#if 0 -//DDR3 -#define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A -#define DDWTC_WrDqsFineDlyByte0_SHIFT 0 -#define DDWTC_WrDqsFineDlyByte0_MASK 0x1f -#define DDWTC_WrDqsGrossDlyByte0_SHIFT 5 -#define DDWTC_WrDqsGrossDlyByte0_MASK 0x3 -#define DDWTC_WrDqsFineDlyByte1_SHIFT 8 -#define DDWTC_WrDqsGrossDlyByte1_SHIFT 13 -#define DDWTC_WrDqsFineDlyByte2_SHIFT 16 -#define DDWTC_WrDqsGrossDlyByte2_SHIFT 21 -#define DDWTC_WrDqsFineDlyByte3_SHIFT 24 -#define DDWTC_WrDqsGrossDlyByte3_SHIFT 29 - -#define DRAM_DQS_WRTIE_TIME_CTRL_0_1 0x31 //DIMM0 Channel A -#define DDWTC_WrDqsFineDlyByte4_SHIFT 0 -#define DDWTC_WrDqsGrossDlyByte4_SHIFT 5 -#define DDWTC_WrDqsFineDlyByte5_SHIFT 8 -#define DDWTC_WrDqsGrossDlyByte5_SHIFT 13 -#define DDWTC_WrDqsFineDlyByte6_SHIFT 16 -#define DDWTC_WrDqsGrossDlyByte6_SHIFT 21 -#define DDWTC_WrDqsFineDlyByte7_SHIFT 24 -#define DDWTC_WrDqsGrossDlyByte7_SHIFT 29 - -#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_0 0x32 -#define DDWTCE_WrDqsChkFineDlyByte0_SHIFT 0 -#define DDWTCE_WrDqsChkGrossDlyByte0_SHIFT 5 - -#define DRAM_DQS_WRITE_TIME_CTRL_0_2 0x40 //DIMM0 Channel B -#define DDWTC_WrDqsFineDlyByte8_SHIFT 0 -#define DDWTC_WrDqsGrossDlyByte8_SHIFT 5 -#define DDWTC_WrDqsFineDlyByte9_SHIFT 8 -#define DDWTC_WrDqsGrossDlyByte9_SHIFT 13 -#define DDWTC_WrDqsFineDlyByte10_SHIFT 16 -#define DDWTC_WrDqsGrossDlyByte10_SHIFT 21 -#define DDWTC_WrDqsFineDlyByte11_SHIFT 24 -#define DDWTC_WrDqsGrossDlyByte11_SHIFT 29 - -#define DRAM_DQS_WRTIE_TIME_CTRL_0_3 0x41 //DIMM0 Channel B -#define DDWTC_WrDqsFineDlyByte12_SHIFT 0 -#define DDWTC_WrDqsGrossDlyByte12_SHIFT 5 -#define DDWTC_WrDqsFineDlyByte13_SHIFT 8 -#define DDWTC_WrDqsGrossDlyByte13_SHIFT 13 -#define DDWTC_WrDqsFineDlyByte14_SHIFT 16 -#define DDWTC_WrDqsGrossDlyByte14_SHIFT 21 -#define DDWTC_WrDqsFineDlyByte15_SHIFT 24 -#define DDWTC_WrDqsGrossDlyByte15_SHIFT 29 - -#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_0_1 0x42 -#define DDWTCE_WrDqsChkFineDlyByte1_SHIFT 0 -#define DDWTCE_WrDqsChkGrossDlyByte1_SHIFT 5 - -#define DRAM_DQS_WRITE_TIME_CTRL_1_0 0x33 //DIMM1 Channel A -#define DRAM_DQS_WRTIE_TIME_CTRL_1_1 0x34 //DIMM1 Channel A -#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_0 0x35 -#define DRAM_DQS_WRITE_TIME_CTRL_1_2 0x43 //DIMM1 Channel B -#define DRAM_DQS_WRTIE_TIME_CTRL_1_3 0x44 //DIMM1 Channel B -#define DRAM_DQS_WRITE_TIMING_CTRL_ECC_1_1 0x45 -#endif - #define DRAM_PHASE_RECOVERY_CTRL_0 0x50 #define DPRC_PhRecFineDlyByte0_SHIFT 0 #define DDWTC_PhRecFineDlyByte0_MASK 0x1f diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 327a0e6..f9c7266 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -134,8 +134,6 @@ static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) { dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz -// dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2 -// dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3 } static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index 11f1589..08698dc 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -71,12 +71,10 @@ void get_pci1234(void) //here we need to set hcdn //1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set //2. so at the same time we need update hsdn with hcdn_reg here -// printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num); for (j = 0; j < sysconf.ht_c_num; j++) { u32 dwordx; dwordx = sysconf.ht_c_conf_bus[j]; -// printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]); dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits if ((dwordx & 0x7fd) == dword) { //SBLINK sysconf.pci1234[0] = dwordx; diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 9259147..916111c 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -202,17 +202,6 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 40f5704..5634441 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -978,8 +978,6 @@ static void amdfam10_domain_set_resources(device_t dev) } -// printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - /* split the region to accommodate pci memory space */ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { if (basek <= mmio_basek) { diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index bfc0da0..c1ef29e 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -16,29 +16,6 @@ #ifndef RAMINIT_H #define RAMINIT_H -#if 0 -#if CONFIG_DIMM_SUPPORT == 0x0110 -//FBDIMM REG -/* each channel can have 8 fbdimm */ -#define DIMM_SOCKETS 8 -struct mem_controller { - u32 node_id; - pci_devfn_t f0, f1, f2, f3, f4, f5; - /* channelA, channelB belong to DCT0, - * channelC, channelD belong to DCT1 - * Each DCT may support one ganged logical FBDIMM ---> 128 bit - * or a single unganged channel --->64 bit - * a DCT can not support 2 unganged channels - * two DCTs can not be ganged - */ - u8 spd_switch_addr; - u8 spd_addr[DIMM_SOCKETS*4]; -}; - -#endif -#endif - -//#if (CONFIG_DIMM_SUPPORT & 0x00ff) == 0x0004 //DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F * 2 for socket M2/M3 @@ -63,7 +40,4 @@ struct mem_controller { u8 spd_addr[DIMM_SOCKETS*2]; }; -//#endif - - #endif diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 7e71cf7..3d67bdd 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -20,7 +20,6 @@ static void setup_resource_map(const u32 *register_values, u32 max) { u32 i; -// printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { pci_devfn_t dev; @@ -34,14 +33,13 @@ static void setup_resource_map(const u32 *register_values, u32 max) reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } -// printk(BIOS_DEBUG, "done.\n"); } void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base) { u32 i; -// printk(BIOS_DEBUG, "setting up resource map offset...."); + for (i = 0; i < max; i += 3) { pci_devfn_t dev; u32 where; @@ -53,7 +51,6 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p reg |= register_values[i+2] + offset_io_base; pci_write_config32(dev, where, reg); } -// printk(BIOS_DEBUG, "done.\n"); } #define RES_PCI_IO 0x10 @@ -124,9 +121,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset printk(BIOS_SPEW, "NOW: %08x\n", reg); } break; - } // switch - - + } } if (IS_ENABLED(RES_DEBUG)) @@ -180,46 +175,9 @@ void setup_resource_map_x(const u32 *register_values, u32 max) outl(reg, where); } break; - } // switch - - + } } if (IS_ENABLED(RES_DEBUG)) printk(BIOS_DEBUG, "done.\n"); } - -#if 0 -static void setup_iob_resource_map(const u32 *register_values, u32 max) -{ - u32 i; - - for (i = 0; i < max; i += 3) { - u32 where; - u32 reg; - - where = register_values[i]; - reg = inb(where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - outb(reg, where); - } -} - -static void setup_io_resource_map(const u32 *register_values, u32 max) -{ - u32 i; - - for (i = 0; i < max; i += 3) { - u32 where; - u32 reg; - - where = register_values[i]; - reg = inl(where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - - outl(reg, where); - } -} -#endif

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Patch merged into coreboot/master: google/gru: Ensure correct pull resistors for special-function pins
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 7feb86b26b2b72d21098a90bff0843d8533a7493 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 2 11:25:56 2016 -0700 google/gru: Ensure correct pull resistors for special-function pins Several of the special function pins we're using in firmware have a pre-assigned pull-up or pull-down on power-on reset. We don't want those to interfere with any of the signaling we're trying to do on those pins, so this patch disables them. Also do some house-cleaning to group the bootblock code better, and change the setup code for all SPI and I2C buses to first initialize the controller and then mux the pins... I assume this might be a little safer (in case the controller peripheral has some pins in a weird state before it gets fully initialized, we don't want to mux it through too early). BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560 Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382532 Reviewed-on: https://review.coreboot.org/16711 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16711 for details. -gerrit

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Patch merged into coreboot/master: rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit f7d519c1c7ba3da1b2e459fa1a82805c70544956 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 2 23:48:10 2016 -0700 rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ This patch fixes a typo in the clock initialization code that caused the PERILP1_PCLK_HZ constant to be ignored and the clock to always run at the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our previous tests and validation with this bug, we should probably increase the value of the constant (that had not actually been used) to the value that we had been incorrectly using instead (which also makes effective SPI read times faster). BRANCH=None BUG=chrome-os-partner:56556 TEST=Booted Kevin. Change-Id: Ibeb08f5fe5e984a74e3f57e60c62d4bfb644b6ca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 06e605a5fcb9bdf13a3d301112380633b892fd4e Original-Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381031 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-on: https://review.coreboot.org/16703 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16703 for details. -gerrit

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Patch merged into coreboot/master: gru: Increase SPI speed to 33MHz
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 584dbf2e3a1ac0638ad02c954c2d220278adfbf1 Author: Simon Glass <sjg(a)chromium.org> Date: Sun Sep 4 18:56:46 2016 -0600 gru: Increase SPI speed to 33MHz Increase the SPI bus speed to speed up boot time. The maximum supported speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed, given the clock parents. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. Total time spent on reading from SPI reduces from 185ms to 141ms. Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381313 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16708 for details. -gerrit

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Patch merged into coreboot/master: rockchip: Remove pulls for gpio_output(), clean up code
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 2768a119ce08893975f3bf6788fd31c7071e7c9a Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Sep 1 22:55:58 2016 -0700 rockchip: Remove pulls for gpio_output(), clean up code Output GPIOs should never have a pull-up or pull-down resistor attached since they're actively driven. Since some GPIOs get initialized with a pull at power-on reset, we should explicitly overwrite that setting. Most other platforms do this on gpio_output, but Rockchip hadn't yet. Also, shuffle some code around to make things cleaner and allow for easier code reuse. BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I1425d074ea1e90f4484e1e84a8002b057192c5f7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: df5b236bfd58b172435043c1cb792b917a4ec4ab Original-Change-Id: I044266d71ef8bd0518316ff72d829d1ca1e30f35 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382531 Original-Reviewed-by: Simon Glass <sjg(a)google.com> Reviewed-on: https://review.coreboot.org/16710 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16710 for details. -gerrit

1 0

Patch merged into coreboot/master: google/gru: Init the PWM pinmux after setting up the PWM
by gerrit＠coreboot.org 04 Oct '16

04 Oct '16

the following patch was just integrated into master: commit 1eb69b4a64b0bd96aa57b0e793667dd36d10ff17 Author: Douglas Anderson <dianders(a)chromium.org> Date: Tue Sep 6 13:51:03 2016 -0700 google/gru: Init the PWM pinmux after setting up the PWM If we setup the PWM _after_ the pinmux then there's a period of time when we're driving the PWM incorrectly. Let's setup the regulator and _then_ configure the pinmux. This fixes no known bugs, but it is more correct and probably makes the signals look better at bootup. BRANCH=None BUG=None TEST=scope Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1 Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381592 Original-Reviewed-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16700 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16700 for details. -gerrit

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coreboot-gerrit October 2016