coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/gru: Shrink RW_ELOG region to 4KB
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16715 -gerrit commit 9bfb2e2e90e6041e729c346444a866917f44fde2 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Sep 12 16:02:33 2016 -0700 google/gru: Shrink RW_ELOG region to 4KB Since there's currently a limitation in coreboot's code that prevents more than 4KB to be used by the eventlog anyway, this patch shrinks the available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove prudent later if we ever resolve that limitation, so that tools can rely on the area in the FMAP being the same as the area actually used by the read-only firmware code on these boards. BRANCH=gru BUG=chrome-os-partner:55593 TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a reboot loop to exhaust eventlog space, confirmed that the shrink code kicks in as expected before reaching 4KB. Change-Id: I3c55d836c72486665a19783fe98ce9e0df174b6d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 05efb82ca00703fd92d925ebf717738e37295c18 Original-Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384585 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Simon Glass <sjg(a)google.com> --- src/mainboard/google/gru/chromeos.fmd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index bf30ddf..2200fa7 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,7 +20,8 @@ FLASH@0x0 0x800000 { FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG@0x5d8000 0x8000 + RW_ELOG@0x5d8000 0x1000 + RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 }

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Patch set updated for coreboot: rockchip/rk3399: Move TTB to the end of SRAM
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16714 -gerrit commit a0913f92cae36513a0ee138f01fb0ef73c373934 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Sep 12 15:46:02 2016 -0700 rockchip/rk3399: Move TTB to the end of SRAM We found that we may want to load some components of BL31 on the RK3399 into SRAM. As usual, these components may not overlap any coreboot regions still in use at that time, as is already statically checked by the check-ramstage-overlaps rule in Makefile.inc. On RK3399, the only such regions are TTB and STACK. This patch moves the TTB region back to the end of SRAM (right before STACK), so that a large contiguous region of SRAM before that remains usable for BL31. BRANCH=gru BUG=None TEST=Booted Kevin. Change-Id: I1689d0280d79bad805fea5fc3759c2ae3ba24915 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1d4c6c6f6cc0efe97d6962a81e309a1c040d1def Original-Change-Id: I37c94f2460ef63aec4526caabe58f35ae851bab0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384635 Original-Reviewed-by: Simon Glass <sjg(a)google.com> --- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 54cfbe1..ef8d29d 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -34,9 +34,9 @@ SECTIONS TIMESTAMP(0xFF8C1C00, 1K) BOOTBLOCK(0xFF8C2004, 36K - 4) PRERAM_CBFS_CACHE(0xFF8CB000, 4K) - TTB(0xFF8CC000, 24K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D2000, 92K) - VBOOT2_WORK(0XFF8E9000, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 92K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 24K) STACK(0xFF8EC000, 16K) SRAM_END(0xFF8F0000) }

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Patch set updated for coreboot: rockchip/rk3399: lower kevin board sdram frequency to 800MHz
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16709 -gerrit commit df903c20bbc5669a0500f8cd11bc37203a0365c0 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 11:16:26 2016 -0700 rockchip/rk3399: lower kevin board sdram frequency to 800MHz We found some boards are not stable when sdram is run at 933Mhz. Before we can fix it, we need to lower the sdram frequency to 800MHz. In this patch we modify the DQS delay from 0x280 to 0x260 and extend the DQS window. BRANCH=None BUG=chrome-os-partner:56940 TEST=Booted Kevin. Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382724 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 4 +-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 40 +++++++++++----------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 2ececdf..1235eff 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -56,10 +56,8 @@ static enum dram_speeds get_sdram_index(void) return dram_200MHz; case 3: return dram_666MHz_NO_ODT; - case 4: - return dram_800MHz; default: - return dram_933MHz; + return dram_800MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 3a937bf..034e9d8 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02800280, /* DENALI_PHY_59_DATA */ - 0x02800280, /* DENALI_PHY_60_DATA */ - 0x02800280, /* DENALI_PHY_61_DATA */ - 0x02800280, /* DENALI_PHY_62_DATA */ - 0x00000280, /* DENALI_PHY_63_DATA */ + 0x02600260, /* DENALI_PHY_59_DATA */ + 0x02600260, /* DENALI_PHY_60_DATA */ + 0x02600260, /* DENALI_PHY_61_DATA */ + 0x02600260, /* DENALI_PHY_62_DATA */ + 0x00000260, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02800280, /* DENALI_PHY_187_DATA */ - 0x02800280, /* DENALI_PHY_188_DATA */ - 0x02800280, /* DENALI_PHY_189_DATA */ - 0x02800280, /* DENALI_PHY_190_DATA */ - 0x00000280, /* DENALI_PHY_191_DATA */ + 0x02600260, /* DENALI_PHY_187_DATA */ + 0x02600260, /* DENALI_PHY_188_DATA */ + 0x02600260, /* DENALI_PHY_189_DATA */ + 0x02600260, /* DENALI_PHY_190_DATA */ + 0x00000260, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02800280, /* DENALI_PHY_315_DATA */ - 0x02800280, /* DENALI_PHY_316_DATA */ - 0x02800280, /* DENALI_PHY_317_DATA */ - 0x02800280, /* DENALI_PHY_318_DATA */ - 0x00000280, /* DENALI_PHY_319_DATA */ + 0x02600260, /* DENALI_PHY_315_DATA */ + 0x02600260, /* DENALI_PHY_316_DATA */ + 0x02600260, /* DENALI_PHY_317_DATA */ + 0x02600260, /* DENALI_PHY_318_DATA */ + 0x00000260, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02800280, /* DENALI_PHY_443_DATA */ - 0x02800280, /* DENALI_PHY_444_DATA */ - 0x02800280, /* DENALI_PHY_445_DATA */ - 0x02800280, /* DENALI_PHY_446_DATA */ - 0x00000280, /* DENALI_PHY_447_DATA */ + 0x02600260, /* DENALI_PHY_443_DATA */ + 0x02600260, /* DENALI_PHY_444_DATA */ + 0x02600260, /* DENALI_PHY_445_DATA */ + 0x02600260, /* DENALI_PHY_446_DATA */ + 0x00000260, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */

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Patch set updated for coreboot: rockchip: Correct and standardize clock divisor range assertions
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16704 -gerrit commit 30a0fb788ff48224bde615d8945504d197a639bd Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Sep 6 14:09:16 2016 -0700 rockchip: Correct and standardize clock divisor range assertions Some of the asserts for valid clock divisor ranges were off by one. This patch corrects them and writes them all in a consistent way. BRANCH=None BUG=None TEST=Booted Kevin. Change-Id: I81749408a40822100797f1734f3b88987d12d8d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e09cdfde26700496aaa1fc41489f63a355e8a89d Original-Change-Id: I429edb99e2d5ff2302d9750e6569b3d21f5686fa Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381574 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 20 ++++++++++---------- src/soc/rockchip/rk3399/clock.c | 32 ++++++++++++++++---------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index bb5b846..74151e8 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -272,14 +272,14 @@ void rkclk_init(void) * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; - assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; assert((hclk_div + 1) * PD_BUS_HCLK_HZ == - PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); + PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2)); pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; assert((pclk_div + 1) * PD_BUS_PCLK_HZ == - PD_BUS_ACLK_HZ && pclk_div < 0x7); + PD_BUS_ACLK_HZ && pclk_div <= 0x7); write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, @@ -295,15 +295,15 @@ void rkclk_init(void) * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; - assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == - PERI_ACLK_HZ && (hclk_div < 0x4)); + PERI_ACLK_HZ && (hclk_div <= 0x2)); pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == - PERI_ACLK_HZ && (pclk_div < 0x4)); + PERI_ACLK_HZ && (pclk_div <= 0x3)); write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, @@ -429,7 +429,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) { int src_clk_div = GPLL_HZ / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == GPLL_HZ)); switch (bus) { /*select gpll as spi src clk, and set div*/ case 0: @@ -487,7 +487,7 @@ void rkclk_configure_crypto(unsigned int hz) { u32 div = PD_BUS_ACLK_HZ / hz; - assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ)); + assert((div - 1 <= 3) && (div * hz == PD_BUS_ACLK_HZ)); assert(hz <= 150*MHz); /* Suggested max in TRM. */ write32(&cru_ptr->cru_clksel_con[26], RK_CLRSETBITS(0x3 << 6, (div - 1) << 6)); @@ -499,7 +499,7 @@ void rkclk_configure_tsadc(unsigned int hz) u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/ div = src_clk / hz; - assert((div - 1 < 64) && (div * hz == 32 * KHz)); + assert((div - 1 <= 63) && (div * hz == 32 * KHz)); write32(&cru_ptr->cru_clksel_con[2], RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } @@ -604,7 +604,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) /* vop aclk source clk: cpll */ div = CPLL_HZ / aclk_hz; - assert((div - 1 < 64) && (div * aclk_hz == CPLL_HZ)); + assert((div - 1 <= 63) && (div * aclk_hz == CPLL_HZ)); switch (vop_id) { case 0: diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ded0a94..b9de844 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -402,7 +402,7 @@ void rkclk_init(void) /* configure pmu pclk */ pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; - assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); + assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); write32(&pmucru_ptr->pmucru_clksel[0], RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT, pclk_div << PMU_PCLK_DIV_CON_SHIFT)); @@ -420,15 +420,15 @@ void rkclk_init(void) /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; - assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; assert((hclk_div + 1) * PERIHP_HCLK_HZ == - PERIHP_ACLK_HZ && (hclk_div < 0x4)); + PERIHP_ACLK_HZ && (hclk_div <= 0x3)); pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; assert((pclk_div + 1) * PERIHP_PCLK_HZ == - PERIHP_ACLK_HZ && (pclk_div < 0x7)); + PERIHP_ACLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[14], RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK << @@ -447,15 +447,15 @@ void rkclk_init(void) /* configure perilp0 aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; - assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; assert((hclk_div + 1) * PERILP0_HCLK_HZ == - PERILP0_ACLK_HZ && (hclk_div < 0x4)); + PERILP0_ACLK_HZ && (hclk_div <= 0x3)); pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; assert((pclk_div + 1) * PERILP0_PCLK_HZ == - PERILP0_ACLK_HZ && (pclk_div < 0x7)); + PERILP0_ACLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[23], RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK << @@ -475,11 +475,11 @@ void rkclk_init(void) /* perilp1 hclk select gpll as source */ hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; assert((hclk_div + 1) * PERILP1_HCLK_HZ == - GPLL_HZ && (hclk_div < 0x1f)); + GPLL_HZ && (hclk_div <= 0x1f)); pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; assert((pclk_div + 1) * PERILP1_PCLK_HZ == - PERILP1_HCLK_HZ && (pclk_div < 0x7)); + PERILP1_HCLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[25], RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << @@ -590,7 +590,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */ pll = (bus == 3) ? PPLL_HZ : GPLL_HZ; src_clk_div = pll / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); switch (bus) { case 0: @@ -646,7 +646,7 @@ static void rkclk_configure_i2c(unsigned int bus, unsigned int hz) /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ pll = (bus == 0 || bus == 4 || bus == 8) ? PPLL_HZ : GPLL_HZ; src_clk_div = pll / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); switch (bus) { case 0: @@ -749,7 +749,7 @@ void rkclk_configure_saradc(unsigned int hz) /* saradc src clk from 24MHz */ src_clk_div = 24 * MHz / hz; - assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz)); + assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz)); write32(&cru_ptr->clksel_con[26], RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << @@ -765,7 +765,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) /* vop aclk source clk: cpll */ div = CPLL_HZ / aclk_hz; - assert((div - 1 < 32) && (div * aclk_hz == CPLL_HZ)); + assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ)); write32(reg_addr, RK_CLRSETBITS( ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT | @@ -803,7 +803,7 @@ void rkclk_configure_tsadc(unsigned int hz) /* use 24M as src clock */ src_clk_div = OSC_HZ / hz; - assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ)); + assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ)); write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | @@ -820,7 +820,7 @@ void rkclk_configure_emmc(void) /* Select aclk_emmc source from GPLL */ src_clk_div = GPLL_HZ / aclk_emmc; - assert((src_clk_div - 1 < 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); + assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); write32(&cru_ptr->clksel_con[21], RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK << @@ -832,7 +832,7 @@ void rkclk_configure_emmc(void) /* Select clk_emmc source from GPLL too */ src_clk_div = GPLL_HZ / clk_emmc; - assert((src_clk_div - 1 < 127) && (src_clk_div * clk_emmc == GPLL_HZ)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ)); write32(&cru_ptr->clksel_con[22], RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT |

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Patch set updated for coreboot: rockchip: spi: Set rxd sample delay when using high speed
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16707 -gerrit commit adfa1207a03347ce1cace84eabbe700367a7ac5e Author: Simon Glass <sjg(a)chromium.org> Date: Mon Sep 5 11:04:50 2016 -0600 rockchip: spi: Set rxd sample delay when using high speed At higher SPI bus speeds the SPI RX value is not available in time for sampling at the normal time. Add a delay to ensure that we read the correct data. The value of 40ns is chosen arbitrarily. In my testing I can use a sample delay of 1 even at 24MHz. But since it is not necessary, I have left that case alone. It kicks in at 25MHz and up. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see no change at current speed Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7 Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381311 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/include/soc/spi.h | 3 +++ src/soc/rockchip/common/spi.c | 18 ++++++++++++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index dcaa471..0e1847c 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -199,4 +199,7 @@ check_member(rockchip_spi, rxdr, 0x800); void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); +/* Set the receive sample delay in nanoseconds */ +void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns); + #endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H */ diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index f35f915..7dcaaad 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -32,7 +32,7 @@ struct rockchip_spi_slave { }; #define SPI_TIMEOUT_US 1000 -#define SPI_SRCCLK_HZ (99*MHz) +#define SPI_SRCCLK_HZ (198*MHz) #define SPI_FIFO_DEPTH 32 static struct rockchip_spi_slave rockchip_spi_slaves[] = { @@ -152,9 +152,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) /* Byte and Halfword Transform */ ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); - /* Rxd Sample Delay */ - ctrlr0 |= (0 << SPI_RXDSD_OFFSET); - /* Frame Format */ ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); @@ -165,6 +162,19 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) write32(&regs->rxftlr, SPI_FIFO_DEPTH / 2 - 1); } +void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) +{ + assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; + unsigned int rsd; + + /* Rxd Sample Delay */ + rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); + assert(rsd >= 0 && rsd <= 3); + clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, + rsd << SPI_RXDSD_OFFSET); +} + int spi_claim_bus(struct spi_slave *slave) { spi_cs_activate(slave);

1 0

Patch set updated for coreboot: arm64: Use 'payload' format for ATF instead of 'stage'
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16706 -gerrit commit dcb106bdd3fc8aee52f3f5cfecd64a230fc3c619 Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 12:18:38 2016 -0600 arm64: Use 'payload' format for ATF instead of 'stage' Switch the BL31 (ARM Trusted Firmware) format to payload so that it can have multiple independent segments. This also requires disabling the region check since SRAM is currently faulted by that check. This has been tested with Rockchip's pending change: https://chromium-review.googlesource.com/#/c/368592/3 with the patch mentioned on the bug at #13. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is correct though: CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1b440 size 15a75 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000018104800 Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d using LZMA [ 0x18104800, 18137d90, 0x192843e0) <- 00100038 Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650 dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1 Jumping to boot code at 0000000018104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes CBFS: 'VBOOT' located CBFS at [402000:44cc00) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 10ec0 size 8d0c Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26 Loading segment from ROM address 0x0000000000100038 Entry Point 0x0000000000010000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 using LZMA [ 0x00010000, 00035708, 0x00050000) <- 00100054 Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8 dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 using LZMA [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6 dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff Loaded segments INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80 INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364 INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648 NOTICE: BL31: v1.2(debug): NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1189): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x18104800 INFO: SPSR = 0x8 Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376849 Original-Commit-Ready: Simon Glass <sjg(a)google.com> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 +- src/arch/arm64/arm_tf.c | 5 ++--- src/include/program_loading.h | 10 ++++++++-- src/lib/prog_loaders.c | 2 +- src/lib/selfboot.c | 24 ++++++++++++++---------- 5 files changed, 26 insertions(+), 17 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index ece35a6..6e3f080 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -178,7 +178,7 @@ $(BL31): $(obj)/build.h BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 $(BL31_CBFS)-file := $(BL31) -$(BL31_CBFS)-type := stage +$(BL31_CBFS)-type := payload $(BL31_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(BL31_CBFS) diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 1ec87c4..e976e34 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -50,11 +50,10 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) if (prog_locate(&bl31)) die("BL31 not found"); - if (cbfs_prog_stage_load(&bl31)) + bl31_entry = selfload(&bl31, false); + if (!bl31_entry) die("BL31 load failed"); - bl31_entry = prog_entry(&bl31); - SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0); if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) { diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e265b18..3958fda 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -189,7 +189,13 @@ void payload_run(void); /* Mirror the payload to be loaded. */ void mirror_payload(struct prog *payload); -/* Defined in src/lib/selfboot.c */ -void *selfload(struct prog *payload); +/* + * Set check_regions to true to check that the payload targets usable memory. + * With this flag set, if it does not, the load will fail and this function + * will return NULL. + * + * Defined in src/lib/selfboot.c + */ +void *selfload(struct prog *payload, bool check_regions); #endif /* PROGRAM_LOADING_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..c0dcd60 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -161,7 +161,7 @@ void payload_load(void) mirror_payload(payload); /* Pass cbtables to payload if architecture desires it. */ - prog_set_entry(payload, selfload(payload), + prog_set_entry(payload, selfload(payload, true), cbmem_find(CBMEM_ID_CBTABLE)); out: diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 1ce7f94..162a034 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -88,7 +88,8 @@ static void get_bounce_buffer(unsigned long req_size) /* When the ramstage is relocatable there is no need for a bounce * buffer. All payloads should not overlap the ramstage. */ - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) || + !arch_supports_bounce_buffer()) { bounce_buffer = ~0UL; bounce_size = 0; return; @@ -357,15 +358,16 @@ static int payload_targets_usable_ram(struct segment *head) return 1; } -static int load_self_segments( - struct segment *head, - struct prog *payload) +static int load_self_segments(struct segment *head, struct prog *payload, + bool check_regions) { struct segment *ptr; unsigned long bounce_high = lb_end; - if (!payload_targets_usable_ram(head)) - return 0; + if (check_regions) { + if (!payload_targets_usable_ram(head)) + return 0; + } for(ptr = head->next; ptr != head; ptr = ptr->next) { /* @@ -373,8 +375,10 @@ static int load_self_segments( * allocated so that there aren't conflicts with the actual * payload. */ - bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, - LB_MEM_UNUSABLE); + if (check_regions) { + bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, + LB_MEM_UNUSABLE); + } if (!overlaps_coreboot(ptr)) continue; @@ -486,7 +490,7 @@ static int load_self_segments( return 1; } -void *selfload(struct prog *payload) +void *selfload(struct prog *payload, bool check_regions) { uintptr_t entry = 0; struct segment head; @@ -502,7 +506,7 @@ void *selfload(struct prog *payload) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, payload, check_regions)) goto out; printk(BIOS_SPEW, "Loaded segments\n");

1 0

Patch set updated for coreboot: rockchip/rk3399: Move big CPU cluster initialization into ramstage
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16698 -gerrit commit 73cb1fceb5afbc7ca40312df926028cab019b12f Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 29 15:07:58 2016 -0700 rockchip/rk3399: Move big CPU cluster initialization into ramstage This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/mainboard/google/gru/bootblock.c | 2 +- src/soc/rockchip/rk3399/clock.c | 40 +++++++++++++++++------------ src/soc/rockchip/rk3399/include/soc/clock.h | 7 ++++- src/soc/rockchip/rk3399/soc.c | 4 +++ 4 files changed, 34 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 0e916d2..d76ec8b 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -117,7 +117,7 @@ static void speed_up_boot_cpu(void) udelay(200); - rkclk_configure_cpu(APLL_1512_MHZ, false); + rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); } void bootblock_mainboard_init(void) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 9ac1ffe..ded0a94 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -494,26 +494,32 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big) +void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster) { - u32 aclkm_div; - u32 pclk_dbg_div; - u32 atclk_div; - u32 apll_l_hz; - int con_base = is_big ? 2 : 0; - int parent = is_big ? CLK_CORE_PLL_SEL_ABPLL : CLK_CORE_PLL_SEL_ALPLL; - u32 *pll_con = is_big ? &cru_ptr->apll_b_con[0] : - &cru_ptr->apll_l_con[0]; - - apll_l_hz = apll_cfgs[apll_freq]->freq; - - rkclk_set_pll(pll_con, apll_cfgs[apll_freq]); - - aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; + u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz; + int con_base, parent; + u32 *pll_con; + + switch (cluster) { + case CPU_CLUSTER_LITTLE: + con_base = 0; + parent = CLK_CORE_PLL_SEL_ALPLL; + pll_con = &cru_ptr->apll_l_con[0]; + break; + case CPU_CLUSTER_BIG: + default: + con_base = 2; + parent = CLK_CORE_PLL_SEL_ABPLL; + pll_con = &cru_ptr->apll_b_con[0]; + break; + } - pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1; + apll_hz = apll_cfgs[freq]->freq; + rkclk_set_pll(pll_con, apll_cfgs[freq]); - atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1; + aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1; + pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1; + atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1; write32(&cru_ptr->clksel_con[con_base], RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index e04b216..5926051 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -101,9 +101,14 @@ enum apll_frequencies { APLL_600_MHZ, }; +enum cpu_cluster { + CPU_CLUSTER_LITTLE, + CPU_CLUSTER_BIG, +}; + void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); -void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big); +void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_emmc(void); void rkclk_configure_i2s(unsigned int hz); diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 1adf3f6..12c757f 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -18,6 +18,7 @@ #include <cpu/cpu.h> #include <device/device.h> #include <soc/addressmap.h> +#include <soc/clock.h> #include <soc/display.h> #include <stddef.h> #include <stdlib.h> @@ -42,6 +43,9 @@ static void soc_init(device_t dev) _framebuffer_size); else printk(BIOS_INFO, "Display initialization disabled.\n"); + + /* We don't need big CPUs, but bring them up as a courtesy to Linux. */ + rkclk_configure_cpu(APLL_600_MHZ, CPU_CLUSTER_BIG); } static struct device_operations soc_ops = {

1 0

Patch set updated for coreboot: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16699 -gerrit commit a9168662b358747aadc926fa8170b29f29022ac2 Author: Jeffy Chen <jeffy.chen(a)rock-chips.com> Date: Fri Sep 2 18:16:33 2016 +0800 google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_rialto/sdram_configs.c | 2 +- .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc | 77 ++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 42fa582..0e260c3 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -22,7 +22,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc new file mode 100644 index 0000000..df3bb2a --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x0, + .col = 0x0, + .bk = 0x0, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x0, + .cs1_row = 0x0 + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 22, + .odt = 0 +},

1 0

Patch set updated for coreboot: Gale: Fix the orange color to match the UX doc
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16767 -gerrit commit bd9069a64521d69c45df2893683d40d724b26b16 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Thu Sep 22 08:20:16 2016 -0700 Gale: Fix the orange color to match the UX doc UX Doc = go/gale-hw-ui This color wasn't changed earlier as the change wasn't done in the OS also. However, since we cannot change this later in FW (but OS can change anytime), I am making this change after discussing with the UX team. BUG=b:31501528, b:31633562 TEST=Change the device state to 'recovery mode' to observe the new color. BRANCH=none Change-Id: Ia91f14eb77492095cb41a9de0bb9790e72aa4851 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 36a3d8c6eabbc0b23d0a15d5bddc5ed3bdeebe70 Original-Change-Id: I88768b94cf91804a6005e44b1a168e059698ec4b Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388206 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Christopher Book <cbook(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index fb74a1b..0c70e10 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -170,8 +170,8 @@ static const TiLp55231Program blink_wipeout1_program = { static const uint8_t blink_recovery1_text[] = { 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, 0x94, 0x02, 0x9f, 0x80, 0x98, 255, 0x84, 0x62, - 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, - 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x9f, 0x81, 0x98, 100, 0x84, 0x62, 0x9f, 0x82, + 0x98, 10, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, 0xc0, 0x00, 0xc0, 0x00, 0x00,

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Patch set updated for coreboot: i2c/ww_ring: LED changes for Gale EVT3
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16697 -gerrit commit 3d533b491379bf6a6b504a48500bd45238d4804a Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Aug 15 16:18:11 2016 -0700 i2c/ww_ring: LED changes for Gale EVT3 Gale EVT3 has only one LED controller (earlier we had 2). Removing the support for the second controller and also the corresponding microcode. The color values used are the same as onHub (Arkham to be specific). BUG=b:30890905 TEST=Move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the differnet colors. BRANCH=None Change-Id: I853035610ea7ea7c8d29c30d2de13c9e2e786b2b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 593905d2d69daa7482318aa5f5c5cd7cf984043e Original-Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/370821 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 232 ++++++----------------------- src/drivers/i2c/ww_ring/ww_ring_programs.h | 2 +- 2 files changed, 49 insertions(+), 185 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index a35998c..5b0c8a8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -46,36 +46,36 @@ * Solid LED display, the arguments of the set_pwm commands set intensity and * color of the display: -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 1 + set_pwm 0 end .segment program2 mux_map_addr row_green - set_pwm 1 + set_pwm 0 end .segment program3 mux_map_addr row_blue - set_pwm 1 + set_pwm 0 end */ /* RGB set to 000000, resulting in all LEDs off. */ static const uint8_t solid_000000_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 0, 0xC0, 0x00, 0x9F, 0x81, 0x40, 0, 0xC0, 0x00, 0x9F, 0x82, 0x40, 0, 0xC0, 0x00 }; /* Rgb set to 128, resulting in a brightish white color. */ static const uint8_t solid_808080_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 128, 0xC0, 0x00, 0x9F, 0x81, 0x40, 128, 0xC0, 0x00, 0x9F, 0x82, 0x40, 128, 0xC0, 0x00 }; @@ -100,20 +100,10 @@ static const TiLp55231Program solid_000000_program = { * The three internal engines seem to be competing for resources and get out * of sync in seconds if left running asynchronously. * - * When there are two separate controllers, with three engine each, they all - * run away from each other in no time, resulting in some completely chaotic - * LED behavior. - * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential * accesses. But the controllers still neeed to be synchronized. * - * The first controller is loaded and started first, but it sits waiting for - * the trigger from the second controller to actually start the cycle. Once - * both controllers start running, the first controller is the master, sending - * sych triggers to the second one each time the LED is supposed to be turned - * on or off. - * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller * intervals need to be changed, as the second one is in lockstep with the @@ -126,29 +116,26 @@ static const TiLp55231Program solid_000000_program = { */ /* * blink_solid1.src -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 ld ra, 2 # LED on duration - ld rb, 10 # LED off duration + ld rb, 2 # LED off duration mux_map_addr row_red - trigger w{e} loop: - trigger s{e} - ld rc, 98 ; red intensity + ld rc, 180 ; red intensity set_pwm rc mux_map_addr row_green - ld rc, 0 ; green intensity + ld rc, 80 ; green intensity set_pwm rc mux_map_addr row_blue - ld rc, 234 ; blue intensity + ld rc, 0 ; blue intensity set_pwm rc wait1: wait 0.1 branch ra, wait1 - trigger s{e} set_pwm 0 mux_map_addr row_green set_pwm 0 @@ -158,203 +145,82 @@ wait2: wait 0.1 branch rb, wait2 branch 0, loop - -.segment program2 - end - -.segment program3 - end*/ -/* - * blink_solid2.src - -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b - -.segment program1 - ld ra, 98 - ld rb, 0 - ld rc, 234 - trigger s{e} - mux_map_addr row_red -loop: - trigger w{e} - set_pwm ra ; red intensity - mux_map_addr row_green - set_pwm rb ; green intensity - mux_map_addr row_blue - set_pwm rc ; blue intensity -wait1: - wait 0.1 - branch 1, wait1 - trigger w{e} - set_pwm 0 - mux_map_addr row_green - set_pwm 0 - mux_map_addr row_red - set_pwm 0 -wait2: - wait 0.1 - branch 1, wait2 - branch 0, loop - .segment program2 end - .segment program3 end */ static const uint8_t blink_wipeout1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 80, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, -}; - -static const uint8_t blink_wipeout2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 80, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 180, 0x84, 0x62, + 0x9f, 0x81, 0x98, 80, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_wipeout1_program = { blink_wipeout1_text, sizeof(blink_wipeout1_text), 0, - { 3, 27, 28, } -}; -static const TiLp55231Program blink_wipeout2_program = { - blink_wipeout2_text, - sizeof(blink_wipeout2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; static const uint8_t blink_recovery1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 24, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 255, 0x84, 0x62, + 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_recovery1_program = { blink_recovery1_text, sizeof(blink_recovery1_text), 0, - { 3, 27, 28, } -}; -static const uint8_t blink_recovery2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 24, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program blink_recovery2_program = { - blink_recovery2_text, - sizeof(blink_recovery2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; /* * fade_in1.src * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b + row_red: dw 0000000000000001b + row_green: dw 0000000000000010b + row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 0h - trigger w{e} + set_pwm 1h trigger s{2|3} end - .segment program2 mux_map_addr row_green set_pwm 0h - trigger w{1} - ramp 2, 87 + ramp 2, 50 end - .segment program3 mux_map_addr row_blue set_pwm 0h loop3: trigger w{1} - ramp 2, 155 - end -*/ -/* - * fade_in2.src - * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b - - .segment program1 - mux_map_addr row_red - set_pwm 0h - trigger s{e} - trigger s{2|3} - end - - .segment program2 - mux_map_addr row_green - set_pwm 0h - - trigger w{1} - ramp 2, 87 - end - -.segment program3 - mux_map_addr row_blue - set_pwm 0h - loop3: trigger w{1} - ramp 2, 155 + ramp 2, 255 end */ static const uint8_t fade_in1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xf0, 0x00, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9f, 0x80, + 0x40, 0x01, 0xe0, 0x0c, 0xc0, 0x00, 0x9f, 0x81, + 0x40, 0x00, 0xe0, 0x80, 0x46, 0x32, 0xc0, 0x00, + 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x20, 0xff, + 0xc0, 0x00, 0x00, }; static const TiLp55231Program fade_in1_program = { fade_in1_text, sizeof(fade_in1_text), 0, - { 3, 8, 13, } -}; - -static const uint8_t fade_in2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xe0, 0x40, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program fade_in2_program = { - fade_in2_text, - sizeof(fade_in2_text), - 0, - { 3, 8, 13, } + { 3, 7, 12, } }; const WwRingStateProg wwr_state_programs[] = { @@ -362,12 +228,10 @@ const WwRingStateProg wwr_state_programs[] = { * for test purposes the blank screen program is set to blinking, will * be changed soon. */ - {WWR_ALL_OFF, {&solid_000000_program, &solid_000000_program} }, - {WWR_RECOVERY_PUSHED, {&solid_808080_program, &solid_808080_program} }, - {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program, - &blink_wipeout2_program} }, - {WWR_RECOVERY_REQUEST, {&blink_recovery1_program, - &blink_recovery2_program} }, - {WWR_NORMAL_BOOT, {&fade_in1_program, &fade_in2_program} }, + {WWR_ALL_OFF, {&solid_000000_program} }, + {WWR_RECOVERY_PUSHED, {&solid_808080_program} }, + {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program} }, + {WWR_RECOVERY_REQUEST, {&blink_recovery1_program} }, + {WWR_NORMAL_BOOT, {&fade_in1_program} }, {}, /* Empty record to mark the end of the table. */ }; diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 9f4b928..5fb8ebf 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -36,7 +36,7 @@ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ -#define WW_RING_NUM_LED_CONTROLLERS 2 +#define WW_RING_NUM_LED_CONTROLLERS 1 /* * Structure to describe an lp55231 program: pointer to the text of the

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coreboot-gerrit October 2016