coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Revert "soc/intel/apollolake: Add pmc_ipc device support"
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16881 -gerrit commit 79cbe8b3e8fe554356405964dc7747b79af38b5e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Sep 29 19:37:49 2016 -0700 Revert "soc/intel/apollolake: Add pmc_ipc device support" This reverts commit 28821dbb2261267462a7e9b0cc1c23b51af2d3ee. (https://review.coreboot.org/16649) This change causes the kernel to boot really slow. Maybe there is an interrupt storm that prevents the kernel from making any progress. Reverting until the proper kernel dependency is met. BUG=chrome-os-partner:57364 BRANCH=None TEST=Kernels boots to prompt fine on DVT. Change-Id: I1c9913b4476a08303f9dd887b8631601c847dcf7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d7014ee1bb88df7a2d7f6b3dced797fef75b252d Original-Change-Id: I061c0b03b43b516a190b370c04888e73a410fcf1 Original-Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/391233 Original-Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 --------------------------- src/soc/intel/apollolake/acpi/southbridge.asl | 3 -- 2 files changed, 60 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl deleted file mode 100644 index b89bebf..0000000 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/iomap.h> - -#define MAILBOX_DATA 0x7080 -#define MAILBOX_INTF 0x7084 -#define PMIO_LENGTH 0x80 - -Device (IPC1) -{ - Name (_HID, "INT34D2") - Name (_CID, "INT34D2") - Name (_DDN, "Intel(R) IPC1 Controller") - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) - Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) - Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) - IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE + PMIO_LENGTH, - 0x04, PMIO_LENGTH) - Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) - { - PMC_INT - } - }) - - Method (_CRS, 0x0, NotSerialized) - { - CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) - Store (PMC_BAR0, IBAS) - - CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) - Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) - CreateDwordField (^RBUF, ^MINF._BAS, MIBA) - Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) - - CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (PMC_SRAM_BASE_0, SBAS) - - Return (^RBUF) - } -} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f2b09c7..1c10f1a 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -40,9 +40,6 @@ Scope (\_SB) #include "xhci.asl" -/* PMC IPC */ -#include "pmc_ipc.asl" - /* LPC */ #include "lpc.asl"

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Patch set updated for coreboot: rockchip/rk3399: Configure USB3 controller work in USB2 only mode
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16717 -gerrit commit 0bcdfb76da297fa3050ad6ce2f8c6e5f4b1be59a Author: Liangfeng Wu <wulf(a)rock-chips.com> Date: Thu Sep 15 17:16:54 2016 +0800 rockchip/rk3399: Configure USB3 controller work in USB2 only mode During the USB2 only mode, the Type-C PHY will be held in reset and only USB2 part logic of USB3 OTG controller and PHY may be used over the USB2 pins on the Type-C connector to support Low, Full and High-speed USB operation. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot form USB. Change-Id: Ic265c0c91c24f63b2f9c3106eb2bb277a589233b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a37ccc5b6019967483eac6b5a360d67bc3326e93 Original-Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad Original-Signed-off-by: Liangfeng Wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/385837 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/usb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index f638a1e..4c731bd 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -17,6 +17,9 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/soc.h> #include <soc/usb.h> /* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just @@ -86,12 +89,24 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) void reset_usb_otg0(void) { + /* Keep whole USB OTG0 controller in reset, then + * configure controller to work in USB 2.0 only mode. */ + write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5)); + write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); + write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5)); + printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG0\n"); reset_dwc3(rockchip_usb_otg0_dwc3); } void reset_usb_otg1(void) { + /* Keep whole USB OTG1 controller in reset, then + * configure controller to work in USB 2.0 only mode. */ + write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6)); + write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); + write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6)); + printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG1\n"); reset_dwc3(rockchip_usb_otg1_dwc3); }

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Patch set updated for coreboot: rockchip/rk3399: select rank before triggering training
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16768 -gerrit commit f4f6361ff0daa4d74b451d8750abd950de2c87cb Author: Derek Basehore <dbasehore(a)chromium.org> Date: Wed Sep 21 15:43:36 2016 -0700 rockchip/rk3399: select rank before triggering training This selects the rank to train before training is triggered. This is to prevent any race conditions with the hardware. BRANCH=none BUG=chrome-os-partner:56940 TEST=stressapptest -M 1536 -s 1000 Change-Id: I892bace414cf4495619d41bdaea0c4e91c1e29b3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f2dd6f52978a9e54ddd2688eb68fd237aabfe2d Original-Change-Id: I4e7118d8509b59e391d0a254477b5390dfdd43a5 Original-Signed-off-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/387907 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: 云平汤 <typ(a)rock-chips.com> --- src/soc/rockchip/rk3399/sdram.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 1021c6b..42b2574 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -685,15 +685,14 @@ static int data_training(u32 channel, /* ca training(LPDDR4,LPDDR3 support) */ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); - /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[92], (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -726,6 +725,7 @@ static int data_training(u32 channel, /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ @@ -733,7 +733,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -772,6 +771,7 @@ static int data_training(u32 channel, /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); /* @@ -782,7 +782,6 @@ static int data_training(u32 channel, (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -818,6 +817,7 @@ static int data_training(u32 channel, /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ @@ -825,7 +825,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 24), (0x1 << 8) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -850,6 +849,7 @@ static int data_training(u32 channel, /* wdq leveling(LPDDR4 support) */ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 @@ -862,7 +862,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8;

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Patch set updated for coreboot: rockchip: rk3399: improve write leveling flow
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16716 -gerrit commit 92b0a95d65da34e3332fc6015255d579ed671e6e Author: Jianqun Xu <jay.xu(a)rock-chips.com> Date: Sun Sep 11 18:26:42 2016 +0800 rockchip: rk3399: improve write leveling flow To improve sdram 800MHz and 933MHz stability, we need to modify write leveling flow, to get the more proper write leveling value. BUG=chrome-os-partner:56940 BRANCH=none TEST=Boot from kevin on 933MHz, and do stressapptest Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be Original-Signed-off-by: Jianqun Xu <jay.xu(a)rock-chips.com> Original-Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/384292 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 10 +-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 16 ++-- .../sdram-lpddr3-hynix-4GB-666-no-odt.c | 16 ++-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 16 ++-- .../sdram-lpddr3-hynix-4GB-800-no-odt.c | 56 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 56 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 56 ++++++------ src/soc/rockchip/rk3399/sdram.c | 99 ++++++++-------------- 8 files changed, 146 insertions(+), 179 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 1235eff..2aa05a7 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -50,14 +50,10 @@ static enum dram_speeds get_sdram_index(void) if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) switch (id) { - case 0: - case 1: - case 2: - return dram_200MHz; - case 3: - return dram_666MHz_NO_ODT; - default: + case 4: return dram_800MHz; + default: + return dram_933MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index a9ed180..c877158 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00800080, /* DENALI_PHY_77_DATA */ - 0x01900001, /* DENALI_PHY_78_DATA */ + 0x00000001, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00000000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c044208, /* DENALI_PHY_87_DATA */ + 0x07044208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00800080, /* DENALI_PHY_205_DATA */ - 0x01900001, /* DENALI_PHY_206_DATA */ + 0x00000001, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00000000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c044208, /* DENALI_PHY_215_DATA */ + 0x07044208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00800080, /* DENALI_PHY_333_DATA */ - 0x01900001, /* DENALI_PHY_334_DATA */ + 0x00000001, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00000000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c044208, /* DENALI_PHY_343_DATA */ + 0x07044208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00800080, /* DENALI_PHY_461_DATA */ - 0x01900001, /* DENALI_PHY_462_DATA */ + 0x00000001, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00000000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c044208, /* DENALI_PHY_471_DATA */ + 0x07044208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c index ad0e30c..f57ac18 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01c40080, /* DENALI_PHY_77_DATA */ - 0x01900002, /* DENALI_PHY_78_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01c40080, /* DENALI_PHY_205_DATA */ - 0x01900002, /* DENALI_PHY_206_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01c40080, /* DENALI_PHY_333_DATA */ - 0x01900002, /* DENALI_PHY_334_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01c40080, /* DENALI_PHY_461_DATA */ - 0x01900002, /* DENALI_PHY_462_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 7543e10..591924d 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01c40080, /* DENALI_PHY_77_DATA */ - 0x01900002, /* DENALI_PHY_78_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01c40080, /* DENALI_PHY_205_DATA */ - 0x01900002, /* DENALI_PHY_206_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01c40080, /* DENALI_PHY_333_DATA */ - 0x01900002, /* DENALI_PHY_334_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01c40080, /* DENALI_PHY_461_DATA */ - 0x01900002, /* DENALI_PHY_462_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c index fde24c7e..21f7044 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02800280, /* DENALI_PHY_59_DATA */ - 0x02800280, /* DENALI_PHY_60_DATA */ - 0x02800280, /* DENALI_PHY_61_DATA */ - 0x02800280, /* DENALI_PHY_62_DATA */ - 0x00000280, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00b30080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02800280, /* DENALI_PHY_187_DATA */ - 0x02800280, /* DENALI_PHY_188_DATA */ - 0x02800280, /* DENALI_PHY_189_DATA */ - 0x02800280, /* DENALI_PHY_190_DATA */ - 0x00000280, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00b30080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02800280, /* DENALI_PHY_315_DATA */ - 0x02800280, /* DENALI_PHY_316_DATA */ - 0x02800280, /* DENALI_PHY_317_DATA */ - 0x02800280, /* DENALI_PHY_318_DATA */ - 0x00000280, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00b30080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02800280, /* DENALI_PHY_443_DATA */ - 0x02800280, /* DENALI_PHY_444_DATA */ - 0x02800280, /* DENALI_PHY_445_DATA */ - 0x02800280, /* DENALI_PHY_446_DATA */ - 0x00000280, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00b30080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 1544bd0..b738644 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02600260, /* DENALI_PHY_59_DATA */ - 0x02600260, /* DENALI_PHY_60_DATA */ - 0x02600260, /* DENALI_PHY_61_DATA */ - 0x02600260, /* DENALI_PHY_62_DATA */ - 0x00000260, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00b30080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02600260, /* DENALI_PHY_187_DATA */ - 0x02600260, /* DENALI_PHY_188_DATA */ - 0x02600260, /* DENALI_PHY_189_DATA */ - 0x02600260, /* DENALI_PHY_190_DATA */ - 0x00000260, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00b30080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02600260, /* DENALI_PHY_315_DATA */ - 0x02600260, /* DENALI_PHY_316_DATA */ - 0x02600260, /* DENALI_PHY_317_DATA */ - 0x02600260, /* DENALI_PHY_318_DATA */ - 0x00000260, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00b30080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02600260, /* DENALI_PHY_443_DATA */ - 0x02600260, /* DENALI_PHY_444_DATA */ - 0x02600260, /* DENALI_PHY_445_DATA */ - 0x02600260, /* DENALI_PHY_446_DATA */ - 0x00000260, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00b30080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index a4d2007..362489b 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02600260, /* DENALI_PHY_59_DATA */ - 0x02600260, /* DENALI_PHY_60_DATA */ - 0x02600260, /* DENALI_PHY_61_DATA */ - 0x02600260, /* DENALI_PHY_62_DATA */ - 0x00000260, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01a20080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00030000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c064208, /* DENALI_PHY_87_DATA */ + 0x07064208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02600260, /* DENALI_PHY_187_DATA */ - 0x02600260, /* DENALI_PHY_188_DATA */ - 0x02600260, /* DENALI_PHY_189_DATA */ - 0x02600260, /* DENALI_PHY_190_DATA */ - 0x00000260, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01a20080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00030000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c064208, /* DENALI_PHY_215_DATA */ + 0x07064208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02600260, /* DENALI_PHY_315_DATA */ - 0x02600260, /* DENALI_PHY_316_DATA */ - 0x02600260, /* DENALI_PHY_317_DATA */ - 0x02600260, /* DENALI_PHY_318_DATA */ - 0x00000260, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01a20080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00030000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c064208, /* DENALI_PHY_343_DATA */ + 0x07064208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02600260, /* DENALI_PHY_443_DATA */ - 0x02600260, /* DENALI_PHY_444_DATA */ - 0x02600260, /* DENALI_PHY_445_DATA */ - 0x02600260, /* DENALI_PHY_446_DATA */ - 0x00000260, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01a20080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00030000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c064208, /* DENALI_PHY_471_DATA */ + 0x07064208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9aa2952..9211895 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -580,10 +580,9 @@ static void check_write_leveling_value(u32 channel, const struct rk3399_sdram_params *sdram_params) { - u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; + u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; - u32 i, tmp; - u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 i, j; u32 wl_value[2][4]; u32 rank = sdram_params->ch[channel].rank; @@ -602,71 +601,43 @@ static void check_write_leveling_value(u32 channel, wl_value[i][3] = (read32(&denali_phy[447]) >> 16) & 0x3ff; } - for (i = 0; i < 4; i++) { - if (((wl_value[0][i] > 0x1E0) || (wl_value[0][i] < 0x20)) && - ((wl_value[1][i] > 0x1E0) || (wl_value[1][i] < 0x20))) { - switch (i) { - case 0: - setbits_le32(&denali_phy[79], 0x1 << 16); - break; - case 1: - setbits_le32(&denali_phy[207], 0x1 << 16); - break; - case 2: - setbits_le32(&denali_phy[335], 0x1 << 16); - break; - case 3: - setbits_le32(&denali_phy[463], 0x1 << 16); - break; - default: - break; - } - } - } + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 0 << 16); for (i = 0; i < rank; i++) { - - /* FIXME: denali_phy[463] value wrong if miss this delay */ - udelay(100); - - /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); - /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); - - select_per_cs_training_index(channel, i); - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:25 */ - tmp = read32(&denali_pi[174]) >> 8; - - /* - * check status obs, - * if error maybe can not get leveling done - * PHY_40/168/296/424 phy_wrlvl_status_obs_X:0:13 - */ - obs_0 = read32(&denali_phy[40]); - obs_1 = read32(&denali_phy[168]); - obs_2 = read32(&denali_phy[296]); - obs_3 = read32(&denali_phy[424]); - if (((obs_0 >> 12) & 0x1) || - ((obs_1 >> 12) & 0x1) || - ((obs_2 >> 12) & 0x1) || - ((obs_3 >> 12) & 0x1)) - obs_err = 1; - if ((((tmp >> 10) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) - break; - else if ((((tmp >> 4) & 0x1) == 0x1) || - (obs_err == 1)) - printk(BIOS_DEBUG, - "check_write_leveling_value error!!!\n"); + clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24); + for (j = 0; j < 4; j++) { + if (wl_value[i][j] < 0x80) + clrsetbits_le32(&denali_phy[63+j*128], + 0x3ff << 16, + (wl_value[i][j]+0x200) << 16); + else if ((wl_value[i][j] >= 0x80) && + (wl_value[i][j] < 0x100)) + clrsetbits_le32(&denali_phy[78+j*128], + 0x7 << 8, 0x1 << 8); } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); } + + /* CTL_200 ctrlupd_req 1bit offset_8 */ + clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); } static int data_training(u32 channel,

1 0

Patch set updated for coreboot: rockchip/rk3399: Actually remove big CPU initialization from bootblock
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16769 -gerrit commit 60854fe205bbd5b212b92e6fadee74a827664d34 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 23 16:07:42 2016 -0700 rockchip/rk3399: Actually remove big CPU initialization from bootblock CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h(a)gmx.de> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index b9de844..2596853 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -411,13 +411,6 @@ void rkclk_init(void) rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); - /* - * coreboot boot from little core, but it seem if apll_b use defalut - * 24MHz it will take a long time to enable big core, and will cause - * a watchdog crash, so we should do apll_b initialization here - */ - rkclk_configure_cpu(APLL_600_MHZ, true); - /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

1 0

Patch set updated for coreboot: google/gru: pass the gpio power supply enable pin to bl31
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16719 -gerrit commit 47b95f7af4ad47a515050a429eba2dc03f85e809 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Aug 22 17:35:40 2016 -0700 google/gru: pass the gpio power supply enable pin to bl31 we need to disable some regulator when device into suspend, it mean we need to pass some gpio to bl31, and disable these gpios when bl31 run suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpio go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- 3rdparty/arm-trusted-firmware | 2 +- src/mainboard/google/gru/board.h | 3 +++ src/mainboard/google/gru/mainboard.c | 43 ++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index e4f51ee..bfd9251 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit e4f51eee91187e980f5e0e436c65f325fc35c94b +Subproject commit bfd925139fdbc2e87979849907b34843aa326994 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 382c462..7880cca 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -25,6 +25,9 @@ #define GPIO_POWEROFF GPIO(1, A, 6) #define GPIO_RESET GPIO(0, B, 3) #define GPIO_WP GPIO(1, C, 2) +#define GPIO_P15V_EN GPIO(0, B, 2) +#define GPIO_P30V_EN GPIO(0, B, 4) +#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 8359ca4..902228b 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,48 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_gpio_suspend(void) +{ + /* + * these 3 pin to disable gpio2 ~ gpio4 1.5v, 1.8v, 3.3v power supply + * so need to shut down the power supply from high voltage to + * low voltage, and consider register_bl31() appends to the front off + * the list, we should register 1.5v enable pin to 3.3v enable pin + */ + static struct bl31_gpio_param param_p15_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p15_en.gpio.index = GET_GPIO_NUM(GPIO_P15V_EN); + register_bl31_param(&param_p15_en.h); + + static struct bl31_gpio_param param_p18_audio_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p18_audio_en.gpio.index = GET_GPIO_NUM(GPIO_P18V_AUDIO_PWREN); + register_bl31_param(&param_p18_audio_en.h); + + static struct bl31_gpio_param param_p30_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p30_en.gpio.index = GET_GPIO_NUM(GPIO_P30V_EN); + register_bl31_param(&param_p30_en.h); +} + static void register_reset_to_bl31(void) { static struct bl31_gpio_param param_reset = { @@ -184,6 +226,7 @@ static void mainboard_init(device_t dev) setup_usb(); register_reset_to_bl31(); register_poweroff_to_bl31(); + register_gpio_suspend(); } static void enable_backlight_booster(void)

1 0

Patch set updated for coreboot: soc/qualcomm/ipq40xx: Fix GPIO pull up config.
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16770 -gerrit commit a9898374af927fd5a111e1085c9697cce42f97fd Author: Kan Yan <kyan(a)google.com> Date: Thu Sep 22 18:59:18 2016 -0700 soc/qualcomm/ipq40xx: Fix GPIO pull up config. BUG=b:31690391 TEST=Tested with board ID BRANCH=none Change-Id: I9a2b7eec111a79827f72a506942a8ec833ba7e60 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f23e2b6e72491aaafa15774f9bded3e14363abbc Original-Change-Id: I23183db29d7f7dd812e94ab6a1f2f1329c46ac60 Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388778 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj(a)chromium.org> --- src/soc/qualcomm/ipq40xx/include/soc/gpio.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h index 3f9c385..220ea93 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h @@ -48,8 +48,7 @@ /* GPIO TLMM: Pullup/Pulldown */ #define GPIO_NO_PULL 0 #define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 +#define GPIO_PULL_UP 2 /* GPIO TLMM: Drive Strength */ #define GPIO_2MA 0

1 0

Patch set updated for coreboot: i2c/ww_ring: LED changes as per UX team feedback.
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16718 -gerrit commit 74f9fbdf44665bca94a13b9c92117cd7f3cd1c46 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Sep 19 17:43:25 2016 -0700 i2c/ww_ring: LED changes as per UX team feedback. Colors and patterns as defined by the UX team BUG=b:31501528 TEST=Move the device to different states in FW using rec and dev button and verify the colors BRANCH=None Change-Id: I66d41a54590cd3ce4e5202c7cfa890f462fe195e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 703559d5dddaeeb7d435d6cadbb2009a1b7a76c8 Original-Change-Id: I95ab1fa59b483396ff1498a28f1ee98ac08d02d7 Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387258 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Christopher Book <cbook(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 5b0c8a8..fb74a1b 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -125,13 +125,13 @@ row_blue: dw 0000000000000100b ld rb, 2 # LED off duration mux_map_addr row_red loop: - ld rc, 180 ; red intensity + ld rc, 1 ; red intensity set_pwm rc mux_map_addr row_green - ld rc, 80 ; green intensity + ld rc, 50 ; green intensity set_pwm rc mux_map_addr row_blue - ld rc, 0 ; blue intensity + ld rc, 155 ; blue intensity set_pwm rc wait1: wait 0.1 @@ -152,9 +152,9 @@ wait2: */ static const uint8_t blink_wipeout1_text[] = { 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0x98, 180, 0x84, 0x62, - 0x9f, 0x81, 0x98, 80, 0x84, 0x62, 0x9f, 0x82, - 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x94, 0x02, 0x9f, 0x80, 0x98, 1, 0x84, 0x62, + 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, + 0x98, 155, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, 0xc0, 0x00, 0xc0, 0x00, 0x00, @@ -205,7 +205,7 @@ static const TiLp55231Program blink_recovery1_program = { mux_map_addr row_blue set_pwm 0h loop3: trigger w{1} - ramp 2, 255 + ramp 2, 155 end */ @@ -213,7 +213,7 @@ static const uint8_t fade_in1_text[] = { 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9f, 0x80, 0x40, 0x01, 0xe0, 0x0c, 0xc0, 0x00, 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x46, 0x32, 0xc0, 0x00, - 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x20, 0xff, + 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x34, 0x9B, 0xc0, 0x00, 0x00, }; static const TiLp55231Program fade_in1_program = {

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Patch set updated for coreboot: rockchip: rk3399: improve sdram noc timing
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16713 -gerrit commit 39d26d506d559bf0961c9eb578747ec8d4124754 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 10:21:57 2016 -0700 rockchip: rk3399: improve sdram noc timing sdram noc timing will affect ddr latency, this patch improve rk3399 sdram noc timing so improve memory performance. BRANCH=gru BUG=chrome-os-partner:57248 TEST=Boot from kevin board Change-Id: I09e984490a7ad747ef8abfc6542d0e2c95ec19bc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 43dfe55d713d371e39d21312772fd353614b7642 Original-Change-Id: I393e74ecdeb72930ac38ae9bcf311e5654f65162 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382725 Original-Reviewed-by: Sonny Rao <sonnyrao(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Sonny Rao <sonnyrao(a)chromium.org> Original-Commit-Queue: Sonny Rao <sonnyrao(a)chromium.org> --- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 8 ++++---- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c | 12 ++++++------ .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 12 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c | 8 ++++---- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 8 ++++---- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 16 ++++++++-------- 6 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index dda6d98..a9ed180 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x0e080807}, + {0x80080807}, {0x05010605}, {0x00000002}, {0x00006076}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x0e080807}, + {0x80080807}, {0x05010605}, {0x00000002}, {0x00006076}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c index 9b0bfe7..ad0e30c 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index d5d6761..7543e10 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c index 866759b..fde24c7e 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 034e9d8..1544bd0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 2ef9d0c..a4d2007 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, - {0x14040808}, + {0x801d181e}, + {0x17050a08}, {0x00000002}, - {0x00006226}, - {0x00000054}, + {0x00006426}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, - {0x14040808}, + {0x801d181e}, + {0x17050a08}, {0x00000002}, - {0x00006226}, - {0x00000054}, + {0x00006426}, + {0x0000004c}, 0x00000000 } }

1 0

Patch set updated for coreboot: rockchip: spi: Add support for 16-bit APB reads
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16712 -gerrit commit 354fbf65564e715ad1f0f9071106e33286a394f9 Author: Simon Glass <sjg(a)chromium.org> Date: Mon Sep 5 11:10:26 2016 -0600 rockchip: spi: Add support for 16-bit APB reads With a SPI clock above about 24MHz the APB cannot keep up when doing individual byte transfers. Adjust the driver to use 16-bit reads when it can, to remove this bottleneck. Any transaction which involves writing bytes still uses 8-bit transfers, to simplify the code. These are the transfers that are not time-critical since they tend to be small. The case that really matters is reading from SPI flash. In general we can use 16-bit reads anytime we are transferring an even number of bytes. If the code detects an odd number of bytes, it tries to perform the operation in two steps: once in 16-bit mode with an even number of bytes, and once in 8-bit mode for the final byte. This allow us to use 16-bit reads even if asked to transfer (for example) 0xf423 bytes. The limit on in_now and out_now is adjusted to 0xfffe to avoid an extra transfer when transferring ~>=64KB. CQ-DEPEND=CL:383232 BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. I tested (with extra debugging) that the 16-bit case is being picked when it should be. Change-Id: If5effae9a84e4de06537fd594bedf7f01d6a9c88 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ec250b4931c7d99cc014e32ab597fca948299d08 Original-Change-Id: Idc5b7e5d82cdbdc1e8fe8b2d6da819edf2d5570c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381312 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/spi.c | 53 ++++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 7dcaaad..57e9ca1 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -149,9 +149,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) /* First Bit Mode */ ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET); - /* Byte and Halfword Transform */ - ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); - /* Frame Format */ ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); @@ -220,7 +217,7 @@ static void set_transfer_mode(struct rockchip_spi *regs, } /* returns 0 to indicate success, <0 otherwise */ -static int do_xfer(struct rockchip_spi *regs, const void *dout, +static int do_xfer(struct rockchip_spi *regs, bool use_16bit, const void *dout, unsigned int *bytes_out, void *din, unsigned int *bytes_in) { uint8_t *in_buf = din; @@ -251,12 +248,23 @@ static int do_xfer(struct rockchip_spi *regs, const void *dout, * sychronizing with the SPI clock which is pretty slow. */ if (*bytes_in && !(sr & SR_RF_EMPT)) { - int todo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK; - - *bytes_in -= todo; - xferred = todo; - while (todo-- > 0) - *in_buf++ = read32(&regs->rxdr) & 0xff; + int fifo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK; + int val; + + if (use_16bit) + xferred = fifo * 2; + else + xferred = fifo; + *bytes_in -= xferred; + while (fifo-- > 0) { + val = read32(&regs->rxdr); + if (use_16bit) { + *in_buf++ = val & 0xff; + *in_buf++ = (val >> 8) & 0xff; + } else { + *in_buf++ = val & 0xff; + } + } } min_xfer -= xferred; @@ -290,12 +298,31 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * seems to work fine. */ while (bytes_out || bytes_in) { - unsigned int in_now = MIN(bytes_in, 0xffff); - unsigned int out_now = MIN(bytes_out, 0xffff); + unsigned int in_now = MIN(bytes_in, 0xfffe); + unsigned int out_now = MIN(bytes_out, 0xfffe); unsigned int in_rem, out_rem; + unsigned int mask; + bool use_16bit; rockchip_spi_enable_chip(regs, 0); + /* + * Use 16-bit transfers for higher-speed reads. If we are + * transferring an odd number of bytes, try to make it even. + */ + use_16bit = false; + if (bytes_out == 0) { + if ((in_now & 1) && in_now > 1) + in_now--; + if (!(in_now & 1)) + use_16bit = true; + } + mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; + if (use_16bit) + clrbits_le32(&regs->ctrlr0, mask); + else + setbits_le32(&regs->ctrlr0, mask); + /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ set_transfer_mode(regs, bytes_out, bytes_in); @@ -307,7 +334,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, in_rem = in_now; out_rem = out_now; - ret = do_xfer(regs, dout, &out_rem, din, &in_rem); + ret = do_xfer(regs, use_16bit, dout, &out_rem, din, &in_rem); if (ret < 0) break;

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coreboot-gerrit October 2016