coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: i2c/ww_ring: LED changes as per UX team feedback.
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16718 -gerrit commit 878d0ea0dfc95979e3472176a118ee253652c9c9 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Sep 19 17:43:25 2016 -0700 i2c/ww_ring: LED changes as per UX team feedback. Colors and patterns as defined by the UX team BUG=b:31501528 TEST=Move the device to different states in FW using rec and dev button and verify the colors BRANCH=None Change-Id: I66d41a54590cd3ce4e5202c7cfa890f462fe195e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 703559d5dddaeeb7d435d6cadbb2009a1b7a76c8 Original-Change-Id: I95ab1fa59b483396ff1498a28f1ee98ac08d02d7 Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387258 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Christopher Book <cbook(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index 5b0c8a8..fb74a1b 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -125,13 +125,13 @@ row_blue: dw 0000000000000100b ld rb, 2 # LED off duration mux_map_addr row_red loop: - ld rc, 180 ; red intensity + ld rc, 1 ; red intensity set_pwm rc mux_map_addr row_green - ld rc, 80 ; green intensity + ld rc, 50 ; green intensity set_pwm rc mux_map_addr row_blue - ld rc, 0 ; blue intensity + ld rc, 155 ; blue intensity set_pwm rc wait1: wait 0.1 @@ -152,9 +152,9 @@ wait2: */ static const uint8_t blink_wipeout1_text[] = { 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0x98, 180, 0x84, 0x62, - 0x9f, 0x81, 0x98, 80, 0x84, 0x62, 0x9f, 0x82, - 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x94, 0x02, 0x9f, 0x80, 0x98, 1, 0x84, 0x62, + 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, + 0x98, 155, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, 0xc0, 0x00, 0xc0, 0x00, 0x00, @@ -205,7 +205,7 @@ static const TiLp55231Program blink_recovery1_program = { mux_map_addr row_blue set_pwm 0h loop3: trigger w{1} - ramp 2, 255 + ramp 2, 155 end */ @@ -213,7 +213,7 @@ static const uint8_t fade_in1_text[] = { 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9f, 0x80, 0x40, 0x01, 0xe0, 0x0c, 0xc0, 0x00, 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x46, 0x32, 0xc0, 0x00, - 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x20, 0xff, + 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x34, 0x9B, 0xc0, 0x00, 0x00, }; static const TiLp55231Program fade_in1_program = {

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Patch set updated for coreboot: rockchip: rk3399: improve sdram noc timing
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16713 -gerrit commit 5091901502b08cc2e3db82fd6eaeff397ea760c1 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 10:21:57 2016 -0700 rockchip: rk3399: improve sdram noc timing sdram noc timing will affect ddr latency, this patch improve rk3399 sdram noc timing so improve memory performance. BRANCH=gru BUG=chrome-os-partner:57248 TEST=Boot from kevin board Change-Id: I09e984490a7ad747ef8abfc6542d0e2c95ec19bc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 43dfe55d713d371e39d21312772fd353614b7642 Original-Change-Id: I393e74ecdeb72930ac38ae9bcf311e5654f65162 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382725 Original-Reviewed-by: Sonny Rao <sonnyrao(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Sonny Rao <sonnyrao(a)chromium.org> Original-Commit-Queue: Sonny Rao <sonnyrao(a)chromium.org> --- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 8 ++++---- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c | 12 ++++++------ .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 12 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c | 8 ++++---- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 8 ++++---- .../google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 16 ++++++++-------- 6 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index dda6d98..a9ed180 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x0e080807}, + {0x80080807}, {0x05010605}, {0x00000002}, {0x00006076}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x0e080807}, + {0x80080807}, {0x05010605}, {0x00000002}, {0x00006076}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c index 9b0bfe7..ad0e30c 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index d5d6761..7543e10 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x19151115}, - {0x10030806}, + {0x80151115}, + {0x11030806}, {0x00000002}, {0x00006206}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c index 866759b..fde24c7e 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 034e9d8..1544bd0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, + {0x80191519}, {0x14040808}, {0x00000002}, {0x00006226}, - {0x00000054}, + {0x0000004c}, 0x00000000 } } diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 2ef9d0c..a4d2007 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -26,11 +26,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, - {0x14040808}, + {0x801d181e}, + {0x17050a08}, {0x00000002}, - {0x00006226}, - {0x00000054}, + {0x00006426}, + {0x0000004c}, 0x00000000 } }, @@ -45,11 +45,11 @@ struct rk3399_sdram_params params = { .cs1_row = 0xF, .ddrconfig = 1, { - {0x1d191519}, - {0x14040808}, + {0x801d181e}, + {0x17050a08}, {0x00000002}, - {0x00006226}, - {0x00000054}, + {0x00006426}, + {0x0000004c}, 0x00000000 } }

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Patch set updated for coreboot: rockchip: spi: Add support for 16-bit APB reads
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16712 -gerrit commit 237f0464b41ebd416a52a5a36253ea0fc6d3abcc Author: Simon Glass <sjg(a)chromium.org> Date: Mon Sep 5 11:10:26 2016 -0600 rockchip: spi: Add support for 16-bit APB reads With a SPI clock above about 24MHz the APB cannot keep up when doing individual byte transfers. Adjust the driver to use 16-bit reads when it can, to remove this bottleneck. Any transaction which involves writing bytes still uses 8-bit transfers, to simplify the code. These are the transfers that are not time-critical since they tend to be small. The case that really matters is reading from SPI flash. In general we can use 16-bit reads anytime we are transferring an even number of bytes. If the code detects an odd number of bytes, it tries to perform the operation in two steps: once in 16-bit mode with an even number of bytes, and once in 8-bit mode for the final byte. This allow us to use 16-bit reads even if asked to transfer (for example) 0xf423 bytes. The limit on in_now and out_now is adjusted to 0xfffe to avoid an extra transfer when transferring ~>=64KB. CQ-DEPEND=CL:383232 BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. I tested (with extra debugging) that the 16-bit case is being picked when it should be. Change-Id: If5effae9a84e4de06537fd594bedf7f01d6a9c88 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ec250b4931c7d99cc014e32ab597fca948299d08 Original-Change-Id: Idc5b7e5d82cdbdc1e8fe8b2d6da819edf2d5570c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381312 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/spi.c | 53 ++++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 7dcaaad..57e9ca1 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -149,9 +149,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) /* First Bit Mode */ ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET); - /* Byte and Halfword Transform */ - ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); - /* Frame Format */ ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); @@ -220,7 +217,7 @@ static void set_transfer_mode(struct rockchip_spi *regs, } /* returns 0 to indicate success, <0 otherwise */ -static int do_xfer(struct rockchip_spi *regs, const void *dout, +static int do_xfer(struct rockchip_spi *regs, bool use_16bit, const void *dout, unsigned int *bytes_out, void *din, unsigned int *bytes_in) { uint8_t *in_buf = din; @@ -251,12 +248,23 @@ static int do_xfer(struct rockchip_spi *regs, const void *dout, * sychronizing with the SPI clock which is pretty slow. */ if (*bytes_in && !(sr & SR_RF_EMPT)) { - int todo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK; - - *bytes_in -= todo; - xferred = todo; - while (todo-- > 0) - *in_buf++ = read32(&regs->rxdr) & 0xff; + int fifo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK; + int val; + + if (use_16bit) + xferred = fifo * 2; + else + xferred = fifo; + *bytes_in -= xferred; + while (fifo-- > 0) { + val = read32(&regs->rxdr); + if (use_16bit) { + *in_buf++ = val & 0xff; + *in_buf++ = (val >> 8) & 0xff; + } else { + *in_buf++ = val & 0xff; + } + } } min_xfer -= xferred; @@ -290,12 +298,31 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * seems to work fine. */ while (bytes_out || bytes_in) { - unsigned int in_now = MIN(bytes_in, 0xffff); - unsigned int out_now = MIN(bytes_out, 0xffff); + unsigned int in_now = MIN(bytes_in, 0xfffe); + unsigned int out_now = MIN(bytes_out, 0xfffe); unsigned int in_rem, out_rem; + unsigned int mask; + bool use_16bit; rockchip_spi_enable_chip(regs, 0); + /* + * Use 16-bit transfers for higher-speed reads. If we are + * transferring an odd number of bytes, try to make it even. + */ + use_16bit = false; + if (bytes_out == 0) { + if ((in_now & 1) && in_now > 1) + in_now--; + if (!(in_now & 1)) + use_16bit = true; + } + mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; + if (use_16bit) + clrbits_le32(&regs->ctrlr0, mask); + else + setbits_le32(&regs->ctrlr0, mask); + /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ set_transfer_mode(regs, bytes_out, bytes_in); @@ -307,7 +334,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, in_rem = in_now; out_rem = out_now; - ret = do_xfer(regs, dout, &out_rem, din, &in_rem); + ret = do_xfer(regs, use_16bit, dout, &out_rem, din, &in_rem); if (ret < 0) break;

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Patch set updated for coreboot: google/gru: Shrink RW_ELOG region to 4KB
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16715 -gerrit commit f0fd4d04dfa987a5b68dd44caf8a466aa72d09c1 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Sep 12 16:02:33 2016 -0700 google/gru: Shrink RW_ELOG region to 4KB Since there's currently a limitation in coreboot's code that prevents more than 4KB to be used by the eventlog anyway, this patch shrinks the available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove prudent later if we ever resolve that limitation, so that tools can rely on the area in the FMAP being the same as the area actually used by the read-only firmware code on these boards. BRANCH=gru BUG=chrome-os-partner:55593 TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a reboot loop to exhaust eventlog space, confirmed that the shrink code kicks in as expected before reaching 4KB. Change-Id: I3c55d836c72486665a19783fe98ce9e0df174b6d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 05efb82ca00703fd92d925ebf717738e37295c18 Original-Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384585 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Simon Glass <sjg(a)google.com> --- src/mainboard/google/gru/chromeos.fmd | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index bf30ddf..2200fa7 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,7 +20,8 @@ FLASH@0x0 0x800000 { FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG@0x5d8000 0x8000 + RW_ELOG@0x5d8000 0x1000 + RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 }

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Patch set updated for coreboot: rockchip/rk3399: Move TTB to the end of SRAM
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16714 -gerrit commit 77a0e1b8fc25df7a4eb2d5e9c1ab4f6d6b41a951 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Sep 12 15:46:02 2016 -0700 rockchip/rk3399: Move TTB to the end of SRAM We found that we may want to load some components of BL31 on the RK3399 into SRAM. As usual, these components may not overlap any coreboot regions still in use at that time, as is already statically checked by the check-ramstage-overlaps rule in Makefile.inc. On RK3399, the only such regions are TTB and STACK. This patch moves the TTB region back to the end of SRAM (right before STACK), so that a large contiguous region of SRAM before that remains usable for BL31. BRANCH=gru BUG=None TEST=Booted Kevin. Change-Id: I1689d0280d79bad805fea5fc3759c2ae3ba24915 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1d4c6c6f6cc0efe97d6962a81e309a1c040d1def Original-Change-Id: I37c94f2460ef63aec4526caabe58f35ae851bab0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384635 Original-Reviewed-by: Simon Glass <sjg(a)google.com> --- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 54cfbe1..ef8d29d 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -34,9 +34,9 @@ SECTIONS TIMESTAMP(0xFF8C1C00, 1K) BOOTBLOCK(0xFF8C2004, 36K - 4) PRERAM_CBFS_CACHE(0xFF8CB000, 4K) - TTB(0xFF8CC000, 24K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D2000, 92K) - VBOOT2_WORK(0XFF8E9000, 12K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 92K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 24K) STACK(0xFF8EC000, 16K) SRAM_END(0xFF8F0000) }

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Patch set updated for coreboot: rockchip/rk3399: lower kevin board sdram frequency to 800MHz
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16709 -gerrit commit 903d81ca895cf7987879bd218ad6fd050a38852a Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 11:16:26 2016 -0700 rockchip/rk3399: lower kevin board sdram frequency to 800MHz We found some boards are not stable when sdram is run at 933Mhz. Before we can fix it, we need to lower the sdram frequency to 800MHz. In this patch we modify the DQS delay from 0x280 to 0x260 and extend the DQS window. BRANCH=None BUG=chrome-os-partner:56940 TEST=Booted Kevin. Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382724 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 4 +-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 40 +++++++++++----------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 2ececdf..1235eff 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -56,10 +56,8 @@ static enum dram_speeds get_sdram_index(void) return dram_200MHz; case 3: return dram_666MHz_NO_ODT; - case 4: - return dram_800MHz; default: - return dram_933MHz; + return dram_800MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 3a937bf..034e9d8 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02800280, /* DENALI_PHY_59_DATA */ - 0x02800280, /* DENALI_PHY_60_DATA */ - 0x02800280, /* DENALI_PHY_61_DATA */ - 0x02800280, /* DENALI_PHY_62_DATA */ - 0x00000280, /* DENALI_PHY_63_DATA */ + 0x02600260, /* DENALI_PHY_59_DATA */ + 0x02600260, /* DENALI_PHY_60_DATA */ + 0x02600260, /* DENALI_PHY_61_DATA */ + 0x02600260, /* DENALI_PHY_62_DATA */ + 0x00000260, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02800280, /* DENALI_PHY_187_DATA */ - 0x02800280, /* DENALI_PHY_188_DATA */ - 0x02800280, /* DENALI_PHY_189_DATA */ - 0x02800280, /* DENALI_PHY_190_DATA */ - 0x00000280, /* DENALI_PHY_191_DATA */ + 0x02600260, /* DENALI_PHY_187_DATA */ + 0x02600260, /* DENALI_PHY_188_DATA */ + 0x02600260, /* DENALI_PHY_189_DATA */ + 0x02600260, /* DENALI_PHY_190_DATA */ + 0x00000260, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02800280, /* DENALI_PHY_315_DATA */ - 0x02800280, /* DENALI_PHY_316_DATA */ - 0x02800280, /* DENALI_PHY_317_DATA */ - 0x02800280, /* DENALI_PHY_318_DATA */ - 0x00000280, /* DENALI_PHY_319_DATA */ + 0x02600260, /* DENALI_PHY_315_DATA */ + 0x02600260, /* DENALI_PHY_316_DATA */ + 0x02600260, /* DENALI_PHY_317_DATA */ + 0x02600260, /* DENALI_PHY_318_DATA */ + 0x00000260, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02800280, /* DENALI_PHY_443_DATA */ - 0x02800280, /* DENALI_PHY_444_DATA */ - 0x02800280, /* DENALI_PHY_445_DATA */ - 0x02800280, /* DENALI_PHY_446_DATA */ - 0x00000280, /* DENALI_PHY_447_DATA */ + 0x02600260, /* DENALI_PHY_443_DATA */ + 0x02600260, /* DENALI_PHY_444_DATA */ + 0x02600260, /* DENALI_PHY_445_DATA */ + 0x02600260, /* DENALI_PHY_446_DATA */ + 0x00000260, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */

1 0

Patch set updated for coreboot: rockchip: Correct and standardize clock divisor range assertions
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16704 -gerrit commit 0d3fee38dfa089377642e1f4446aaa18a3c128af Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Sep 6 14:09:16 2016 -0700 rockchip: Correct and standardize clock divisor range assertions Some of the asserts for valid clock divisor ranges were off by one. This patch corrects them and writes them all in a consistent way. BRANCH=None BUG=None TEST=Booted Kevin. Change-Id: I81749408a40822100797f1734f3b88987d12d8d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e09cdfde26700496aaa1fc41489f63a355e8a89d Original-Change-Id: I429edb99e2d5ff2302d9750e6569b3d21f5686fa Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381574 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 20 ++++++++++---------- src/soc/rockchip/rk3399/clock.c | 32 ++++++++++++++++---------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index bb5b846..74151e8 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -272,14 +272,14 @@ void rkclk_init(void) * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; - assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; assert((hclk_div + 1) * PD_BUS_HCLK_HZ == - PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); + PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2)); pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; assert((pclk_div + 1) * PD_BUS_PCLK_HZ == - PD_BUS_ACLK_HZ && pclk_div < 0x7); + PD_BUS_ACLK_HZ && pclk_div <= 0x7); write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, @@ -295,15 +295,15 @@ void rkclk_init(void) * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; - assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == - PERI_ACLK_HZ && (hclk_div < 0x4)); + PERI_ACLK_HZ && (hclk_div <= 0x2)); pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == - PERI_ACLK_HZ && (pclk_div < 0x4)); + PERI_ACLK_HZ && (pclk_div <= 0x3)); write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, @@ -429,7 +429,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) { int src_clk_div = GPLL_HZ / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == GPLL_HZ)); switch (bus) { /*select gpll as spi src clk, and set div*/ case 0: @@ -487,7 +487,7 @@ void rkclk_configure_crypto(unsigned int hz) { u32 div = PD_BUS_ACLK_HZ / hz; - assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ)); + assert((div - 1 <= 3) && (div * hz == PD_BUS_ACLK_HZ)); assert(hz <= 150*MHz); /* Suggested max in TRM. */ write32(&cru_ptr->cru_clksel_con[26], RK_CLRSETBITS(0x3 << 6, (div - 1) << 6)); @@ -499,7 +499,7 @@ void rkclk_configure_tsadc(unsigned int hz) u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/ div = src_clk / hz; - assert((div - 1 < 64) && (div * hz == 32 * KHz)); + assert((div - 1 <= 63) && (div * hz == 32 * KHz)); write32(&cru_ptr->cru_clksel_con[2], RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } @@ -604,7 +604,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) /* vop aclk source clk: cpll */ div = CPLL_HZ / aclk_hz; - assert((div - 1 < 64) && (div * aclk_hz == CPLL_HZ)); + assert((div - 1 <= 63) && (div * aclk_hz == CPLL_HZ)); switch (vop_id) { case 0: diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ded0a94..b9de844 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -402,7 +402,7 @@ void rkclk_init(void) /* configure pmu pclk */ pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; - assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); + assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); write32(&pmucru_ptr->pmucru_clksel[0], RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT, pclk_div << PMU_PCLK_DIV_CON_SHIFT)); @@ -420,15 +420,15 @@ void rkclk_init(void) /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; - assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; assert((hclk_div + 1) * PERIHP_HCLK_HZ == - PERIHP_ACLK_HZ && (hclk_div < 0x4)); + PERIHP_ACLK_HZ && (hclk_div <= 0x3)); pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; assert((pclk_div + 1) * PERIHP_PCLK_HZ == - PERIHP_ACLK_HZ && (pclk_div < 0x7)); + PERIHP_ACLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[14], RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK << @@ -447,15 +447,15 @@ void rkclk_init(void) /* configure perilp0 aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; - assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; assert((hclk_div + 1) * PERILP0_HCLK_HZ == - PERILP0_ACLK_HZ && (hclk_div < 0x4)); + PERILP0_ACLK_HZ && (hclk_div <= 0x3)); pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; assert((pclk_div + 1) * PERILP0_PCLK_HZ == - PERILP0_ACLK_HZ && (pclk_div < 0x7)); + PERILP0_ACLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[23], RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK << @@ -475,11 +475,11 @@ void rkclk_init(void) /* perilp1 hclk select gpll as source */ hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; assert((hclk_div + 1) * PERILP1_HCLK_HZ == - GPLL_HZ && (hclk_div < 0x1f)); + GPLL_HZ && (hclk_div <= 0x1f)); pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; assert((pclk_div + 1) * PERILP1_PCLK_HZ == - PERILP1_HCLK_HZ && (pclk_div < 0x7)); + PERILP1_HCLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[25], RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << @@ -590,7 +590,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */ pll = (bus == 3) ? PPLL_HZ : GPLL_HZ; src_clk_div = pll / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); switch (bus) { case 0: @@ -646,7 +646,7 @@ static void rkclk_configure_i2c(unsigned int bus, unsigned int hz) /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ pll = (bus == 0 || bus == 4 || bus == 8) ? PPLL_HZ : GPLL_HZ; src_clk_div = pll / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); switch (bus) { case 0: @@ -749,7 +749,7 @@ void rkclk_configure_saradc(unsigned int hz) /* saradc src clk from 24MHz */ src_clk_div = 24 * MHz / hz; - assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz)); + assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz)); write32(&cru_ptr->clksel_con[26], RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << @@ -765,7 +765,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) /* vop aclk source clk: cpll */ div = CPLL_HZ / aclk_hz; - assert((div - 1 < 32) && (div * aclk_hz == CPLL_HZ)); + assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ)); write32(reg_addr, RK_CLRSETBITS( ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT | @@ -803,7 +803,7 @@ void rkclk_configure_tsadc(unsigned int hz) /* use 24M as src clock */ src_clk_div = OSC_HZ / hz; - assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ)); + assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ)); write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | @@ -820,7 +820,7 @@ void rkclk_configure_emmc(void) /* Select aclk_emmc source from GPLL */ src_clk_div = GPLL_HZ / aclk_emmc; - assert((src_clk_div - 1 < 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); + assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); write32(&cru_ptr->clksel_con[21], RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK << @@ -832,7 +832,7 @@ void rkclk_configure_emmc(void) /* Select clk_emmc source from GPLL too */ src_clk_div = GPLL_HZ / clk_emmc; - assert((src_clk_div - 1 < 127) && (src_clk_div * clk_emmc == GPLL_HZ)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ)); write32(&cru_ptr->clksel_con[22], RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT |

1 0

Patch set updated for coreboot: arm64: Use 'payload' format for ATF instead of 'stage'
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16706 -gerrit commit 155f40b6f2010499359166034969f5f04d04549a Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 12:18:38 2016 -0600 arm64: Use 'payload' format for ATF instead of 'stage' Switch the BL31 (ARM Trusted Firmware) format to payload so that it can have multiple independent segments. This also requires disabling the region check since SRAM is currently faulted by that check. This has been tested with Rockchip's pending change: https://chromium-review.googlesource.com/#/c/368592/3 with the patch mentioned on the bug at #13. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is correct though: CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1b440 size 15a75 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000018104800 Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d using LZMA [ 0x18104800, 18137d90, 0x192843e0) <- 00100038 Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650 dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1 Jumping to boot code at 0000000018104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes CBFS: 'VBOOT' located CBFS at [402000:44cc00) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 10ec0 size 8d0c Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26 Loading segment from ROM address 0x0000000000100038 Entry Point 0x0000000000010000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 using LZMA [ 0x00010000, 00035708, 0x00050000) <- 00100054 Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8 dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 using LZMA [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6 dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff Loaded segments INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80 INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364 INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648 NOTICE: BL31: v1.2(debug): NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1189): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x18104800 INFO: SPSR = 0x8 Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376849 Original-Commit-Ready: Simon Glass <sjg(a)google.com> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 +- src/arch/arm64/arm_tf.c | 5 ++--- src/include/program_loading.h | 10 ++++++++-- src/lib/prog_loaders.c | 2 +- src/lib/selfboot.c | 24 ++++++++++++++---------- 5 files changed, 26 insertions(+), 17 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index ece35a6..6e3f080 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -178,7 +178,7 @@ $(BL31): $(obj)/build.h BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 $(BL31_CBFS)-file := $(BL31) -$(BL31_CBFS)-type := stage +$(BL31_CBFS)-type := payload $(BL31_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(BL31_CBFS) diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 1ec87c4..e976e34 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -50,11 +50,10 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) if (prog_locate(&bl31)) die("BL31 not found"); - if (cbfs_prog_stage_load(&bl31)) + bl31_entry = selfload(&bl31, false); + if (!bl31_entry) die("BL31 load failed"); - bl31_entry = prog_entry(&bl31); - SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0); if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) { diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e265b18..3958fda 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -189,7 +189,13 @@ void payload_run(void); /* Mirror the payload to be loaded. */ void mirror_payload(struct prog *payload); -/* Defined in src/lib/selfboot.c */ -void *selfload(struct prog *payload); +/* + * Set check_regions to true to check that the payload targets usable memory. + * With this flag set, if it does not, the load will fail and this function + * will return NULL. + * + * Defined in src/lib/selfboot.c + */ +void *selfload(struct prog *payload, bool check_regions); #endif /* PROGRAM_LOADING_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..c0dcd60 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -161,7 +161,7 @@ void payload_load(void) mirror_payload(payload); /* Pass cbtables to payload if architecture desires it. */ - prog_set_entry(payload, selfload(payload), + prog_set_entry(payload, selfload(payload, true), cbmem_find(CBMEM_ID_CBTABLE)); out: diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 1ce7f94..162a034 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -88,7 +88,8 @@ static void get_bounce_buffer(unsigned long req_size) /* When the ramstage is relocatable there is no need for a bounce * buffer. All payloads should not overlap the ramstage. */ - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) || + !arch_supports_bounce_buffer()) { bounce_buffer = ~0UL; bounce_size = 0; return; @@ -357,15 +358,16 @@ static int payload_targets_usable_ram(struct segment *head) return 1; } -static int load_self_segments( - struct segment *head, - struct prog *payload) +static int load_self_segments(struct segment *head, struct prog *payload, + bool check_regions) { struct segment *ptr; unsigned long bounce_high = lb_end; - if (!payload_targets_usable_ram(head)) - return 0; + if (check_regions) { + if (!payload_targets_usable_ram(head)) + return 0; + } for(ptr = head->next; ptr != head; ptr = ptr->next) { /* @@ -373,8 +375,10 @@ static int load_self_segments( * allocated so that there aren't conflicts with the actual * payload. */ - bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, - LB_MEM_UNUSABLE); + if (check_regions) { + bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, + LB_MEM_UNUSABLE); + } if (!overlaps_coreboot(ptr)) continue; @@ -486,7 +490,7 @@ static int load_self_segments( return 1; } -void *selfload(struct prog *payload) +void *selfload(struct prog *payload, bool check_regions) { uintptr_t entry = 0; struct segment head; @@ -502,7 +506,7 @@ void *selfload(struct prog *payload) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, payload, check_regions)) goto out; printk(BIOS_SPEW, "Loaded segments\n");

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Patch set updated for coreboot: rockchip/rk3399: Move big CPU cluster initialization into ramstage
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16698 -gerrit commit e9f1f3ec54e4b750d42034c67b58363c04e7ee39 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 29 15:07:58 2016 -0700 rockchip/rk3399: Move big CPU cluster initialization into ramstage This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/mainboard/google/gru/bootblock.c | 2 +- src/soc/rockchip/rk3399/clock.c | 40 +++++++++++++++++------------ src/soc/rockchip/rk3399/include/soc/clock.h | 7 ++++- src/soc/rockchip/rk3399/soc.c | 4 +++ 4 files changed, 34 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 0e916d2..d76ec8b 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -117,7 +117,7 @@ static void speed_up_boot_cpu(void) udelay(200); - rkclk_configure_cpu(APLL_1512_MHZ, false); + rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); } void bootblock_mainboard_init(void) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 9ac1ffe..ded0a94 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -494,26 +494,32 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big) +void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster) { - u32 aclkm_div; - u32 pclk_dbg_div; - u32 atclk_div; - u32 apll_l_hz; - int con_base = is_big ? 2 : 0; - int parent = is_big ? CLK_CORE_PLL_SEL_ABPLL : CLK_CORE_PLL_SEL_ALPLL; - u32 *pll_con = is_big ? &cru_ptr->apll_b_con[0] : - &cru_ptr->apll_l_con[0]; - - apll_l_hz = apll_cfgs[apll_freq]->freq; - - rkclk_set_pll(pll_con, apll_cfgs[apll_freq]); - - aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; + u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz; + int con_base, parent; + u32 *pll_con; + + switch (cluster) { + case CPU_CLUSTER_LITTLE: + con_base = 0; + parent = CLK_CORE_PLL_SEL_ALPLL; + pll_con = &cru_ptr->apll_l_con[0]; + break; + case CPU_CLUSTER_BIG: + default: + con_base = 2; + parent = CLK_CORE_PLL_SEL_ABPLL; + pll_con = &cru_ptr->apll_b_con[0]; + break; + } - pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1; + apll_hz = apll_cfgs[freq]->freq; + rkclk_set_pll(pll_con, apll_cfgs[freq]); - atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1; + aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1; + pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1; + atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1; write32(&cru_ptr->clksel_con[con_base], RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index e04b216..5926051 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -101,9 +101,14 @@ enum apll_frequencies { APLL_600_MHZ, }; +enum cpu_cluster { + CPU_CLUSTER_LITTLE, + CPU_CLUSTER_BIG, +}; + void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); -void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big); +void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_emmc(void); void rkclk_configure_i2s(unsigned int hz); diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 1adf3f6..12c757f 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -18,6 +18,7 @@ #include <cpu/cpu.h> #include <device/device.h> #include <soc/addressmap.h> +#include <soc/clock.h> #include <soc/display.h> #include <stddef.h> #include <stdlib.h> @@ -42,6 +43,9 @@ static void soc_init(device_t dev) _framebuffer_size); else printk(BIOS_INFO, "Display initialization disabled.\n"); + + /* We don't need big CPUs, but bring them up as a courtesy to Linux. */ + rkclk_configure_cpu(APLL_600_MHZ, CPU_CLUSTER_BIG); } static struct device_operations soc_ops = {

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Patch set updated for coreboot: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16699 -gerrit commit 14fb013fe2f123895877923ae348ee24de07caed Author: Jeffy Chen <jeffy.chen(a)rock-chips.com> Date: Fri Sep 2 18:16:33 2016 +0800 google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_rialto/sdram_configs.c | 2 +- .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc | 77 ++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 42fa582..0e260c3 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -22,7 +22,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc new file mode 100644 index 0000000..df3bb2a --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x0, + .col = 0x0, + .bk = 0x0, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x0, + .cs1_row = 0x0 + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 22, + .odt = 0 +},

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coreboot-gerrit October 2016