coreboot-gerrit October 2016

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New patch to review for coreboot: soc/intel/apollolake: Set package power limits for RAPL registers
by Sumeet R Pawnikar 05 Oct '16

05 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16884 -gerrit commit db135036699b838eda9ca42a43cee1be23437adb Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Sep 27 23:18:35 2016 +0530 soc/intel/apollolake: Set package power limits for RAPL registers This patch sets the package power limit values in RAPL MSR and MMIO registers after boot and suspend-resume cycle. BUG=chrome-os-partner:56922 TEST=Build, booted and tested these package power limits before and after boot and suspend-resume cycle. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 123 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 8 ++ 2 files changed, 131 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index eeac6ce..6bbc5e5 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -38,6 +38,64 @@ #include "chip.h" +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + static void *vbt; static struct region_device vbt_rdev; @@ -193,6 +251,68 @@ static void pcie_override_devicetree_after_silicon_init(void) pcie_update_device_tree(PCIEB0_DEVFN, 2); } +/* Configure processor power limits */ +static void set_power_limits(u8 power_limit_1_time) +{ + uint32_t *rapl_mmio_reg; + msr_t rapl_msr_reg, limit; + unsigned power_unit; + unsigned tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + rapl_mmio_reg = (void*)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); + + if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + power_limit_1_time = MB_POWER_LIMIT1_TIME_DEFAULT; + + /* Get units */ + rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (rapl_msr_reg.lo & 0xf); + + /* Get power defaults for this SKU */ + rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); + tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; + min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; + max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; + max_time = (rapl_msr_reg.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit PL2 to 15W */ + limit.hi = 0; + limit.hi |= 0xf00 & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + + /* Program package power limits in RAPL MSR */ + wrmsr(MSR_PKG_POWER_LIMIT, limit); + + /* Setting RAPL MMIO reister for Power limits */ + write32(rapl_mmio_reg, limit.lo & (~(PKG_POWER_LIMIT_EN))); + write32(rapl_mmio_reg + 1, limit.hi); +} + static void rapl_update(void) { uint32_t *rapl_reg; @@ -241,6 +361,9 @@ static void soc_init(void *data) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + /* Set RAPL MSR for Package power limits*/ + set_power_limits(28); + /* Update RAPL package power limit */ rapl_update(); } diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..dbe0503 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -39,6 +39,14 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L2_DISABLE (1 << 2) #define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +/* For Mobile, default PL1 time window value is 28 seconds */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 28 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f

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Patch set updated for coreboot: mainboard/google/reef: add pyro variant.
by Kevin Chiu 05 Oct '16

05 Oct '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16855 -gerrit commit 08bf8a43ed1d19d2660b421a924e1649a2cac6e6 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Mon Oct 3 17:15:15 2016 +0800 mainboard/google/reef: add pyro variant. Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b --- src/mainboard/google/reef/Kconfig | 4 + src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/pyro/Makefile.inc | 1 + .../google/reef/variants/pyro/devicetree.cb | 173 +++++++++++++++++++++ .../variants/pyro/include/variant/acpi/dptf.asl | 89 +++++++++++ .../google/reef/variants/pyro/include/variant/ec.h | 21 +++ .../reef/variants/pyro/include/variant/gpio.h | 21 +++ src/mainboard/google/reef/variants/pyro/memory.c | 116 ++++++++++++++ 8 files changed, 430 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index ffdf917..19b1bd1 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,14 +50,17 @@ config MAINBOARD_DIR config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF + default "pyro" if BOARD_GOOGLE_PYRO config DEVICETREE string + default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF + default "Pyro" if BOARD_GOOGLE_PYRO config MAINBOARD_FAMILY string @@ -67,6 +70,7 @@ config GBB_HWID string depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF + default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index 926f61d..d73e69b 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -2,3 +2,8 @@ config BOARD_GOOGLE_REEF bool "Reef" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_PYRO + bool "Pyro" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Makefile.inc b/src/mainboard/google/reef/variants/pyro/Makefile.inc new file mode 100644 index 0000000..fd45b94 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Makefile.inc @@ -0,0 +1 @@ +romstage-y += memory.c diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb new file mode 100644 index 0000000..087f858 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..43e2e93 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/acpi/dptf.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/ec.h b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c new file mode 100644 index 0000000..a87e6c6 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <variant/gpio.h> + + +static const struct lpddr4_sku skus[] = { + /* + * K4F6E304HB-MGCJ - both logical channels While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [0] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HB-MGCJ", + }, + /* K4F8E304HB-MGCJ - both logical channels */ + [1] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "K4F8E304HB-MGCJ", + }, + /* + * MT53B512M32D2NP-062WT:C - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate + * the deneisty as 8Gb per rank. + */ + [2] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, + }, + /* MT53B256M32D1NP-062 WT:C - both logical channels */ + [3] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, + }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, + /*Samsung 290 K4F6E304HB-MGCH 16Gb dual-ch*/ + [0xe] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "K4F6E304HBMGCH", + .disable_periodic_retraining = 1, + }, + /*Samsung 280 K4F8E304HB-MGCH 8Gb dual-ch*/ + [0xf] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 0, + .ch1_dual_rank = 0, + .part_num = "K4F8E304HBMGCH", + .disable_periodic_retraining = 1, + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), + .swizzle_config = &baseboard_lpddr4_swizzle, +}; + +const struct lpddr4_cfg *variant_lpddr4_config(void) +{ + return &lp4cfg; +}

1 0

Patch merged into coreboot/master: siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 ms
by gerrit＠coreboot.org 05 Oct '16

05 Oct '16

the following patch was just integrated into master: commit 77ba882c67b98801232bace922471f22fafc0212 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Oct 4 11:59:59 2016 +0200 siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 ms Due to different LCD panel requirements the delay between LVDS becomes active and the backlight is switched on needs to be increased to 500 ms. Change-Id: I09029624469aef412141c7b46224d48557ba4af1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/16875 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16875 for details. -gerrit

1 0

New patch to review for coreboot: Update build-release script
by Martin Roth 05 Oct '16

05 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16883 -gerrit commit c4a5181f653d1e204d9402afd49a442dd92386cd Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 4 16:45:17 2016 -0600 Update build-release script - Add more help text. - Remove braces from variables where the variable is isolated. - Remove --recurse-submodules from clone. This breaks on old coreboot versions. - Add some whitespace between blocks. - Fix all shellcheck warnings. - Verify tar version and fail if it doesn't support --sort. Change-Id: I4a49df99532d9a92a4a05bceff16f96a4fc3e205 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/release/build-release | 56 ++++++++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/util/release/build-release b/util/release/build-release index 11e7177..2525252 100755 --- a/util/release/build-release +++ b/util/release/build-release @@ -3,10 +3,10 @@ # ${GPG_KEY_ID}: gpg key id (if not don't sign) # ${USERNAME}: username (if not default to https) # ${COMMIT_ID}: commit id (if not master) -VERSION_NAME=${1} -COMMIT_ID=${2} -USERNAME=${3} -GPG_KEY_ID=${4} +VERSION_NAME=$1 +COMMIT_ID=$2 +USERNAME=$3 +GPG_KEY_ID=$4 set -e @@ -16,32 +16,50 @@ LANG=C TZ=UTC export LC_ALL LANG TZ -if [ -z "${VERSION_NAME}" ] || [ "${VERSION_NAME}" = "--help" ]; then +if [ -z "$VERSION_NAME" ] || [ "$VERSION_NAME" = "--help" ]; then echo "usage: $0 <version> [commit id] [gpg key id] [username]" - echo "tags a new coreboot version and creates a tar archive" + echo "Tags a new coreboot version and creates a tar archive" + echo + echo "version: New version name to tag the tree with" + echo "commit id: check out this commit-id after cloning the coreboot tree" + echo "gpg key id: used to tag the version, and generate a gpg signature" + echo "username: clone the tree using ssh://USERNAME - defaults to https://" exit 1 fi + +# Verify that gnu tar v1.28 or newer is present to support --sort +tarversion=$(tar --version | grep '(GNU tar)' | sed 's/.*) //' | sed 's/\.//2') +if [ -z "$tarversion" ] || (( $(echo "$tarversion < 1.28" | bc -l) )); then + echo "Error: GNU tar version 1.28 or greater is required. Exiting." + exit 1 +fi + if [ -n "${USERNAME}" ]; then - git clone --recurse-submodules ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git coreboot-${VERSION_NAME} + git clone "ssh://${USERNAME}@review.coreboot.org:29418/coreboot.git" "coreboot-${VERSION_NAME}" else - git clone --recurse-submodules https://review.coreboot.org/coreboot.git coreboot-${VERSION_NAME} + git clone https://review.coreboot.org/coreboot.git "coreboot-${VERSION_NAME}" fi -cd coreboot-${VERSION_NAME} -if [ -n "${COMMIT_ID}" ]; then - git reset --hard ${COMMIT_ID} + +cd "coreboot-${VERSION_NAME}" || exit 1 +if [ -n "$COMMIT_ID" ]; then + git reset --hard "$COMMIT_ID" fi + git submodule update --init --checkout -if [ -n "${GPG_KEY_ID}" ]; then - git tag -a -s -u ${GPG_KEY_ID} --force ${VERSION_NAME} -m "coreboot version ${VERSION_NAME}" +if [ -n "$GPG_KEY_ID" ]; then + git tag -a -s -u "$GPG_KEY_ID" --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" else - git tag -a --force ${VERSION_NAME} -m "coreboot version ${VERSION_NAME}" + git tag -a --force "$VERSION_NAME" -m "coreboot version $VERSION_NAME" fi -printf "${VERSION_NAME}-$(git log --pretty=%H|head -1)\n" > .coreboot-version + +printf "%s-%s\n" "$VERSION_NAME" "$(git log --pretty=%H|head -1)" > .coreboot-version tstamp=$(git log --pretty=format:%ci -1) cd .. -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude=coreboot-${VERSION_NAME}/3rdparty/blobs -cvf - coreboot-${VERSION_NAME} |xz -9 > coreboot-${VERSION_NAME}.tar.xz -tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - coreboot-${VERSION_NAME}/3rdparty/blobs |xz -9 > coreboot-blobs-${VERSION_NAME}.tar.xz + +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude="coreboot-${VERSION_NAME}/3rdparty/blobs" -cvf - "coreboot-${VERSION_NAME}" |xz -9 > "coreboot-${VERSION_NAME}.tar.xz" +tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - "coreboot-${VERSION_NAME}/3rdparty/blobs" |xz -9 > "coreboot-blobs-${VERSION_NAME}.tar.xz" + if [ -n "${GPG_KEY_ID}" ]; then - gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-${VERSION_NAME}.tar.xz - gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-blobs-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-blobs-${VERSION_NAME}.tar.xz + gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-${VERSION_NAME}.tar.xz" + gpg2 --armor --local-user "$GPG_KEY_ID" --output "coreboot-blobs-${VERSION_NAME}.tar.xz.sig" --detach-sig "coreboot-blobs-${VERSION_NAME}.tar.xz" fi

1 0

Patch set updated for coreboot: rockchip/rk3399: Configure USB3 controller work in USB2 only mode
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16717 -gerrit commit 02dd84f88e3ded4e5eb4660a512d498dadf440f0 Author: Liangfeng Wu <wulf(a)rock-chips.com> Date: Thu Sep 15 17:16:54 2016 +0800 rockchip/rk3399: Configure USB3 controller work in USB2 only mode During the USB2 only mode, the Type-C PHY will be held in reset and only USB2 part logic of USB3 OTG controller and PHY may be used over the USB2 pins on the Type-C connector to support Low, Full and High-speed USB operation. BRANCH=none BUG=chrome-os-partner:56425 TEST=Go to recovery mode, plug a Type-C USB drive containing chrome OS image into both ports in all orientations, check if system can boot form USB. Change-Id: Ic265c0c91c24f63b2f9c3106eb2bb277a589233b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a37ccc5b6019967483eac6b5a360d67bc3326e93 Original-Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad Original-Signed-off-by: Liangfeng Wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/385837 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/usb.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index f638a1e..4c731bd 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -17,6 +17,9 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <soc/clock.h> +#include <soc/grf.h> +#include <soc/soc.h> #include <soc/usb.h> /* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just @@ -86,12 +89,24 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) void reset_usb_otg0(void) { + /* Keep whole USB OTG0 controller in reset, then + * configure controller to work in USB 2.0 only mode. */ + write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5)); + write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); + write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5)); + printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG0\n"); reset_dwc3(rockchip_usb_otg0_dwc3); } void reset_usb_otg1(void) { + /* Keep whole USB OTG1 controller in reset, then + * configure controller to work in USB 2.0 only mode. */ + write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6)); + write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0)); + write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6)); + printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG1\n"); reset_dwc3(rockchip_usb_otg1_dwc3); }

1 0

Patch set updated for coreboot: rockchip/rk3399: select rank before triggering training
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16768 -gerrit commit e1f80777ca58afabf339e9e69937c53d8afebb95 Author: Derek Basehore <dbasehore(a)chromium.org> Date: Wed Sep 21 15:43:36 2016 -0700 rockchip/rk3399: select rank before triggering training This selects the rank to train before training is triggered. This is to prevent any race conditions with the hardware. BRANCH=none BUG=chrome-os-partner:56940 TEST=stressapptest -M 1536 -s 1000 Change-Id: I892bace414cf4495619d41bdaea0c4e91c1e29b3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f2dd6f52978a9e54ddd2688eb68fd237aabfe2d Original-Change-Id: I4e7118d8509b59e391d0a254477b5390dfdd43a5 Original-Signed-off-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/387907 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: 云平汤 <typ(a)rock-chips.com> --- src/soc/rockchip/rk3399/sdram.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 1021c6b..42b2574 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -685,15 +685,14 @@ static int data_training(u32 channel, /* ca training(LPDDR4,LPDDR3 support) */ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); - /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[92], (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -726,6 +725,7 @@ static int data_training(u32 channel, /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ @@ -733,7 +733,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -772,6 +771,7 @@ static int data_training(u32 channel, /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); /* @@ -782,7 +782,6 @@ static int data_training(u32 channel, (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -818,6 +817,7 @@ static int data_training(u32 channel, /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ @@ -825,7 +825,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 24), (0x1 << 8) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -850,6 +849,7 @@ static int data_training(u32 channel, /* wdq leveling(LPDDR4 support) */ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 @@ -862,7 +862,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8;

1 0

Patch set updated for coreboot: rockchip: rk3399: improve write leveling flow
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16716 -gerrit commit ab5989b5687e3821952fe3318232773f654ac9d3 Author: Jianqun Xu <jay.xu(a)rock-chips.com> Date: Sun Sep 11 18:26:42 2016 +0800 rockchip: rk3399: improve write leveling flow To improve sdram 800MHz and 933MHz stability, we need to modify write leveling flow, to get the more proper write leveling value. BUG=chrome-os-partner:56940 BRANCH=none TEST=Boot from kevin on 933MHz, and do stressapptest Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be Original-Signed-off-by: Jianqun Xu <jay.xu(a)rock-chips.com> Original-Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/384292 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 10 +-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 16 ++-- .../sdram-lpddr3-hynix-4GB-666-no-odt.c | 16 ++-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 16 ++-- .../sdram-lpddr3-hynix-4GB-800-no-odt.c | 56 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 56 ++++++------ .../gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 56 ++++++------ src/soc/rockchip/rk3399/sdram.c | 99 ++++++++-------------- 8 files changed, 146 insertions(+), 179 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 1235eff..2aa05a7 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -50,14 +50,10 @@ static enum dram_speeds get_sdram_index(void) if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) switch (id) { - case 0: - case 1: - case 2: - return dram_200MHz; - case 3: - return dram_666MHz_NO_ODT; - default: + case 4: return dram_800MHz; + default: + return dram_933MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index a9ed180..c877158 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00800080, /* DENALI_PHY_77_DATA */ - 0x01900001, /* DENALI_PHY_78_DATA */ + 0x00000001, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00000000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c044208, /* DENALI_PHY_87_DATA */ + 0x07044208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00800080, /* DENALI_PHY_205_DATA */ - 0x01900001, /* DENALI_PHY_206_DATA */ + 0x00000001, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00000000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c044208, /* DENALI_PHY_215_DATA */ + 0x07044208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00800080, /* DENALI_PHY_333_DATA */ - 0x01900001, /* DENALI_PHY_334_DATA */ + 0x00000001, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00000000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c044208, /* DENALI_PHY_343_DATA */ + 0x07044208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00800080, /* DENALI_PHY_461_DATA */ - 0x01900001, /* DENALI_PHY_462_DATA */ + 0x00000001, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00000000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0003150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c044208, /* DENALI_PHY_471_DATA */ + 0x07044208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c index ad0e30c..f57ac18 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666-no-odt.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01c40080, /* DENALI_PHY_77_DATA */ - 0x01900002, /* DENALI_PHY_78_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01c40080, /* DENALI_PHY_205_DATA */ - 0x01900002, /* DENALI_PHY_206_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01c40080, /* DENALI_PHY_333_DATA */ - 0x01900002, /* DENALI_PHY_334_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01c40080, /* DENALI_PHY_461_DATA */ - 0x01900002, /* DENALI_PHY_462_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 7543e10..591924d 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01c40080, /* DENALI_PHY_77_DATA */ - 0x01900002, /* DENALI_PHY_78_DATA */ + 0x00000002, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x010000c0, /* DENALI_PHY_85_DATA */ 0x00100000, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01c40080, /* DENALI_PHY_205_DATA */ - 0x01900002, /* DENALI_PHY_206_DATA */ + 0x00000002, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x010000c0, /* DENALI_PHY_213_DATA */ 0x00100000, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01c40080, /* DENALI_PHY_333_DATA */ - 0x01900002, /* DENALI_PHY_334_DATA */ + 0x00000002, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x010000c0, /* DENALI_PHY_341_DATA */ 0x00100000, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01c40080, /* DENALI_PHY_461_DATA */ - 0x01900002, /* DENALI_PHY_462_DATA */ + 0x00000002, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x010000c0, /* DENALI_PHY_469_DATA */ 0x00100000, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c index fde24c7e..21f7044 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800-no-odt.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02800280, /* DENALI_PHY_59_DATA */ - 0x02800280, /* DENALI_PHY_60_DATA */ - 0x02800280, /* DENALI_PHY_61_DATA */ - 0x02800280, /* DENALI_PHY_62_DATA */ - 0x00000280, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00b30080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02800280, /* DENALI_PHY_187_DATA */ - 0x02800280, /* DENALI_PHY_188_DATA */ - 0x02800280, /* DENALI_PHY_189_DATA */ - 0x02800280, /* DENALI_PHY_190_DATA */ - 0x00000280, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00b30080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02800280, /* DENALI_PHY_315_DATA */ - 0x02800280, /* DENALI_PHY_316_DATA */ - 0x02800280, /* DENALI_PHY_317_DATA */ - 0x02800280, /* DENALI_PHY_318_DATA */ - 0x00000280, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00b30080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02800280, /* DENALI_PHY_443_DATA */ - 0x02800280, /* DENALI_PHY_444_DATA */ - 0x02800280, /* DENALI_PHY_445_DATA */ - 0x02800280, /* DENALI_PHY_446_DATA */ - 0x00000280, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00b30080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 1544bd0..b738644 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02600260, /* DENALI_PHY_59_DATA */ - 0x02600260, /* DENALI_PHY_60_DATA */ - 0x02600260, /* DENALI_PHY_61_DATA */ - 0x02600260, /* DENALI_PHY_62_DATA */ - 0x00000260, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x00b30080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00020000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c054208, /* DENALI_PHY_87_DATA */ + 0x07054208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02600260, /* DENALI_PHY_187_DATA */ - 0x02600260, /* DENALI_PHY_188_DATA */ - 0x02600260, /* DENALI_PHY_189_DATA */ - 0x02600260, /* DENALI_PHY_190_DATA */ - 0x00000260, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x00b30080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00020000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c054208, /* DENALI_PHY_215_DATA */ + 0x07054208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02600260, /* DENALI_PHY_315_DATA */ - 0x02600260, /* DENALI_PHY_316_DATA */ - 0x02600260, /* DENALI_PHY_317_DATA */ - 0x02600260, /* DENALI_PHY_318_DATA */ - 0x00000260, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x00b30080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00020000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c054208, /* DENALI_PHY_343_DATA */ + 0x07054208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02600260, /* DENALI_PHY_443_DATA */ - 0x02600260, /* DENALI_PHY_444_DATA */ - 0x02600260, /* DENALI_PHY_445_DATA */ - 0x02600260, /* DENALI_PHY_446_DATA */ - 0x00000260, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x00b30080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00020000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c054208, /* DENALI_PHY_471_DATA */ + 0x07054208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index a4d2007..362489b 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02600260, /* DENALI_PHY_59_DATA */ - 0x02600260, /* DENALI_PHY_60_DATA */ - 0x02600260, /* DENALI_PHY_61_DATA */ - 0x02600260, /* DENALI_PHY_62_DATA */ - 0x00000260, /* DENALI_PHY_63_DATA */ + 0x02700270, /* DENALI_PHY_59_DATA */ + 0x02700270, /* DENALI_PHY_60_DATA */ + 0x02700270, /* DENALI_PHY_61_DATA */ + 0x02700270, /* DENALI_PHY_62_DATA */ + 0x00000270, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -679,7 +679,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_75_DATA */ 0x00800080, /* DENALI_PHY_76_DATA */ 0x01a20080, /* DENALI_PHY_77_DATA */ - 0x01900003, /* DENALI_PHY_78_DATA */ + 0x00000003, /* DENALI_PHY_78_DATA */ 0x00000000, /* DENALI_PHY_79_DATA */ 0x00030000, /* DENALI_PHY_80_DATA */ 0x00000200, /* DENALI_PHY_81_DATA */ @@ -688,7 +688,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_84_DATA */ 0x020000c0, /* DENALI_PHY_85_DATA */ 0x00100001, /* DENALI_PHY_86_DATA */ - 0x0c064208, /* DENALI_PHY_87_DATA */ + 0x07064208, /* DENALI_PHY_87_DATA */ 0x000f0c18, /* DENALI_PHY_88_DATA */ 0x01000140, /* DENALI_PHY_89_DATA */ 0x00000c20, /* DENALI_PHY_90_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02600260, /* DENALI_PHY_187_DATA */ - 0x02600260, /* DENALI_PHY_188_DATA */ - 0x02600260, /* DENALI_PHY_189_DATA */ - 0x02600260, /* DENALI_PHY_190_DATA */ - 0x00000260, /* DENALI_PHY_191_DATA */ + 0x02700270, /* DENALI_PHY_187_DATA */ + 0x02700270, /* DENALI_PHY_188_DATA */ + 0x02700270, /* DENALI_PHY_189_DATA */ + 0x02700270, /* DENALI_PHY_190_DATA */ + 0x00000270, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -807,7 +807,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_203_DATA */ 0x00800080, /* DENALI_PHY_204_DATA */ 0x01a20080, /* DENALI_PHY_205_DATA */ - 0x01900003, /* DENALI_PHY_206_DATA */ + 0x00000003, /* DENALI_PHY_206_DATA */ 0x00000000, /* DENALI_PHY_207_DATA */ 0x00030000, /* DENALI_PHY_208_DATA */ 0x00000200, /* DENALI_PHY_209_DATA */ @@ -816,7 +816,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_212_DATA */ 0x020000c0, /* DENALI_PHY_213_DATA */ 0x00100001, /* DENALI_PHY_214_DATA */ - 0x0c064208, /* DENALI_PHY_215_DATA */ + 0x07064208, /* DENALI_PHY_215_DATA */ 0x000f0c18, /* DENALI_PHY_216_DATA */ 0x01000140, /* DENALI_PHY_217_DATA */ 0x00000c20, /* DENALI_PHY_218_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02600260, /* DENALI_PHY_315_DATA */ - 0x02600260, /* DENALI_PHY_316_DATA */ - 0x02600260, /* DENALI_PHY_317_DATA */ - 0x02600260, /* DENALI_PHY_318_DATA */ - 0x00000260, /* DENALI_PHY_319_DATA */ + 0x02700270, /* DENALI_PHY_315_DATA */ + 0x02700270, /* DENALI_PHY_316_DATA */ + 0x02700270, /* DENALI_PHY_317_DATA */ + 0x02700270, /* DENALI_PHY_318_DATA */ + 0x00000270, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -935,7 +935,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_331_DATA */ 0x00800080, /* DENALI_PHY_332_DATA */ 0x01a20080, /* DENALI_PHY_333_DATA */ - 0x01900003, /* DENALI_PHY_334_DATA */ + 0x00000003, /* DENALI_PHY_334_DATA */ 0x00000000, /* DENALI_PHY_335_DATA */ 0x00030000, /* DENALI_PHY_336_DATA */ 0x00000200, /* DENALI_PHY_337_DATA */ @@ -944,7 +944,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_340_DATA */ 0x020000c0, /* DENALI_PHY_341_DATA */ 0x00100001, /* DENALI_PHY_342_DATA */ - 0x0c064208, /* DENALI_PHY_343_DATA */ + 0x07064208, /* DENALI_PHY_343_DATA */ 0x000f0c18, /* DENALI_PHY_344_DATA */ 0x01000140, /* DENALI_PHY_345_DATA */ 0x00000c20, /* DENALI_PHY_346_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02600260, /* DENALI_PHY_443_DATA */ - 0x02600260, /* DENALI_PHY_444_DATA */ - 0x02600260, /* DENALI_PHY_445_DATA */ - 0x02600260, /* DENALI_PHY_446_DATA */ - 0x00000260, /* DENALI_PHY_447_DATA */ + 0x02700270, /* DENALI_PHY_443_DATA */ + 0x02700270, /* DENALI_PHY_444_DATA */ + 0x02700270, /* DENALI_PHY_445_DATA */ + 0x02700270, /* DENALI_PHY_446_DATA */ + 0x00000270, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */ @@ -1063,7 +1063,7 @@ struct rk3399_sdram_params params = { 0x00800080, /* DENALI_PHY_459_DATA */ 0x00800080, /* DENALI_PHY_460_DATA */ 0x01a20080, /* DENALI_PHY_461_DATA */ - 0x01900003, /* DENALI_PHY_462_DATA */ + 0x00000003, /* DENALI_PHY_462_DATA */ 0x00000000, /* DENALI_PHY_463_DATA */ 0x00030000, /* DENALI_PHY_464_DATA */ 0x00000200, /* DENALI_PHY_465_DATA */ @@ -1072,7 +1072,7 @@ struct rk3399_sdram_params params = { 0xc0013150, /* DENALI_PHY_468_DATA */ 0x020000c0, /* DENALI_PHY_469_DATA */ 0x00100001, /* DENALI_PHY_470_DATA */ - 0x0c064208, /* DENALI_PHY_471_DATA */ + 0x07064208, /* DENALI_PHY_471_DATA */ 0x000f0c18, /* DENALI_PHY_472_DATA */ 0x01000140, /* DENALI_PHY_473_DATA */ 0x00000c20, /* DENALI_PHY_474_DATA */ diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9aa2952..9211895 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -580,10 +580,9 @@ static void check_write_leveling_value(u32 channel, const struct rk3399_sdram_params *sdram_params) { - u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; + u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; - u32 i, tmp; - u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; + u32 i, j; u32 wl_value[2][4]; u32 rank = sdram_params->ch[channel].rank; @@ -602,71 +601,43 @@ static void check_write_leveling_value(u32 channel, wl_value[i][3] = (read32(&denali_phy[447]) >> 16) & 0x3ff; } - for (i = 0; i < 4; i++) { - if (((wl_value[0][i] > 0x1E0) || (wl_value[0][i] < 0x20)) && - ((wl_value[1][i] > 0x1E0) || (wl_value[1][i] < 0x20))) { - switch (i) { - case 0: - setbits_le32(&denali_phy[79], 0x1 << 16); - break; - case 1: - setbits_le32(&denali_phy[207], 0x1 << 16); - break; - case 2: - setbits_le32(&denali_phy[335], 0x1 << 16); - break; - case 3: - setbits_le32(&denali_phy[463], 0x1 << 16); - break; - default: - break; - } - } - } + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 0 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 0 << 16); for (i = 0; i < rank; i++) { - - /* FIXME: denali_phy[463] value wrong if miss this delay */ - udelay(100); - - /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); - /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); - - select_per_cs_training_index(channel, i); - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:25 */ - tmp = read32(&denali_pi[174]) >> 8; - - /* - * check status obs, - * if error maybe can not get leveling done - * PHY_40/168/296/424 phy_wrlvl_status_obs_X:0:13 - */ - obs_0 = read32(&denali_phy[40]); - obs_1 = read32(&denali_phy[168]); - obs_2 = read32(&denali_phy[296]); - obs_3 = read32(&denali_phy[424]); - if (((obs_0 >> 12) & 0x1) || - ((obs_1 >> 12) & 0x1) || - ((obs_2 >> 12) & 0x1) || - ((obs_3 >> 12) & 0x1)) - obs_err = 1; - if ((((tmp >> 10) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) - break; - else if ((((tmp >> 4) & 0x1) == 0x1) || - (obs_err == 1)) - printk(BIOS_DEBUG, - "check_write_leveling_value error!!!\n"); + clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24); + clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24); + for (j = 0; j < 4; j++) { + if (wl_value[i][j] < 0x80) + clrsetbits_le32(&denali_phy[63+j*128], + 0x3ff << 16, + (wl_value[i][j]+0x200) << 16); + else if ((wl_value[i][j] >= 0x80) && + (wl_value[i][j] < 0x100)) + clrsetbits_le32(&denali_phy[78+j*128], + 0x7 << 8, 0x1 << 8); } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - write32((&denali_pi[175]), 0x00003f7c); } + + /* CTL_200 ctrlupd_req 1bit offset_8 */ + clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); } static int data_training(u32 channel,

1 0

Patch set updated for coreboot: rockchip/rk3399: Actually remove big CPU initialization from bootblock
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16769 -gerrit commit de0ae44aa394dc0c2feb2a2b108b444d247fbceb Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 23 16:07:42 2016 -0700 rockchip/rk3399: Actually remove big CPU initialization from bootblock CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h(a)gmx.de> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index b9de844..2596853 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -411,13 +411,6 @@ void rkclk_init(void) rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); - /* - * coreboot boot from little core, but it seem if apll_b use defalut - * 24MHz it will take a long time to enable big core, and will cause - * a watchdog crash, so we should do apll_b initialization here - */ - rkclk_configure_cpu(APLL_600_MHZ, true); - /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

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Patch set updated for coreboot: google/gru: pass the gpio power supply enable pin to bl31
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16719 -gerrit commit dad79ecd469d9f6de6fdb3d9fb6a9eea031f4941 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Aug 22 17:35:40 2016 -0700 google/gru: pass the gpio power supply enable pin to bl31 we need to disable some regulator when device into suspend, it mean we need to pass some gpio to bl31, and disable these gpios when bl31 run suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpio go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- 3rdparty/arm-trusted-firmware | 2 +- src/mainboard/google/gru/board.h | 3 +++ src/mainboard/google/gru/mainboard.c | 43 ++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index e4f51ee..bfd9251 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit e4f51eee91187e980f5e0e436c65f325fc35c94b +Subproject commit bfd925139fdbc2e87979849907b34843aa326994 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 382c462..7880cca 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -25,6 +25,9 @@ #define GPIO_POWEROFF GPIO(1, A, 6) #define GPIO_RESET GPIO(0, B, 3) #define GPIO_WP GPIO(1, C, 2) +#define GPIO_P15V_EN GPIO(0, B, 2) +#define GPIO_P30V_EN GPIO(0, B, 4) +#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 8359ca4..902228b 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,48 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_gpio_suspend(void) +{ + /* + * these 3 pin to disable gpio2 ~ gpio4 1.5v, 1.8v, 3.3v power supply + * so need to shut down the power supply from high voltage to + * low voltage, and consider register_bl31() appends to the front off + * the list, we should register 1.5v enable pin to 3.3v enable pin + */ + static struct bl31_gpio_param param_p15_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p15_en.gpio.index = GET_GPIO_NUM(GPIO_P15V_EN); + register_bl31_param(&param_p15_en.h); + + static struct bl31_gpio_param param_p18_audio_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p18_audio_en.gpio.index = GET_GPIO_NUM(GPIO_P18V_AUDIO_PWREN); + register_bl31_param(&param_p18_audio_en.h); + + static struct bl31_gpio_param param_p30_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p30_en.gpio.index = GET_GPIO_NUM(GPIO_P30V_EN); + register_bl31_param(&param_p30_en.h); +} + static void register_reset_to_bl31(void) { static struct bl31_gpio_param param_reset = { @@ -184,6 +226,7 @@ static void mainboard_init(device_t dev) setup_usb(); register_reset_to_bl31(); register_poweroff_to_bl31(); + register_gpio_suspend(); } static void enable_backlight_booster(void)

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Patch set updated for coreboot: soc/qualcomm/ipq40xx: Fix GPIO pull up config.
by Patrick Georgi 04 Oct '16

04 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16770 -gerrit commit 5227bb264230ec50855e5fe8f79444f86f1ce760 Author: Kan Yan <kyan(a)google.com> Date: Thu Sep 22 18:59:18 2016 -0700 soc/qualcomm/ipq40xx: Fix GPIO pull up config. BUG=b:31690391 TEST=Tested with board ID BRANCH=none Change-Id: I9a2b7eec111a79827f72a506942a8ec833ba7e60 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f23e2b6e72491aaafa15774f9bded3e14363abbc Original-Change-Id: I23183db29d7f7dd812e94ab6a1f2f1329c46ac60 Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388778 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj(a)chromium.org> --- src/soc/qualcomm/ipq40xx/include/soc/gpio.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h index 3f9c385..220ea93 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h @@ -48,8 +48,7 @@ /* GPIO TLMM: Pullup/Pulldown */ #define GPIO_NO_PULL 0 #define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 +#define GPIO_PULL_UP 2 /* GPIO TLMM: Drive Strength */ #define GPIO_2MA 0

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coreboot-gerrit October 2016