coreboot-gerrit January 2016

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Patch set updated for coreboot: intel/microcode: Move skylake's PRMRR check into mainline code
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854 -gerrit commit 5df2ca284c95aad52df63317588076fe78b25086 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 16:24:49 2016 -0700 intel/microcode: Move skylake's PRMRR check into mainline code Currently, the skylake build is breaking in ROMCC because of this code. Moving it into the mainline microcode patch location fixes the issue with romcc and cleans up the code path significantly. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/microcode/microcode.c | 11 +++++++++++ src/include/cpu/x86/mtrr.h | 1 + src/soc/intel/skylake/bootblock/cpu.c | 18 +----------------- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 35eff16..ada744e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -23,6 +23,7 @@ #endif #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> #include <rules.h> @@ -92,6 +93,16 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; + /* If PRMRR/SGX is supported the FIT microcode load step will set + * msr 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRR_CAP_MSR); + if ((msr.lo & MTRR_CAP_PRMRR) && (current_rev == m->rev - 1)) + return; + #if ENV_RAMSTAGE /*SoC specific check to update microcode*/ if (soc_skip_ucode_update(current_rev, m->rev)) { diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..950c7d4 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -11,6 +11,7 @@ #define MTRR_CAP_MSR 0x0fe +#define MTRR_CAP_PRMRR (1 << 12) #define MTRR_CAP_SMRR (1 << 11) #define MTRR_CAP_WC (1 << 10) #define MTRR_CAP_FIX (1 << 8) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d638..0f1bcd7 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -173,23 +173,7 @@ static void check_for_clean_reset(void) static void patch_microcode(void) { - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); + intel_update_microcode_from_cbfs(); } static void bootblock_cpu_init(void)

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New patch to review for coreboot: intel/microcode: Move skylake's PRMRR check into mainline code
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854 -gerrit commit 54a712e5ab4b5a756f51c3824acd9871015f4cbf Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 16:24:49 2016 -0700 intel/microcode: Move skylake's PRMRR check into mainline code Currently, the skylake build is breaking in ROMCC because of this code. Moving it into the mainline microcode patch location fixes the issue with romcc and cleans up the code path significantly. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/microcode/microcode.c | 11 +++++++++++ src/include/cpu/x86/mtrr.h | 1 + src/soc/intel/skylake/bootblock/cpu.c | 18 +----------------- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 35eff16..ada744e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -23,6 +23,7 @@ #endif #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> #include <rules.h> @@ -92,6 +93,16 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; + /* If PRMRR/SGX is supported the FIT microcode load step will set + * msr 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRR_CAP_MSR); + if ((msr.lo & MTRR_CAP_PRMRR) && (current_rev == m->rev - 1)) + return; + #if ENV_RAMSTAGE /*SoC specific check to update microcode*/ if (soc_skip_ucode_update(current_rev, m->rev)) { diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..950c7d4 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -11,6 +11,7 @@ #define MTRR_CAP_MSR 0x0fe +#define MTRR_CAP_PRMRR (1 << 12) #define MTRR_CAP_SMRR (1 << 11) #define MTRR_CAP_WC (1 << 10) #define MTRR_CAP_FIX (1 << 8) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d638..0f1bcd7 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -173,23 +173,7 @@ static void check_for_clean_reset(void) static void patch_microcode(void) { - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); + intel_update_microcode_from_cbfs(); } static void bootblock_cpu_init(void)

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Patch merged into coreboot/master: viatool: Add VIA C3 MSRs
by gerrit＠coreboot.org 06 Jan '16

06 Jan '16

the following patch was just integrated into master: commit b47dc52f30d5285f17e7e7456a09f512e815bcfc Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Wed Jan 6 19:26:26 2016 +0300 viatool: Add VIA C3 MSRs Tested on C3/EPIA board and Linux x86 Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925 Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> Reviewed-on: https://review.coreboot.org/12851 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12851 for details. -gerrit

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New patch to review for coreboot: buildgcc: Don't request that optional tools be installed
by Martin Roth 06 Jan '16

06 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12852 -gerrit commit 7c57767419097079900a29175533b6619d0f2f59 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 13:54:32 2016 -0700 buildgcc: Don't request that optional tools be installed Previously, when we tested for g++ and two different versions of clang, if the earlier versions were not found, buildgcc would still request that they be installed. This obviously isn't needed, and isn't the desired outcome. Now, if one of the first tests fails, nothing gets printed. If all the tests fail, it tells you to install either g++ or clang. Change-Id: I71359f59c4c6bee3c3c55e4e6105f11e6ca51527 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 31db9cb..5628a3a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -114,6 +114,9 @@ please_install() esac printf "${RED}ERROR:${red} Missing tool: Please install \'$1\' utility. (eg $solution)${NC}\n" >&2 + if [ -n "$2" ]; then + printf "${RED}ERROR:${red} or install \'$2\' utility. (eg $solution)${NC}\n" >&2 + fi } searchtool() @@ -121,6 +124,7 @@ searchtool() # $1 short name # $2 search string # $3 soft fail if set + # $4 alternative package to install on failure # result: file name of that tool on stdout # or no output if nothing suitable was found search=GNU @@ -166,8 +170,8 @@ searchtool() fi fi fi - please_install $1 - [ -z "$3" ] && exit 1 + + [ -z "$3" ] && please_install $1 $4 && exit 1 false } @@ -644,7 +648,7 @@ searchtool bison > /dev/null searchtool flex flex > /dev/null searchtool g++ "Free Software Foundation" nofail > /dev/null || \ searchtool clang "clang version" nofail > /dev/null || \ -searchtool clang "LLVM" > /dev/null +searchtool clang "LLVM" "" "g++" > /dev/null searchtool wget > /dev/null searchtool bzip2 "bzip2," > /dev/null

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Patch set updated for coreboot: viatool: add NetBSD support
by Andrey Korolyov 06 Jan '16

06 Jan '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12836 -gerrit commit 8a7448fcf5c89b2cd3da805d1f9491bb3e35ab7a Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Tue Jan 5 20:09:02 2016 +0300 viatool: add NetBSD support Change-Id: I033044e4b781475d6d60a49a61313a720103ce38 Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> --- util/viatool/Makefile | 8 ++++++++ util/viatool/viatool.c | 12 ++++++++++++ util/viatool/viatool.h | 25 +++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/util/viatool/Makefile b/util/viatool/Makefile index de3bfdd..4d9d0d0 100644 --- a/util/viatool/Makefile +++ b/util/viatool/Makefile @@ -40,6 +40,10 @@ CFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib LIBS = -lz endif +ifeq ($(OS_ARCH), NetBSD) +CFLAGS += -I/usr/pkg/include +LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib -lz -lpciutils -lpci -l$(shell uname -p) +endif all: pciutils dep $(PROGRAM) @@ -62,7 +66,11 @@ dep: define LIBPCI_TEST /* Avoid a failing test due to libpci header symbol shadowing breakage */ #define index shadow_workaround_index +#ifdef __NetBSD__ +#include <pciutils/pci.h> +#else #include <pci/pci.h> +#endif struct pci_access *pacc; int main(int argc, char **argv) { diff --git a/util/viatool/viatool.c b/util/viatool/viatool.c index 0fde455..c19647f 100644 --- a/util/viatool/viatool.c +++ b/util/viatool/viatool.c @@ -25,6 +25,10 @@ #include <unistd.h> #include "viatool.h" +#ifdef __NetBSD__ +#include <machine/sysarch.h> +#endif + /* * http://pci-ids.ucw.cz/read/PC/8086 * http://en.wikipedia.org/wiki/Intel_Tick-Tock @@ -146,6 +150,14 @@ int main(int argc, char *argv[]) #if defined(__FreeBSD__) if (open("/dev/io", O_RDWR) < 0) { perror("/dev/io"); +#elif defined(__NetBSD__) +# ifdef __i386__ + if (i386_iopl(3)) { + perror("iopl"); +# else + if (x86_64_iopl(3)) { + perror("iopl"); +# endif #else if (iopl(3)) { perror("iopl"); diff --git a/util/viatool/viatool.h b/util/viatool/viatool.h index a0a5d79..3a6f048 100644 --- a/util/viatool/viatool.h +++ b/util/viatool/viatool.h @@ -28,13 +28,38 @@ #define __DARWIN__ #include <DirectHW/DirectHW.h> #endif +#ifdef __NetBSD__ +#include <pciutils/pci.h> +#else #include <pci/pci.h> +#endif /* This #include is needed for freebsd_{rd,wr}msr. */ #if defined(__FreeBSD__) #include <machine/cpufunc.h> #endif +#ifdef __NetBSD__ +static inline uint8_t inb(unsigned port) +{ + uint8_t data; + __asm volatile("inb %w1,%0" : "=a" (data) : "d" (port)); + return data; +} +static inline uint16_t inw(unsigned port) +{ + uint16_t data; + __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); + return data; +} +static inline uint32_t inl(unsigned port) +{ + uint32_t data; + __asm volatile("inl %w1,%0": "=a" (data) : "d" (port)); + return data; +} +#endif + #include <stdlib.h> #define VIATOOL_VERSION "1.0"

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Patch set updated for coreboot: viatool: Add VIA C3 MSRs
by Andrey Korolyov 06 Jan '16

06 Jan '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12851 -gerrit commit cd76fc6337cf487a64297cca2fff3f2a53db66f6 Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Wed Jan 6 19:26:26 2016 +0300 viatool: Add VIA C3 MSRs Tested on C3/EPIA board and Linux x86 Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925 Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> --- util/viatool/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/util/viatool/cpu.c b/util/viatool/cpu.c index 9aaa050..4bf1271 100644 --- a/util/viatool/cpu.c +++ b/util/viatool/cpu.c @@ -185,6 +185,48 @@ int print_intel_core_msrs(void) //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO }; + /* VIA C3 Nehemiah */ + static const msr_entry_t model69x_global_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x002a, "EBL_CR_POWERON" }, + { 0x00c1, "PERFCTR0" }, + { 0x00c2, "PERFCTR1" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0186, "EVNTSEL0" }, + { 0x0187, "EVNTSEL1" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x1107, "FCR" }, + { 0x1108, "FCR2" }, +// WRITE ONLY { 0x1109, "FCR3" }, + }; + static const msr_entry_t model6bx_global_msrs[] = { { 0x0010, "IA32_TIME_STAMP_COUNTER" }, { 0x0017, "IA32_PLATFORM_ID" }, @@ -894,6 +936,7 @@ int print_intel_core_msrs(void) cpu_t cpulist[] = { { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, + { 0x00690, model69x_global_msrs, ARRAY_SIZE(model69x_global_msrs), NULL, 0 }, { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },

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Patch merged into coreboot/master: cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
by gerrit＠coreboot.org 06 Jan '16

06 Jan '16

the following patch was just integrated into master: commit bfa19e1e47e7f383a45c9e6955c7968c3b926540 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jan 5 11:00:49 2016 -0600 cpu/amd/fam10h-15h: Add tsc_freq_mhz() function The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/12834 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: correct add-master-header logic to match runtime expectations
by gerrit＠coreboot.org 06 Jan '16

06 Jan '16

the following patch was just integrated into master: commit bb826ef661f7ff390e284bcae6b0b330ca48ceb3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 4 13:56:00 2016 -0600 cbfstool: correct add-master-header logic to match runtime expectations The cbfs master header's offset and romsize fields are absolute values within the boot media proper. Therefore, when adding a master header provide the offset of the CBFS region one is operating on as well as the absolute end offset (romsize) to match expectations. Built with and without CBFS_SIZE != ROM_SIZE on x86 and ARM device. Manually inspected the master headers within the images to confirm proper caclulations. Change-Id: Id0623fd713ee7a481ce3326f4770c81beda20f64 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/12825 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/12825 for details. -gerrit

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Patch merged into coreboot/master: Revert "x86: Align CBFS on top of ROM"
by gerrit＠coreboot.org 06 Jan '16

06 Jan '16

the following patch was just integrated into master: commit 12c55eda11453ed1e7a24e218338831f67cd5de6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 4 13:57:07 2016 -0600 Revert "x86: Align CBFS on top of ROM" This reverts commit 65e33c08a9a88c52baaadaf515b9591856115a77. This was the wrong logic to fix the master header. Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/12824 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12824 for details. -gerrit

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Patch merged into coreboot/master: intel/braswell: Build in both C0 and 'other' vbios
by gerrit＠coreboot.org 06 Jan '16

06 Jan '16

the following patch was just integrated into master: commit f812c44f003a1ba34548d1eceb622221d95a5945 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 4 12:43:22 2016 -0700 intel/braswell: Build in both C0 and 'other' vbios The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12826 for details. -gerrit

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coreboot-gerrit January 2016