coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Drop abuild.disabled files for Skylake boards
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12857 -gerrit commit be6cb3ff4849f11a03f9b83a2c59fae0a4d43f49 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 Drop abuild.disabled files for Skylake boards Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- src/mainboard/intel/sklrvp/abuild.disabled | 2 -- 5 files changed, 10 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel.

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New patch to review for coreboot: intel/skylake: Init variable so GCC knows it's set
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12860 -gerrit commit d86365d810f0f4326ad513470034016befbe79e9 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 15:35:45 2016 -0700 intel/skylake: Init variable so GCC knows it's set Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/skylake/pcr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 7efbb25..9c5a5a2 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -158,7 +158,7 @@ static int pcr_and_then_or(u8 pid, u16 offset, u32 size, u32 anddata, u32 ordata) { u8 status; - u32 data32; + u32 data32 = 0; status = pch_pcr_read(pid, offset, size, &data32); if (status != 0)

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New patch to review for coreboot: fsp1_1: Remove #if protection in header - It's not needed
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12859 -gerrit commit b5a9376c447a500bd9f478a7dab59ab8f9ecd2b4 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 15:33:38 2016 -0700 fsp1_1: Remove #if protection in header - It's not needed There's nothing in these files that needs to be hidden if GOP support is disabled. Removing this allows skylake to build when GOP support is turned off. Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/intel/fsp1_1/include/fsp/gop.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h index 8277a23..29d6a6c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/gop.h +++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h @@ -16,12 +16,8 @@ #ifndef _FSP1_1_GOP_H_ #define _FSP1_1_GOP_H_ -/* GOP support */ -#if IS_ENABLED(CONFIG_GOP_SUPPORT) - #include <fsp/gma.h> const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); -#endif /* CONFIG_GOP_SUPPORT */ #endif /* _FSP_GOP_H_ */

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Patch set updated for coreboot: intel/microcode: Move skylake's PRMRR check into mainline code
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854 -gerrit commit 81525dbd5d36129c428f013682ab3a485d63be4f Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 16:24:49 2016 -0700 intel/microcode: Move skylake's PRMRR check into mainline code Currently, the skylake build is breaking in ROMCC because of this code. Moving it into the mainline microcode patch location fixes the issue with romcc and cleans up the code path significantly. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/microcode/microcode.c | 11 +++++++++++ src/include/cpu/x86/mtrr.h | 1 + src/soc/intel/skylake/bootblock/cpu.c | 18 +----------------- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 35eff16..ada744e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -23,6 +23,7 @@ #endif #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> #include <rules.h> @@ -92,6 +93,16 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; + /* If PRMRR/SGX is supported the FIT microcode load step will set + * msr 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRR_CAP_MSR); + if ((msr.lo & MTRR_CAP_PRMRR) && (current_rev == m->rev - 1)) + return; + #if ENV_RAMSTAGE /*SoC specific check to update microcode*/ if (soc_skip_ucode_update(current_rev, m->rev)) { diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..950c7d4 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -11,6 +11,7 @@ #define MTRR_CAP_MSR 0x0fe +#define MTRR_CAP_PRMRR (1 << 12) #define MTRR_CAP_SMRR (1 << 11) #define MTRR_CAP_WC (1 << 10) #define MTRR_CAP_FIX (1 << 8) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d638..0f1bcd7 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -173,23 +173,7 @@ static void check_for_clean_reset(void) static void patch_microcode(void) { - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); + intel_update_microcode_from_cbfs(); } static void bootblock_cpu_init(void)

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Patch set updated for coreboot: intel/skylake: Remove check for Microcode loaded by ME
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854 -gerrit commit 237c8541503dd04a244ebb5e5124bcd188dd4c28 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 16:24:49 2016 -0700 intel/skylake: Remove check for Microcode loaded by ME This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/skylake/bootblock/cpu.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d638..6fc4d92 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -171,32 +171,11 @@ static void check_for_clean_reset(void) soft_reset(); } -static void patch_microcode(void) -{ - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); -} - static void bootblock_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - patch_microcode(); + intel_update_microcode_from_cbfs(); }

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Patch merged into coreboot/master: intel/braswell: Disable IFD & ME by default so abuild can build
by gerrit＠coreboot.org 07 Jan '16

07 Jan '16

the following patch was just integrated into master: commit 481a19cf99a9736c089320df33d3248522e0efc9 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 4 14:23:53 2016 -0700 intel/braswell: Disable IFD & ME by default so abuild can build The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12828 for details. -gerrit

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Patch merged into coreboot/master: mainboard: Drop abuild.disabled files for Braswell boards
by gerrit＠coreboot.org 07 Jan '16

07 Jan '16

the following patch was just integrated into master: commit 9dbdf520d8c3bc7bea3a4565206525f85ddc631f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 mainboard: Drop abuild.disabled files for Braswell boards Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/12463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12463 for details. -gerrit

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Patch set updated for coreboot: mainboard: Drop abuild.disabled files for Braswell boards
by Stefan Reinauer 07 Jan '16

07 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12463 -gerrit commit 94e296b24586ecf33501d30ec682961951dc8007 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 mainboard: Drop abuild.disabled files for Braswell boards Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/google/cyan/abuild.disabled | 2 -- src/mainboard/intel/strago/abuild.disabled | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/mainboard/google/cyan/abuild.disabled b/src/mainboard/google/cyan/abuild.disabled deleted file mode 100644 index 025ebea..0000000 --- a/src/mainboard/google/cyan/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Braswell FSP binary and header -files along with the Braswell microcode files from Intel. diff --git a/src/mainboard/intel/strago/abuild.disabled b/src/mainboard/intel/strago/abuild.disabled deleted file mode 100644 index 025ebea..0000000 --- a/src/mainboard/intel/strago/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Braswell FSP binary and header -files along with the Braswell microcode files from Intel.

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Patch merged into coreboot/master: buildgcc: Don't request that optional tools be installed
by gerrit＠coreboot.org 07 Jan '16

07 Jan '16

the following patch was just integrated into master: commit e396317244191df506bb2b566f91a518b639f213 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 13:54:32 2016 -0700 buildgcc: Don't request that optional tools be installed Previously, when we tested for g++ and two different versions of clang, if the earlier versions were not found, buildgcc would still request that they be installed. This obviously isn't needed, and isn't the desired outcome. Now, if one of the first tests fails, nothing gets printed. If all the tests fail, it tells you to install either g++ or clang. Change-Id: I71359f59c4c6bee3c3c55e4e6105f11e6ca51527 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12852 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12852 for details. -gerrit

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New patch to review for coreboot: xcompile: More updates on ARM64 Erratum flags
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12858 -gerrit commit f0215c0669decb3b7a099d2b5459ece89d758885 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 14:57:26 2016 -0700 xcompile: More updates on ARM64 Erratum flags I tried to handle the checking for the config flag internal to xcompile, but the config flags don't appear to have been loaded into the environment by make at that point. This does update the if to check if the flag is even set before putting anything into .xcompile though. If the LDFLAG isn't set, there's no point in appending anything. Also removes the LP version of the erratum config flag, which was a copy/paste mistake from $(CONFIG_LP_COMPILER_GCC). Change-Id: I3d8b0328c85310393a120741a498bc18867a6f54 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/xcompile/xcompile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index b3dd074..a1856e4 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -231,15 +231,16 @@ AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} EOF - if [ "${TARCH}" = "arm64" ]; then - cat <<EOF + if [ "${TARCH}" = "arm64" ] && \ + [ -n "${LDFLAGS_ARM64_A53_ERRATUM_843419}" ]; then + cat <<EOF -ifeq (\$(CONFIG_ARM64_A53_ERRATUM_843419)\$(CONFIG_LP_ARM64_A53_ERRATUM_843419),y) +ifeq (\$(CONFIG_ARM64_A53_ERRATUM_843419),y) LD_${TARCH}+=${LDFLAGS_ARM64_A53_ERRATUM_843419} endif EOF - fi # if [ "${TARCH}" = "arm64" ] + fi # if [ "${TARCH}" = "arm64" ]... cat <<EOF NM_${TARCH}:=${GCCPREFIX}nm

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coreboot-gerrit January 2016