coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard: Drop abuild.disabled files for Skylake boards
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12857 -gerrit commit 660f5dc0b053a27f009e0eb3898fdfec84372e0a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 mainboard: Drop abuild.disabled files for Skylake boards Make sure the latest & greatest Intel targets actually build in our build system. intel/sklrvp is still failing for reasons unrelated to the rest of the skylake boards. Leaving that disabled for now. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- 4 files changed, 8 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel.

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Patch set updated for coreboot: intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in Kconfig
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12865 -gerrit commit fb009dc4c5cb9b8295cc56206e80bf433a1f95e5 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 16:25:39 2016 -0700 intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in Kconfig Because these platforms haven't been getting build testing, they've missed out on some of the improvements that the other platforms have gotten. Enable MAINBOARD_HAS_LPC_TPM so that they will build. Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/lars/Kconfig | 1 + src/mainboard/intel/kunimitsu/Kconfig | 1 + src/mainboard/intel/sklrvp/Kconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 58391ae..94ec30f 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 81c18f5..6dabee6 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index e6dd86b..0872aac 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select PCIEXP_L1_SUB_STATE

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New patch to review for coreboot: intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in Kconfig
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12865 -gerrit commit e8b03c0a43a12949ee8ee333979cf24dff7371ca Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 16:25:39 2016 -0700 intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in Kconfig Because these platforms haven't been getting build testing, they've missed out on some of the improvements that the other platforms have gotten. Enable MAINBOARD_HAS_LPC_TPM so that they will build. Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/lars/Kconfig | 1 + src/mainboard/intel/kunimitsu/Kconfig | 1 + src/mainboard/intel/sklrvp/Kconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 58391ae..94ec30f 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 81c18f5..6dabee6 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index e6dd86b..0872aac 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select PCIEXP_L1_SUB_STATE

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Patch set updated for coreboot: mainboard: Drop abuild.disabled files for Skylake boards
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12857 -gerrit commit 5763be07871a1ab2ad37792a93d59c918d8b95c4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 mainboard: Drop abuild.disabled files for Skylake boards Make sure the latest & greatest Intel targets actually build in our build system. intel/sklrvp is still failing for reasons unrelated to the rest of the skylake boards. Leaving that disabled for now. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- 4 files changed, 8 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel.

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Patch set updated for coreboot: mainboard: Drop abuild.disabled files for Skylake boards
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12857 -gerrit commit 27b98d54ddd16193a0ef1274db8c6a3796127229 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 mainboard: Drop abuild.disabled files for Skylake boards Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- src/mainboard/intel/sklrvp/abuild.disabled | 2 -- 5 files changed, 10 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel.

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Patch set updated for coreboot: intel/skylake: Init variable so GCC knows it's set
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12860 -gerrit commit 728a11ecaa031533db9fc4383df7b5db0f5920fd Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 15:35:45 2016 -0700 intel/skylake: Init variable so GCC knows it's set Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/skylake/pcr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 7efbb25..9c5a5a2 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -158,7 +158,7 @@ static int pcr_and_then_or(u8 pid, u16 offset, u32 size, u32 anddata, u32 ordata) { u8 status; - u32 data32; + u32 data32 = 0; status = pch_pcr_read(pid, offset, size, &data32); if (status != 0)

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Patch set updated for coreboot: fsp1_1: Remove #if protection in header - It's not needed
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12859 -gerrit commit a7305b96a2844ca2836f6cd7aa48df5c595a1097 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 15:33:38 2016 -0700 fsp1_1: Remove #if protection in header - It's not needed There's nothing in these files that needs to be hidden if GOP support is disabled. Removing this allows skylake to build when GOP support is turned off. Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/intel/fsp1_1/include/fsp/gop.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h index 8277a23..29d6a6c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/gop.h +++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h @@ -16,12 +16,8 @@ #ifndef _FSP1_1_GOP_H_ #define _FSP1_1_GOP_H_ -/* GOP support */ -#if IS_ENABLED(CONFIG_GOP_SUPPORT) - #include <fsp/gma.h> const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); -#endif /* CONFIG_GOP_SUPPORT */ #endif /* _FSP_GOP_H_ */

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Patch set updated for coreboot: intel/microcode: Move skylake's PRMRR check into mainline code
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854 -gerrit commit 8f6d35b0397ceacfac6bb1f23ad7051f83fdc5cc Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 16:24:49 2016 -0700 intel/microcode: Move skylake's PRMRR check into mainline code Currently, the skylake build is breaking in ROMCC because of this code. Moving it into the mainline microcode patch location fixes the issue with romcc and cleans up the code path significantly. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/microcode/microcode.c | 11 +++++++++++ src/include/cpu/x86/mtrr.h | 1 + src/soc/intel/skylake/bootblock/cpu.c | 18 +----------------- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 35eff16..ada744e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -23,6 +23,7 @@ #endif #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> #include <rules.h> @@ -92,6 +93,16 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; + /* If PRMRR/SGX is supported the FIT microcode load step will set + * msr 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRR_CAP_MSR); + if ((msr.lo & MTRR_CAP_PRMRR) && (current_rev == m->rev - 1)) + return; + #if ENV_RAMSTAGE /*SoC specific check to update microcode*/ if (soc_skip_ucode_update(current_rev, m->rev)) { diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8fd4261..950c7d4 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -11,6 +11,7 @@ #define MTRR_CAP_MSR 0x0fe +#define MTRR_CAP_PRMRR (1 << 12) #define MTRR_CAP_SMRR (1 << 11) #define MTRR_CAP_WC (1 << 10) #define MTRR_CAP_FIX (1 << 8) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d638..0f1bcd7 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -173,23 +173,7 @@ static void check_for_clean_reset(void) static void patch_microcode(void) { - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); + intel_update_microcode_from_cbfs(); } static void bootblock_cpu_init(void)

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Patch set updated for coreboot: mainboard: Drop abuild.disabled files for Skylake boards
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12857 -gerrit commit df4d50ed88087c61b2087e0c4851dce530e54bde Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 mainboard: Drop abuild.disabled files for Skylake boards Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/chell/abuild.disabled | 2 -- src/mainboard/google/glados/abuild.disabled | 2 -- src/mainboard/google/lars/abuild.disabled | 2 -- src/mainboard/intel/kunimitsu/abuild.disabled | 2 -- src/mainboard/intel/sklrvp/abuild.disabled | 2 -- 5 files changed, 10 deletions(-) diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/chell/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/glados/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/google/lars/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/kunimitsu/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel.

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Patch set updated for coreboot: Chromeos: Implement wifi_regulatory_domain using "regions" key in VPD
by Martin Roth 07 Jan '16

07 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12743 -gerrit commit 296c85f31cba9e3191f3d052c9fcbc120bdff7d3 Author: Felix Durairaj <felixx.durairaj(a)intel.com> Date: Fri Nov 20 16:18:42 2015 -0800 Chromeos: Implement wifi_regulatory_domain using "regions" key in VPD Implement wifi_regulatory_domain function by getting country code from VPD CQ-DEPEND=CL:12744 Reviewed-on: https://chromium-review.googlesource.com/314385 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Ia6a24df110a3860d404d345571007ae8965e9564 Signed-off-by: fdurairx <felixx.durairaj(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/cros_vpd.h | 2 + src/vendorcode/google/chromeos/wrdd.c | 76 +++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 00fcd2f..adb51b4 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -38,6 +38,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c +ramstage-y += wrdd.c ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c ramstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index 19658c2..ca9c320 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -7,6 +7,8 @@ #ifndef __CROS_VPD_H__ #define __CROS_VPD_H__ +#define CROS_VPD_WIFI_DOMAINKEY "regions" + /* * Reads VPD string value by key. * diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c new file mode 100644 index 0000000..ab27cc0 --- /dev/null +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <cpu/cpu.h> +#include <types.h> +#include <string.h> +#include <wrdd.h> +#include "cros_vpd.h" + +/* + * wrdd_domain_value is ISO 3166-2 + * ISO 3166-2 code consists of two parts, separated by a hyphen + * The first part is the ISO 3166-1 alpha-2 code of the country; + * The second part is a string of up to three alphanumeric characters + */ +struct wrdd_code_value_pair { + const char *code; + u16 value; +}; + +/* Retrieve the regulatory domain information from VPD and + * return it as an uint16. + * WARNING: if domain information is not found in the VPD, + * this function will fall back to the default value + */ +uint16_t wifi_regulatory_domain(void) +{ + static struct wrdd_code_value_pair wrdd_table[] = { + { + /* Indonesia + * Alpha-2 code 'ID' + * Full name 'the Republic of Indonesia' + * Alpha-3 code 'IDN' + * Numeric code '360' + */ + .code = "id", + .value = WRDD_REGULATORY_DOMAIN_INDONESIA + } + }; + const char *wrdd_domain_key = CROS_VPD_WIFI_DOMAINKEY; + int i; + struct wrdd_code_value_pair *p; + /* wrdd_domain_value is ISO 3166-2 */ + char wrdd_domain_code[7]; + + /* If not found for any reason fall backto the default value */ + if (!cros_vpd_gets(wrdd_domain_key, wrdd_domain_code, + sizeof(wrdd_domain_code))) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", wrdd_domain_key); + return WRDD_DEFAULT_REGULATORY_DOMAIN; + } + printk(BIOS_DEBUG, "Found '%s'='%s' in VPD\n", + wrdd_domain_key, wrdd_domain_code); + + for (i = 0; i < ARRAY_SIZE(wrdd_table); i++) { + p = &wrdd_table[i]; + if (strncmp(p->code, wrdd_domain_code, + ARRAY_SIZE(wrdd_domain_code)) == 0) + return p->value; + } + return WRDD_DEFAULT_REGULATORY_DOMAIN; +}

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coreboot-gerrit January 2016