coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltage
by gerrit＠coreboot.org 08 Jan '16

08 Jan '16

the following patch was just integrated into master: commit fecc24af049bfec00efce49858e228dd9ab2d11c Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 21:18:21 2016 -0700 vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltage I think this has a fairly low likelyhood of happening, but if AGESA can't determine the voltage of the memory, it assignes a value of 255 to the variable that it later uses to read from an 3-value array. There is an assert, but that doesn't halt AGESA, so it would use some random value. If the voltage can't be determined, fall back to 1.5v as the default value. Fixes coverity warning 1294803 - Out-of-bounds read Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12855 for details. -gerrit

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Patch set updated for coreboot: superiotool: fix out-of-box NetBSD Makefile support
by Andrey Korolyov 08 Jan '16

08 Jan '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12830 -gerrit commit c267a006d17e5d59abda57e077b52c644deb717e Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Mon Jan 4 02:20:04 2016 +0300 superiotool: fix out-of-box NetBSD Makefile support Add NetBSD-specific locations under pkg/ and missing linker flag for libpciutils. Change-Id: I812817a374aaba561b28d8a22f20d238c9dca32b Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> --- util/superiotool/Makefile | 9 +++++++-- util/superiotool/superiotool.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index cf487dc..5507813 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -43,7 +43,9 @@ LDFLAGS += -L/usr/local/lib LIBS = -lz endif ifeq ($(OS_ARCH), NetBSD) -LDFLAGS = -l$(shell uname -p) +CFLAGS += -I/usr/pkg/include +LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib +LIBS = -lz -l$(shell uname -p) endif # Support for PCI-attached "Super I/Os" (e.g. in VIA VT82686A/B). @@ -51,8 +53,11 @@ CONFIG_PCI = yes ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT -LIBS += -lpci OBJS += pci.o via.o amd.o +LIBS += -lpci + ifeq ($(OS_ARCH),NetBSD) + LIBS += -lpciutils + endif endif all: $(PROGRAM) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index cc87a0f..443cc07 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -34,7 +34,11 @@ #endif #ifdef PCI_SUPPORT +# ifdef __NetBSD__ +#include <pciutils/pci.h> +# else #include <pci/pci.h> +# endif #endif #if defined(__FreeBSD__)

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Patch set updated for coreboot: superiotool: fix out-of-box NetBSD Makefile support
by Andrey Korolyov 08 Jan '16

08 Jan '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12830 -gerrit commit 9619403513e3b66ef255873803f549d4c2e3df55 Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Mon Jan 4 02:20:04 2016 +0300 superiotool: fix out-of-box NetBSD Makefile support Add NetBSD-specific locations under pkg/ and missing linker flag for libpciutils. Change-Id: I812817a374aaba561b28d8a22f20d238c9dca32b Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> --- util/superiotool/Makefile | 10 ++++++++-- util/superiotool/superiotool.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index cf487dc..0e69176 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -43,7 +43,9 @@ LDFLAGS += -L/usr/local/lib LIBS = -lz endif ifeq ($(OS_ARCH), NetBSD) -LDFLAGS = -l$(shell uname -p) +CFLAGS += -I/usr/pkg/include +LDFLAGS += -L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib +LIBS = -lz -l$(shell uname -p) endif # Support for PCI-attached "Super I/Os" (e.g. in VIA VT82686A/B). @@ -51,8 +53,12 @@ CONFIG_PCI = yes ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT -LIBS += -lpci OBJS += pci.o via.o amd.o + ifeq ($(OS_ARCH),NetBSD) + LIBS += -lpciutils -lpci + else + LIBS += -lpci + endif endif all: $(PROGRAM) diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index cc87a0f..443cc07 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -34,7 +34,11 @@ #endif #ifdef PCI_SUPPORT +# ifdef __NetBSD__ +#include <pciutils/pci.h> +# else #include <pci/pci.h> +# endif #endif #if defined(__FreeBSD__)

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Patch set updated for coreboot: ectool: fix NetBSD compilation
by Andrey Korolyov 08 Jan '16

08 Jan '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12831 -gerrit commit 8a7900afdba8ce106baa884794736448147a3722 Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Tue Jan 5 14:27:59 2016 +0300 ectool: fix NetBSD compilation Since NetBSD does not support uname -o, push check for CygWin inside separate non-failing condition in Makefile. Change-Id: Ibd264384f49b33412f0ef8554bd9c9fb8f60a892 Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> --- util/ectool/Makefile | 8 ++++++-- util/ectool/ec.c | 16 ++++++++++++++++ util/ectool/ectool.c | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/util/ectool/Makefile b/util/ectool/Makefile index a869577..8aa1415 100644 --- a/util/ectool/Makefile +++ b/util/ectool/Makefile @@ -19,12 +19,16 @@ CFLAGS = -O2 -Wall -W PROGRAM = ectool INSTALL = /usr/bin/install PREFIX = /usr/local +OS_ARCH = $(shell uname) -OS_ARCH = $(shell uname -o) -ifeq ($(OS_ARCH), Cygwin) +ifeq ($(shell uname -o 2>/dev/null), Cygwin) LDFLAGS = -lioperm endif +ifeq ($(OS_ARCH), NetBSD) +LDFLAGS = -l$(shell uname -p) +endif + all: $(PROGRAM) $(PROGRAM): ec.o ectool.o diff --git a/util/ectool/ec.c b/util/ectool/ec.c index 406cc41..098e812 100644 --- a/util/ectool/ec.c +++ b/util/ectool/ec.c @@ -17,9 +17,25 @@ #include <stdint.h> #include <stdlib.h> #include <unistd.h> +#ifndef __NetBSD__ #include <sys/io.h> +#endif #include "ec.h" +#ifdef __NetBSD__ +#include <machine/sysarch.h> +static uint8_t inb(unsigned port) +{ + uint8_t data; + __asm volatile("inb %w1,%0" : "=a" (data) : "d" (port)); + return data; +} +static __inline void outb(uint8_t data, unsigned port) +{ + __asm volatile("outb %0,%w1" : : "a" (data), "d" (port)); +} +#endif + extern int verbose; #define debug(x...) if (verbose) printf(x) diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index 4639c4e..623bc09 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -18,10 +18,17 @@ #include <stdlib.h> #include <unistd.h> #include <getopt.h> +#ifndef __NetBSD__ #include <sys/io.h> +#endif #include <ec.h> #include <stdlib.h> +#ifdef __NetBSD__ +#include <machine/sysarch.h> +#endif + + #define ECTOOL_VERSION "0.1" void print_version(void) @@ -108,7 +115,15 @@ int main(int argc, char *argv[]) } } +#ifdef __NetBSD__ +# ifdef __i386__ + if (i386_iopl(3)) { +# else + if (x86_64_iopl(3)) { +# endif +#else if (iopl(3)) { +#endif printf("You need to be root.\n"); exit(1); }

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New patch to review for coreboot: arch/x86/include: Rename bootblock_common to bootblock_romcc.h
by Alexandru Gagniuc 08 Jan '16

08 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12867 -gerrit commit 016d72ac324cd9bdf4950a7432f037ac3486ac45 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 7 19:10:24 2016 -0800 arch/x86/include: Rename bootblock_common to bootblock_romcc.h This header is only used for the bootblock compiled with ROMCC. As the follow-on patches introduce a bootblock which does not make use of ROMCC, rename this header to prevent confusion. Change-Id: Id29c5bc6928c11cc7cb922fcfac71e5a3dcd113c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/bootblock_normal.c | 2 +- src/arch/x86/bootblock_simple.c | 2 +- src/arch/x86/include/arch/bootblock_common.h | 77 ---------------------------- src/arch/x86/include/arch/bootblock_romcc.h | 77 ++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 79 deletions(-) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index a6a877c..061e3cb 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_romcc.h> #include <pc80/mc146818rtc.h> #include <halt.h> diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index 4bff360..b5eb414 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_romcc.h> #include <halt.h> static void main(unsigned long bist) diff --git a/src/arch/x86/include/arch/bootblock_common.h b/src/arch/x86/include/arch/bootblock_common.h deleted file mode 100644 index 939ba08..0000000 --- a/src/arch/x86/include/arch/bootblock_common.h +++ /dev/null @@ -1,77 +0,0 @@ -#include <arch/cbfs.h> -#include <cpu/x86/lapic/boot_cpu.c> -#include <pc80/mc146818rtc.h> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif - -#if CONFIG_USE_OPTION_TABLE -static void sanitize_cmos(void) -{ - if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { - unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); - if (cmos_default) { - int i; - cmos_disable_rtc(); - for (i = 14; i < 128; i++) { - cmos_write_inner(cmos_default[i], i); - } - cmos_enable_rtc(); - } - } -} -#endif - -#if CONFIG_CMOS_POST -static void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG_CMOS_POST_EXTRA - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} -#endif diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h new file mode 100644 index 0000000..939ba08 --- /dev/null +++ b/src/arch/x86/include/arch/bootblock_romcc.h @@ -0,0 +1,77 @@ +#include <arch/cbfs.h> +#include <cpu/x86/lapic/boot_cpu.c> +#include <pc80/mc146818rtc.h> + +#ifdef CONFIG_BOOTBLOCK_RESETS +#include CONFIG_BOOTBLOCK_RESETS +#endif + +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#endif + +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) +{ +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT + bootblock_northbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT + bootblock_southbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_CPU_INIT + bootblock_cpu_init(); +#endif +} +#endif + +#if CONFIG_USE_OPTION_TABLE +static void sanitize_cmos(void) +{ + if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { + unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); + if (cmos_default) { + int i; + cmos_disable_rtc(); + for (i = 14; i < 128; i++) { + cmos_write_inner(cmos_default[i], i); + } + cmos_enable_rtc(); + } + } +} +#endif + +#if CONFIG_CMOS_POST +static void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG_CMOS_POST_EXTRA + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} +#endif

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Patch set updated for coreboot: cpu/qemu-x86: Run a C environment in the bootblock
by Alexandru Gagniuc 08 Jan '16

08 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11858 -gerrit commit 87d6a3cd0f79223d1bb4385c84a92ddfba4985ef Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Oct 10 16:35:58 2015 -0700 cpu/qemu-x86: Run a C environment in the bootblock Make use of the ROMCC-less bootblock introduced earlier. The "qemu" cpu is particularly easy because it does not require CAR setup. Change-Id: Idf161d363d2daf3c55454d376ca42d492463971a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/Kconfig | 2 +- src/cpu/qemu-x86/Makefile.inc | 1 + src/cpu/qemu-x86/bootblock.S | 48 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ea2bc46..f956de5 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,4 +19,4 @@ config CPU_QEMU_X86 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP + select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index b5f8369..ef94a52 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -12,6 +12,7 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.S ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic diff --git a/src/cpu/qemu-x86/bootblock.S b/src/cpu/qemu-x86/bootblock.S new file mode 100644 index 0000000..6e1cd2e --- /dev/null +++ b/src/cpu/qemu-x86/bootblock.S @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/post_codes.h> + +#define STACK_SIZE 0x10000 +#define STACK_BASE 0xd0000 + +.intel_syntax noprefix + +#define post_code(code) \ + mov eax, code; \ + out 0x80, eax + +.global bootblock_pre_c_entry + +.section .text +bootblock_pre_c_entry: + + /* Set up a stack */ + mov esp, (STACK_BASE + STACK_SIZE - 4) + + /* + * We have the following values saved from earlier: + * mm0: BIST result + * mm1: TSC timestamp low 32 bits + * mm2: TSC timestamp high 32 bits + */ + movd eax, mm2 + push eax + movd eax, mm1 + push eax + movd eax, mm0 + push eax + call bootblock_main + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever

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Patch set updated for coreboot: arch/x86: Allow boot flow which runs CAR setup in bootblock
by Alexandru Gagniuc 08 Jan '16

08 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11784 -gerrit commit 38dc37615529a2954351395e61f6892b310fb221 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:42:26 2015 -0700 arch/x86: Allow boot flow which runs CAR setup in bootblock Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Kconfig | 7 +++++ src/arch/x86/Makefile.inc | 17 +++++++++--- src/arch/x86/bootblock.S | 40 --------------------------- src/arch/x86/bootblock.c | 60 ++++++++++++++++++++++++++++++++++++++++ src/arch/x86/bootblock_legacy.S | 53 +++++++++++++++++++++++++++++++++++ src/arch/x86/bootblock_modern.S | 56 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/bootblock.h | 19 +++++++++++++ 7 files changed, 208 insertions(+), 44 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 738e7d1..28ec524 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -58,6 +58,13 @@ config ARCH_RAMSTAGE_X86_64 bool default n +# This is a new bootflow, in which a C environment is available in the +# bootblock. That can be achieved either by performing CAR setup is in the +# bootblock, or using memory available at boot-time (e.g. SRAM) +config C_ENVIRONMENT_BOOTBLOCK + bool + default n + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9713d52..6ed8a26 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -68,16 +68,15 @@ else LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 endif +bootblock-y += memcpy.c +bootblock-y += mmap_boot.c + # Add the assembly file that pulls in the rest of the dependencies in # the right order. Make sure the auto generated bootblock.inc is a proper # dependency. Make the same true for the linker sript. bootblock-y += id.S $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h -bootblock-y += bootblock.S -bootblock-y += walkcbfs.S -$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc - bootblock-y += bootblock.ld $(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld @@ -95,11 +94,21 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock. cat $^ >> $@.tmp mv $@.tmp $@ +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock_modern.S +bootblock-y += bootblock.c +else +bootblock-y += bootblock_legacy.S +bootblock-y += walkcbfs.S + +$(obj)/arch/x86/bootblock_legacy.bootblock.o: $(objgenerated)/bootblock.inc + $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ +endif # $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) $(objcbfs)/bootblock.debug: $$(bootblock-objs) diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S deleted file mode 100644 index 27a23eb..0000000 --- a/src/arch/x86/bootblock.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> - -#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#endif - -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock.c b/src/arch/x86/bootblock.c new file mode 100644 index 0000000..03849b1 --- /dev/null +++ b/src/arch/x86/bootblock.c @@ -0,0 +1,60 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbfs.h> +#include <bootblock.h> +#include <halt.h> + + +/* + * TODO: Implement a generic fallback/normal mechanism + */ +static const char *get_next_stage_name(void) +{ + if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) + return CONFIG_CBFS_PREFIX "/romstage"; + + /* BOOTBLOCK_NORMAL not implemented */ + return CONFIG_CBFS_PREFIX "/romstage"; +} + +static void enter_romstage(void *romstage_entry, uint32_t bist) +{ + asm volatile ( + "jmp *%0\n\t" + : : "r" (romstage_entry), "a" (bist) + ); +} + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) +{ + void *entry; + struct cbfs_stage *romstage; + const char* target1 = get_next_stage_name(); + + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + + /* + * TODO: Do something constructive with tsc_lo and tsc_hi + */ + if (romstage) { + entry = (void *)(uintptr_t)romstage->entry; + enter_romstage(entry, bist); + } + halt(); +} diff --git a/src/arch/x86/bootblock_legacy.S b/src/arch/x86/bootblock_legacy.S new file mode 100644 index 0000000..9cd7eaf --- /dev/null +++ b/src/arch/x86/bootblock_legacy.S @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is the original bootblock used by coreboot on x86 systems. It contains + * a monolithic code flow, assembled from the following stages: + * - reset16.inc: the reset vector + * - entry16.inc: protected mode setup + * - entry16.inc: segment descriptor setup + * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization + * - generated/bootblock.inc: ROMCC part of the bootblock + * + * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * tries to do the absolute minimum before walking CBFS and jumping to romstage. + * + * This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. + */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generated by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions at the beginning of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock_modern.S b/src/arch/x86/bootblock_modern.S new file mode 100644 index 0000000..a9023b9 --- /dev/null +++ b/src/arch/x86/bootblock_modern.S @@ -0,0 +1,56 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CR0_MP (1 << 1) +#define CR0_EM (1 << 2) + +#define CR4_OSFXSR (1 << 9) +#define CR4_OSXMMEXCPT (1 << 10) + +/* + * Include the old code for reset vector and protected mode entry. That code has + * withstood the test of time + */ +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +.intel_syntax noprefix + +bootblock_protected_mode_entry: + /* Save BIST result */ + movd mm0, eax + /* Save an early timestamp */ + rdtsc + movd mm1, eax + movd mm2, edx + +#if !IS_ENABLED(CONFIG_SSE) +enable_sse: + mov eax, cr0 + and ax, not CR0_EM /* Clear coprocessor emulation CR0.EM */ + or ax, CR0_MP /* Set coprocessor monitoring CR0.MP */ + mov cr0, eax + mov eax, cr4 + or ax, (CR4_OSFXSR | CR4_OSXMMEXCPT) + mov cr4, eax +#endif /* IS_ENABLED(CONFIG_SSE) */ + + /* We're done. Now it's up to platform-specific code */ + jmp bootblock_pre_c_entry diff --git a/src/arch/x86/include/bootblock.h b/src/arch/x86/include/bootblock.h new file mode 100644 index 0000000..f7671c2 --- /dev/null +++ b/src/arch/x86/include/bootblock.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _ARCH_X86_BOOTBLOCK_H +#define _ARCH_X86_BOOTBLOCK_H + +#include <arch/cpu.h> + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); + +#endif /* _ARCH_X86_BOOTBLOCK_H */

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Patch set updated for coreboot: intel/skylake: Init variable so GCC knows it's set
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12860 -gerrit commit 1c8543f01f90b853844882c56afbe637ddd66c66 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 15:35:45 2016 -0700 intel/skylake: Init variable so GCC knows it's set Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/skylake/pcr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 7efbb25..0900510 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -63,6 +63,7 @@ static int pch_pcr_read(u8 pid, u16 offset, u32 size, void *data) *(u8 *) data = read8(pcr_reg_address(pid, offset)); break; default: + return -1; break; } return 0; @@ -158,7 +159,7 @@ static int pcr_and_then_or(u8 pid, u16 offset, u32 size, u32 anddata, u32 ordata) { u8 status; - u32 data32; + u32 data32 = 0; status = pch_pcr_read(pid, offset, size, &data32); if (status != 0)

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Patch merged into coreboot/master: fsp_baytrail: Add additional PCI space above 4GB
by gerrit＠coreboot.org 08 Jan '16

08 Jan '16

the following patch was just integrated into master: commit b95a0745865a084e5426b9930eba0dadd3301c23 Author: Martin Roth <martinroth(a)google.com> Date: Tue Dec 22 12:40:53 2015 -0700 fsp_baytrail: Add additional PCI space above 4GB This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: York Yang <york.yang(a)intel.com> See https://review.coreboot.org/12791 for details. -gerrit

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New patch to review for coreboot: intel/sklrvp: Drop abuild.disabled file to start build testing
by Martin Roth 08 Jan '16

08 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12866 -gerrit commit a9513ac5c637116d7f509dc9035cd674748008d2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:21:34 2015 -0800 intel/sklrvp: Drop abuild.disabled file to start build testing Remove the final abuild.disabled file so that we can test all the boards again. Change-Id: I40353ea7a062c80637ea86c6cf646d42231c0f06 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/sklrvp/abuild.disabled | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel.

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coreboot-gerrit January 2016