coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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2471 discussions

New patch to review for coreboot: arch/x86: Include in the bootblock files needed by run_romstage
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12880 -gerrit commit 60907be072da6162f76d6943543fd304f9fc10d7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 23:05:00 2016 -0800 arch/x86: Include in the bootblock files needed by run_romstage run_romstage(), the generic function for loading romstage from the bootblock makes use of CBFS APIs which requires symbols that were not previously available in the x86 bootblock. Compile the files which provide these symbols in the bootblock. Change-Id: I36558b672a926ab22bc9018cd51aee32213792c2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c940f44..8249a77 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -68,7 +68,9 @@ else LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 endif +bootblock-y += boot.c bootblock-y += memcpy.c +bootblock-y += memset.c bootblock-y += mmap_boot.c # Add the assembly file that pulls in the rest of the dependencies in

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New patch to review for coreboot: cpu/qemu-x86: Remove "bist" parameter handling from romstage
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12879 -gerrit commit c06d399c5df4150be58dfa61b28df8c32a4e596c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:57:58 2016 -0800 cpu/qemu-x86: Remove "bist" parameter handling from romstage This parameter is unused at this point, so there is no reason hauling it around in assembly in order to pass it to C code. Change-Id: Ice3ff6f06f561099a3ed7764062f0ac0521855be Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/romstage.h | 18 ++++++++++++++++++ src/cpu/qemu-x86/romstage_entry.inc | 8 -------- src/mainboard/emulation/qemu-i440fx/romstage.c | 4 ++-- src/mainboard/emulation/qemu-q35/romstage.c | 4 ++-- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/cpu/qemu-x86/romstage.h b/src/cpu/qemu-x86/romstage.h new file mode 100644 index 0000000..ea628c8 --- /dev/null +++ b/src/cpu/qemu-x86/romstage.h @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _CPU_QEMU_X86_ROMSTAGE_H_ +#define _CPU_QEMU_X86_ROMSTAGE_H_ + +/* romstage C entry point */ +void main(void); + +#endif /* _CPU_QEMU_X86_ROMSTAGE_H_ */ diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc index c930fdc..75eb700 100644 --- a/src/cpu/qemu-x86/romstage_entry.inc +++ b/src/cpu/qemu-x86/romstage_entry.inc @@ -24,9 +24,6 @@ #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - /* Save the BIST result. */ - movl %eax, %ebp - cache_as_ram: post_code(0x20) @@ -34,11 +31,6 @@ cache_as_ram: movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - before_romstage: post_code(0x29) /* Call romstage.c main function. */ diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 2d2a87e..1aa773d 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -27,8 +27,8 @@ #include "memory.c" -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +#include <cpu/qemu-x86/romstage.h> +void main(void) { int cbmem_was_initted; diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index f6b7b63..bba605e 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -28,8 +28,8 @@ #include "../qemu-i440fx/memory.c" -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +#include <cpu/qemu-x86/romstage.h> +void main(void) { int cbmem_was_initted;

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New patch to review for coreboot: cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12878 -gerrit commit b8dafe6081ce13287a3b724acf23cd6113c2becb Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:51:21 2016 -0800 cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code This CPU doesn't use cache-as-ram; however, since it uses a C environment bootblock, any such setup would have to be handled in the bootblock anyway. Ramstage is succesfully loaded and executed with this change. Change-Id: Ib9a70fed933ac484f8a5632b6b8f1ab9f69a9ae0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/romstage_entry.inc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc index fcd2d3b..c930fdc 100644 --- a/src/cpu/qemu-x86/romstage_entry.inc +++ b/src/cpu/qemu-x86/romstage_entry.inc @@ -29,15 +29,7 @@ cache_as_ram: post_code(0x20) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - post_code(0x21) /* Set up the stack pointer. */ movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax movl %eax, %esp

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New patch to review for coreboot: cpu/qemu-x86: Move romstage assembly file to cpu directory
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12877 -gerrit commit 071feff3499d7a997fbfb25a35d2c7fbffa13840 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:46:18 2016 -0800 cpu/qemu-x86: Move romstage assembly file to cpu directory The romstage assembly file was implemented in qemu-i440fx mainboard directory, but was also used by the qemu-q35 board via cpu_incs-y. Consolidate this file into the cpu directory, as it is used by all boards with this cpu. Both qemu x86 boards succesfully execute ramstage. Change-Id: I078da8c6d508571035e088d100fc18dae99e570b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/Makefile.inc | 1 + src/cpu/qemu-x86/romstage_entry.inc | 68 ++++++++++++++++++++++ src/mainboard/emulation/qemu-i440fx/Makefile.inc | 1 - .../emulation/qemu-i440fx/cache_as_ram.inc | 68 ---------------------- src/mainboard/emulation/qemu-q35/Makefile.inc | 1 - 5 files changed, 69 insertions(+), 70 deletions(-) diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 0ed76f9..b6cf4f7 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -12,6 +12,7 @@ ## GNU General Public License for more details. ## +cpu_incs-y += $(src)/cpu/qemu-x86/romstage_entry.inc bootblock-y += bootblock_asm.S bootblock-y += bootblock.c ramstage-y += qemu.c diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc new file mode 100644 index 0000000..fcd2d3b --- /dev/null +++ b/src/cpu/qemu-x86/romstage_entry.inc @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +#include <cbmem.h> + +#define CACHE_AS_RAM_SIZE 0x10000 +#define CACHE_AS_RAM_BASE 0xd0000 + +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + // movl $0x23322332, %eax + xorl %eax, %eax + rep stosl + + post_code(0x21) + /* Set up the stack pointer. */ + movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x29) + /* Call romstage.c main function. */ + call main + + post_code(0x30) + +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl $CONFIG_RAMTOP, %esp + movl %esp, %ebp + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index f9cf252..6ed3af1 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,3 +1,2 @@ -cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += northbridge.c ramstage-y += fw_cfg.c diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc deleted file mode 100644 index fcd2d3b..0000000 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cbmem.h> - -#define CACHE_AS_RAM_SIZE 0x10000 -#define CACHE_AS_RAM_BASE 0xd0000 - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - post_code(0x21) - /* Set up the stack pointer. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x29) - /* Call romstage.c main function. */ - call main - - post_code(0x30) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl $CONFIG_RAMTOP, %esp - movl %esp, %ebp - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index fc4374c..e5f4b87 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,3 +1,2 @@ -cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += ../qemu-i440fx/northbridge.c ramstage-y += ../qemu-i440fx/fw_cfg.c

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New patch to review for coreboot: cpu/qemu-x86 boards: Move BIST check from romstage to bootblock
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12876 -gerrit commit e1e72da5927966e2e8f35d6384c81c41acfe43f5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:25:22 2016 -0800 cpu/qemu-x86 boards: Move BIST check from romstage to bootblock This allows for the removal of the 'bist' parameter in romstage, and eventually use of run_romstage() to enter romstage instead of the custom inline assembly stub currently in use. Change-Id: Ia63f3995e94bb63fe62e979dca3e0e6e17378a63 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/bootblock.c | 7 +++++++ src/mainboard/emulation/qemu-i440fx/romstage.c | 4 ---- src/mainboard/emulation/qemu-q35/romstage.c | 4 ---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index d62c47e..b4700a7 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -12,6 +12,7 @@ #include <arch/cpu.h> #include <cbfs.h> #include <console/console.h> +#include <cpu/x86/bist.h> #include <halt.h> /* Called from assembly. Prototype not needed by external .c file */ @@ -46,6 +47,12 @@ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) console_init(); + /* + * TODO: We might want a cleaner way to handle BIST reporting before we + * can converge with the generic bootblock in lib/. + */ + report_bist_failure(bist); + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); /* diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index f16f8dd..2d2a87e 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -20,7 +20,6 @@ #include <device/pnp_def.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" #include <delay.h> @@ -38,9 +37,6 @@ void main(unsigned long bist) console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - //print_pci_devices(); //dump_pci_devices(); diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index d54d8b0..f6b7b63 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -21,7 +21,6 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> -#include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" #include <delay.h> @@ -40,9 +39,6 @@ void main(unsigned long bist) i82801ix_early_init(); console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - //print_pci_devices(); //dump_pci_devices();

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New patch to review for coreboot: cpu/qemu-x86: Enable bootblock console
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12875 -gerrit commit 1fb18fdd66d0e8f75d23ff44fdf23cc6111b2dd7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:00:21 2016 -0800 cpu/qemu-x86: Enable bootblock console This brings the qemu C environment bootblock closer to the generic bootblock in lib/. This is a step before the bootblocks can be converged, but the code is not yet ready for unification. When running qemu with the "-serial stdio" flag, the "bootblock starting..." message now appears on the console. Change-Id: I121bce620cf7f8a713e7dad1833cff1b0dc2116f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/bootblock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 92dd6f7..d62c47e 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -11,6 +11,7 @@ #include <arch/cpu.h> #include <cbfs.h> +#include <console/console.h> #include <halt.h> /* Called from assembly. Prototype not needed by external .c file */ @@ -42,6 +43,9 @@ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) struct cbfs_stage *romstage; const char* target1 = get_next_stage_name(); + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + console_init(); + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); /*

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New patch to review for coreboot: drivers/uart/Makefile.inc: Compile uart8250io in bootblock
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12874 -gerrit commit 54057f5e832dedaa9a9934a39cd72942199366c5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 21:56:43 2016 -0800 drivers/uart/Makefile.inc: Compile uart8250io in bootblock This is needed for the next patch, which enables bootblock console on "qemu" CPUs, since that platform uses the 8250io driver. Note that the include is guarded by CONFIG_DRIVERS_UART_8250IO, so there is no risk of breaking builds on non-x86 architectures. Change-Id: Iaeed7280aa97b58d46b003df66647dae4a4e0e29 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/uart/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index da8b5f7..4b2aa53 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -10,6 +10,7 @@ smm-$(CONFIG_DEBUG_SMI) += util.c # be located in the soc/ or cpu/ directories instead of here. ifeq ($(CONFIG_DRIVERS_UART_8250IO),y) +bootblock-y += uart8250io.c verstage-y += uart8250io.c romstage-y += uart8250io.c ramstage-y += uart8250io.c

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New patch to review for coreboot: lib/Makefile.inc: Link hexdump.c in the bootblock as well
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12873 -gerrit commit f398558779035c090d81a7fdac2bc44d302f3405 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 14 09:58:36 2015 -0700 lib/Makefile.inc: Link hexdump.c in the bootblock as well Change-Id: Id58f252e238cc3eb3fe9632493642d2a37c2a772 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8842823..dc68d89 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -136,6 +136,7 @@ ramstage-y += imd_cbmem.c romstage-y += imd.c ramstage-y += imd.c +bootblock-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c

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New patch to review for coreboot: lib/hexdump: Refactor to skip lines with all ones as well
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12872 -gerrit commit 3b1bb69102346eacf05770eb20ee96601d718487 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 14 09:56:28 2015 -0700 lib/hexdump: Refactor to skip lines with all ones as well We already do this for lines with all zeroes, so it makes sense to treat all ones the same, for symmetry. Change-Id: I4b637b07a49e0c649331aa200995b474dd9a2682 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/lib/hexdump.c | 43 ++++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 7907a38..0715a5f 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -23,39 +23,40 @@ static int isprint(int c) void hexdump(const void *memory, size_t length) { int i; - uint8_t *m; + uint8_t *line; int all_zero = 0; - - m = (uint8_t *) memory; + int all_one = 0; for (i = 0; i < length; i += 16) { int j; - int left = MIN(length - i, 16); + line = ((uint8_t *)memory) + i; + + all_zero++; + all_one++; + for (j = 0; j < 16; j++) { + if (line[j] != 0) { + all_zero = 0; + break; + } + } - if (left < 16) { - all_zero = 0; - } else { - all_zero++; - for (j = 0; j < 16; j++) { - if (m[i + j] != 0) { - all_zero = 0; - break; - } + for (j = 0; j < 16; j++) { + if (line[j] != 0xff) { + all_one = 0; + break; } } - if (all_zero < 2) { + if ((all_zero < 2) && (all_one < 2)) { printk(BIOS_DEBUG, "%p:", memory + i); - for (j = 0; j < left; j++) - printk(BIOS_DEBUG, " %02x", m[i + j]); - for (j = left; j < 16; j++) - printk(BIOS_DEBUG, " "); + for (j = 0; j < 16; j++) + printk(BIOS_DEBUG, " %02x", line[j]); printk(BIOS_DEBUG, " "); - for (j = 0; j < left; j++) + for (j = 0; j < 16; j++) printk(BIOS_DEBUG, "%c", - isprint(m[i + j]) ? m[i + j] : '.'); + isprint(line[j]) ? line[j] : '.'); printk(BIOS_DEBUG, "\n"); - } else if (all_zero == 2) { + } else if ((all_zero == 2) || (all_one == 2)) { printk(BIOS_DEBUG, "...\n"); } }

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New patch to review for coreboot: console: Allow selecting C environment bootblock console on x86
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12871 -gerrit commit 58f6218aa14582322d87e243c311036c906cb614 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 18:01:18 2015 -0700 console: Allow selecting C environment bootblock console on x86 There's no reason to not have console in the bootblock, if the bootblock is running a C environment. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 73c6b28..57b828a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -2,7 +2,7 @@ menu "Console" config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV || ARCH_MIPS + depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV || ARCH_MIPS || C_ENVIRONMENT_BOOTBLOCK default n help Use console during the bootblock if supported

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coreboot-gerrit January 2016