coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cpu/qemu-x86: Run a C environment in the bootblock
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11858 -gerrit commit f6fd880bfae7a31fd16f9c88cdaeb62ea3026255 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Oct 10 16:35:58 2015 -0700 cpu/qemu-x86: Run a C environment in the bootblock Make use of the ROMCC-less bootblock introduced earlier. The "qemu" cpu is particularly easy because it does not require CAR setup. Change-Id: Idf161d363d2daf3c55454d376ca42d492463971a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/Kconfig | 1 + src/cpu/qemu-x86/Makefile.inc | 2 ++ src/cpu/qemu-x86/bootblock.c | 55 ++++++++++++++++++++++++++++++++++++++++ src/cpu/qemu-x86/bootblock_asm.S | 48 +++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ea2bc46..0ace941 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,4 +19,5 @@ config CPU_QEMU_X86 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select C_ENVIRONMENT_BOOTBLOCK select SMP diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index b5f8369..0ed76f9 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -12,6 +12,8 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock_asm.S +bootblock-y += bootblock.c ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c new file mode 100644 index 0000000..92dd6f7 --- /dev/null +++ b/src/cpu/qemu-x86/bootblock.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <cbfs.h> +#include <halt.h> + +/* Called from assembly. Prototype not needed by external .c file */ +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); + +/* + * TODO: Implement a generic fallback/normal mechanism + */ +static const char *get_next_stage_name(void) +{ + if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) + return CONFIG_CBFS_PREFIX "/romstage"; + + /* BOOTBLOCK_NORMAL not implemented */ + return CONFIG_CBFS_PREFIX "/romstage"; +} + +static void enter_romstage(void *romstage_entry, uint32_t bist) +{ + asm volatile ( + "jmp *%0\n\t" + : : "r" (romstage_entry), "a" (bist) + ); +} + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) +{ + void *entry; + struct cbfs_stage *romstage; + const char* target1 = get_next_stage_name(); + + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + + /* + * TODO: Do something constructive with tsc_lo and tsc_hi + */ + if (romstage) { + entry = (void *)(uintptr_t)romstage->entry; + enter_romstage(entry, bist); + } + halt(); +} diff --git a/src/cpu/qemu-x86/bootblock_asm.S b/src/cpu/qemu-x86/bootblock_asm.S new file mode 100644 index 0000000..6e1cd2e --- /dev/null +++ b/src/cpu/qemu-x86/bootblock_asm.S @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/post_codes.h> + +#define STACK_SIZE 0x10000 +#define STACK_BASE 0xd0000 + +.intel_syntax noprefix + +#define post_code(code) \ + mov eax, code; \ + out 0x80, eax + +.global bootblock_pre_c_entry + +.section .text +bootblock_pre_c_entry: + + /* Set up a stack */ + mov esp, (STACK_BASE + STACK_SIZE - 4) + + /* + * We have the following values saved from earlier: + * mm0: BIST result + * mm1: TSC timestamp low 32 bits + * mm2: TSC timestamp high 32 bits + */ + movd eax, mm2 + push eax + movd eax, mm1 + push eax + movd eax, mm0 + push eax + call bootblock_main + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever

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Patch set updated for coreboot: drivers/uart/Makefile.inc: Compile uart8250io in bootblock
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12874 -gerrit commit e4bececdf745e04643bf902bff137d440f2b35f4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 21:56:43 2016 -0800 drivers/uart/Makefile.inc: Compile uart8250io in bootblock This is needed for the next patch, which enables bootblock console on "qemu" CPUs, since that platform uses the 8250io driver. Note that the include is guarded by CONFIG_DRIVERS_UART_8250IO, so there is no risk of breaking builds on non-x86 architectures. Change-Id: Iaeed7280aa97b58d46b003df66647dae4a4e0e29 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/uart/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index da8b5f7..4b2aa53 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -10,6 +10,7 @@ smm-$(CONFIG_DEBUG_SMI) += util.c # be located in the soc/ or cpu/ directories instead of here. ifeq ($(CONFIG_DRIVERS_UART_8250IO),y) +bootblock-y += uart8250io.c verstage-y += uart8250io.c romstage-y += uart8250io.c ramstage-y += uart8250io.c

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Patch set updated for coreboot: cpu/qemu-x86: Enable bootblock console
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12875 -gerrit commit aa95a775371fa2d832c845a8bd464d06076c8d86 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:00:21 2016 -0800 cpu/qemu-x86: Enable bootblock console This brings the qemu C environment bootblock closer to the generic bootblock in lib/. This is a step before the bootblocks can be converged, but the code is not yet ready for unification. When running qemu with the "-serial stdio" flag, the "bootblock starting..." message now appears on the console. Change-Id: I121bce620cf7f8a713e7dad1833cff1b0dc2116f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/bootblock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 92dd6f7..d62c47e 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -11,6 +11,7 @@ #include <arch/cpu.h> #include <cbfs.h> +#include <console/console.h> #include <halt.h> /* Called from assembly. Prototype not needed by external .c file */ @@ -42,6 +43,9 @@ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) struct cbfs_stage *romstage; const char* target1 = get_next_stage_name(); + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + console_init(); + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); /*

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Patch set updated for coreboot: */Makefile.inc: Compile files needed by uart8250 in x86 bootblock
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12869 -gerrit commit 114f1f45a477aa10a2945e551aa12e491d2b8375 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:35:07 2015 -0700 */Makefile.inc: Compile files needed by uart8250 in x86 bootblock These files provide symbols needed by console and uart drivers. This was not an issue in the past, as we were not setting up a C environment this early in the boot process. Change-Id: Ied5106ac30a68971c8330e8f8270ab060994a89d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/cpu/x86/lapic/Makefile.inc | 1 + src/drivers/uart/Makefile.inc | 1 + src/lib/Makefile.inc | 1 + 3 files changed, 3 insertions(+) diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 1deec3f..c0a3572 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -3,6 +3,7 @@ ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +bootblock-y += boot_cpu.c verstage-y += boot_cpu.c romstage-y += boot_cpu.c ramstage-y += boot_cpu.c diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index fc33ee9..da8b5f7 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -17,6 +17,7 @@ smm-$(CONFIG_DEBUG_SMI) += uart8250io.c endif ifeq ($(CONFIG_DRIVERS_UART_8250MEM),y) +bootblock-y += uart8250mem.c verstage-y += uart8250mem.c romstage-y += uart8250mem.c ramstage-y += uart8250mem.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 724391f..8842823 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -87,6 +87,7 @@ endif romstage-y += compute_ip_checksum.c ifeq ($(CONFIG_COMPILER_GCC),y) +bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += gcc.c verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += gcc.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c

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Patch set updated for coreboot: src/arch/x86: Link the compiler runtime library in the bootblock
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12870 -gerrit commit ed2c73fc9480731d087ff185b53564c52b69bf44 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:35:39 2015 -0700 src/arch/x86: Link the compiler runtime library in the bootblock At least on GCC __udivdi3 and __umoddi3 are needed by the console code. They are provided by the compiler runtime library. Change-Id: I78bbea425c33d7eebaf829d58d763b7a1c6e997c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/arch/x86/Makefile.inc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f372645..c940f44 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -112,8 +112,12 @@ endif # $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - $(filter-out %.ld,$(bootblock-objs)) \ + $(LD_bootblock) $(LDFLAGS_bootblock) -static \ + -o $@ $(COMPILER_RT_FLAGS_bootblock) -L$(obj) \ + -whole-archive --start-group \ + $(filter %.o,$(bootblock-objs)) \ + --no-whole-archive $(COMPILER_RT_bootblock) \ + --end-group \ -T $(obj)/arch/x86/bootblock.bootblock.ld

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Patch set updated for coreboot: console: Allow selecting C environment bootblock console on x86
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12871 -gerrit commit 384f3a4f2d094617f2276163c0eb965d1dc8a9c2 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 18:01:18 2015 -0700 console: Allow selecting C environment bootblock console on x86 There's no reason to not have console in the bootblock, if the bootblock is running a C environment. Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 73c6b28..57b828a 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -2,7 +2,7 @@ menu "Console" config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV || ARCH_MIPS + depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV || ARCH_MIPS || C_ENVIRONMENT_BOOTBLOCK default n help Use console during the bootblock if supported

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Patch set updated for coreboot: cpu/qemu-x86: Use run_romstage instead of custom inline assembly
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12881 -gerrit commit 3e4ec37c1e2fc141afd82a5a3310d3a092ad392b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 23:08:09 2016 -0800 cpu/qemu-x86: Use run_romstage instead of custom inline assembly Now that passing the BIST result to romstage is no longer required, we no longer need to use custom assembly to call into romstage. Instead, a lot of the logic in the bootblock can now be replaced by a single call to run_romstage(). This is another step in converging the bootblock with the generic bootblock logic in lib/. Change-Id: I66436c8fba5121a3758d02955f691ac9d273b049 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/bootblock.c | 34 ++-------------------------------- 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index b4700a7..056bde4 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -18,32 +18,8 @@ /* Called from assembly. Prototype not needed by external .c file */ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); -/* - * TODO: Implement a generic fallback/normal mechanism - */ -static const char *get_next_stage_name(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) - return CONFIG_CBFS_PREFIX "/romstage"; - - /* BOOTBLOCK_NORMAL not implemented */ - return CONFIG_CBFS_PREFIX "/romstage"; -} - -static void enter_romstage(void *romstage_entry, uint32_t bist) -{ - asm volatile ( - "jmp *%0\n\t" - : : "r" (romstage_entry), "a" (bist) - ); -} - asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) { - void *entry; - struct cbfs_stage *romstage; - const char* target1 = get_next_stage_name(); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) console_init(); @@ -53,14 +29,8 @@ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) */ report_bist_failure(bist); - romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + run_romstage(); - /* - * TODO: Do something constructive with tsc_lo and tsc_hi - */ - if (romstage) { - entry = (void *)(uintptr_t)romstage->entry; - enter_romstage(entry, bist); - } + /* Should never be reached, but halt just in case. */ halt(); }

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Patch set updated for coreboot: arch/x86: Include in the bootblock files needed by run_romstage
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12880 -gerrit commit 9bef3cf2eb75e096cf9a2fcac8ba643c534bb2e0 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 23:05:00 2016 -0800 arch/x86: Include in the bootblock files needed by run_romstage run_romstage(), the generic function for loading romstage from the bootblock makes use of CBFS APIs which requires symbols that were not previously available in the x86 bootblock. Compile the files which provide these symbols in the bootblock. Change-Id: I36558b672a926ab22bc9018cd51aee32213792c2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c940f44..8249a77 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -68,7 +68,9 @@ else LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 endif +bootblock-y += boot.c bootblock-y += memcpy.c +bootblock-y += memset.c bootblock-y += mmap_boot.c # Add the assembly file that pulls in the rest of the dependencies in

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Patch set updated for coreboot: arch/x86/include: Rename bootblock_common to bootblock_romcc.h
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12867 -gerrit commit 63ab98ffb21cd4ba34ff57f59e371dd64b5790b1 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 7 19:10:24 2016 -0800 arch/x86/include: Rename bootblock_common to bootblock_romcc.h This header is only used for the bootblock compiled with ROMCC. As the follow-on patches introduce a bootblock which does not make use of ROMCC, rename this header to prevent confusion. Change-Id: Id29c5bc6928c11cc7cb922fcfac71e5a3dcd113c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/bootblock_normal.c | 2 +- src/arch/x86/bootblock_simple.c | 2 +- src/arch/x86/include/arch/bootblock_common.h | 77 ---------------------------- src/arch/x86/include/arch/bootblock_romcc.h | 77 ++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 79 deletions(-) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index a6a877c..061e3cb 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_romcc.h> #include <pc80/mc146818rtc.h> #include <halt.h> diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index 4bff360..b5eb414 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_romcc.h> #include <halt.h> static void main(unsigned long bist) diff --git a/src/arch/x86/include/arch/bootblock_common.h b/src/arch/x86/include/arch/bootblock_common.h deleted file mode 100644 index 939ba08..0000000 --- a/src/arch/x86/include/arch/bootblock_common.h +++ /dev/null @@ -1,77 +0,0 @@ -#include <arch/cbfs.h> -#include <cpu/x86/lapic/boot_cpu.c> -#include <pc80/mc146818rtc.h> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif - -#if CONFIG_USE_OPTION_TABLE -static void sanitize_cmos(void) -{ - if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { - unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); - if (cmos_default) { - int i; - cmos_disable_rtc(); - for (i = 14; i < 128; i++) { - cmos_write_inner(cmos_default[i], i); - } - cmos_enable_rtc(); - } - } -} -#endif - -#if CONFIG_CMOS_POST -static void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG_CMOS_POST_EXTRA - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} -#endif diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h new file mode 100644 index 0000000..939ba08 --- /dev/null +++ b/src/arch/x86/include/arch/bootblock_romcc.h @@ -0,0 +1,77 @@ +#include <arch/cbfs.h> +#include <cpu/x86/lapic/boot_cpu.c> +#include <pc80/mc146818rtc.h> + +#ifdef CONFIG_BOOTBLOCK_RESETS +#include CONFIG_BOOTBLOCK_RESETS +#endif + +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#endif + +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) +{ +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT + bootblock_northbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT + bootblock_southbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_CPU_INIT + bootblock_cpu_init(); +#endif +} +#endif + +#if CONFIG_USE_OPTION_TABLE +static void sanitize_cmos(void) +{ + if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { + unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); + if (cmos_default) { + int i; + cmos_disable_rtc(); + for (i = 14; i < 128; i++) { + cmos_write_inner(cmos_default[i], i); + } + cmos_enable_rtc(); + } + } +} +#endif + +#if CONFIG_CMOS_POST +static void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG_CMOS_POST_EXTRA + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} +#endif

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New patch to review for coreboot: cpu/qemu-x86: Use run_romstage instead of custom inline assembly
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12881 -gerrit commit f6dd761b76b55c8b73e3267ba09b82a917a8e451 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 23:08:09 2016 -0800 cpu/qemu-x86: Use run_romstage instead of custom inline assembly Now that passing the BIST result to romstage is no longer required, we no longer need to use custom assembly to call into romstage. Instead, a lot of the logic in the bootblock can now be replaced by a single call to run_romstage(). This is another step in converging the bootblock with the generic bootblock logic in lib/. Change-Id: I66436c8fba5121a3758d02955f691ac9d273b049 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/bootblock.c | 34 ++-------------------------------- 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index b4700a7..056bde4 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -18,32 +18,8 @@ /* Called from assembly. Prototype not needed by external .c file */ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); -/* - * TODO: Implement a generic fallback/normal mechanism - */ -static const char *get_next_stage_name(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) - return CONFIG_CBFS_PREFIX "/romstage"; - - /* BOOTBLOCK_NORMAL not implemented */ - return CONFIG_CBFS_PREFIX "/romstage"; -} - -static void enter_romstage(void *romstage_entry, uint32_t bist) -{ - asm volatile ( - "jmp *%0\n\t" - : : "r" (romstage_entry), "a" (bist) - ); -} - asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) { - void *entry; - struct cbfs_stage *romstage; - const char* target1 = get_next_stage_name(); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) console_init(); @@ -53,14 +29,8 @@ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) */ report_bist_failure(bist); - romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + run_romstage(); - /* - * TODO: Do something constructive with tsc_lo and tsc_hi - */ - if (romstage) { - entry = (void *)(uintptr_t)romstage->entry; - enter_romstage(entry, bist); - } + /* Should never be reached, but halt just in case. */ halt(); }

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coreboot-gerrit January 2016