coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch set updated for coreboot: Enable USB 3 controller on ThinkPad X220
by nemo 10 Jan '16

10 Jan '16

nemo (mtcoreboot(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12882 -gerrit commit 1f44588e2af7ce745efcbc60e780d5d6925bf1e2 Author: Marian Tietz <mtcoreboot(a)gmail.com> Date: Sat Jan 9 18:18:47 2016 +0100 Enable USB 3 controller on ThinkPad X220 Since only X220 with i7 have the USB3 controller this was probably overlooked. Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot(a)gmail.com> --- src/mainboard/lenovo/x220/devicetree.cb | 4 +++- src/mainboard/lenovo/x220/romstage.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 9c9ac7c..9f25658 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -109,7 +109,9 @@ chip northbridge/intel/sandybridge end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 + device pci 1c.6 on + subsystemid 0x17aa 0x21db + end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on subsystemid 0x17aa 0x21db diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 1d89d92..ce3f276 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -54,7 +54,7 @@ void pch_enable_lpc(void) void rcba_config(void) { /* Disable unused devices (board specific) */ - RCBA32(FD) = 0x1fe41fe3; + RCBA32(FD) = 0x1fa41fe3; RCBA32(BUC) = 0; }

1 0

New patch to review for coreboot: mb/lenovo/x200: Add panel power sequence values
by Nico Huber 10 Jan '16

10 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12886 -gerrit commit 9acf33a1dd62afa757452de7764072289bd56911 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 9 23:33:30 2016 +0100 mb/lenovo/x200: Add panel power sequence values Values are taken from the vendor BIOS of my X200s. Notable effect: Stops display from flashing during native graphics init / Linux mode setting. Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/mainboard/lenovo/x200/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 36a1939..92c41d7 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -3,6 +3,11 @@ chip northbridge/intel/gm45 register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms + register "gpu_panel_power_down_delay" = "250" # T3: 25ms + register "gpu_panel_power_backlight_on_delay" = "2500" # T5: 250ms + register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms + register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1"

1 0

New patch to review for coreboot: nb/intel/gm45: Backport configuration of panel power timings
by Nico Huber 10 Jan '16

10 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12885 -gerrit commit 9b9be598c7e83ef0207ba09a5cc647770a6cd09e Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 9 23:27:16 2016 +0100 nb/intel/gm45: Backport configuration of panel power timings Register settings are the same as on newer chips (compare sandy- bridge), just at different locations. Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/gm45/chip.h | 5 ++++ src/northbridge/intel/gm45/gma.c | 58 +++++++++++++++++++++++++++++++++------ 2 files changed, 54 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index de9b512..b537b93 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -20,6 +20,11 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_gm45_config { + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 2824cf7..299cb25 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -37,6 +37,11 @@ static struct resource *gtt_res = NULL; +u32 gtt_read(u32 reg) +{ + return read32(res2mmio(gtt_res, reg, 0)); +} + void gtt_write(u32 reg, u32 data) { write32(res2mmio(gtt_res, reg, 0), data); @@ -413,6 +418,44 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, } } +static void gma_pm_init_post_vbios(struct device *const dev) +{ + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; + + u32 reg32; + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(PP_ON_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(PP_ON_DELAYS, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(PP_OFF_DELAYS); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(PP_OFF_DELAYS, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = gtt_read(PP_DIVISOR); + reg32 &= ~0x1f; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + gtt_write(PP_DIVISOR, reg32); + } + + /* Enable Backlight */ + gtt_write(BLC_PWM_CTL2, (1 << 31)); + if (conf->gfx.backlight == 0) + gtt_write(BLC_PWM_CTL, 0x06100610); + else + gtt_write(BLC_PWM_CTL, conf->gfx.backlight); +} + static void gma_func0_init(struct device *dev) { u32 reg32; @@ -430,7 +473,12 @@ static void gma_func0_init(struct device *dev) if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev); - } else { + } + + /* Post VBIOS init */ + gma_pm_init_post_vbios(dev); + + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { u32 physbase; struct resource *lfb_res; struct resource *pio_res; @@ -453,14 +501,6 @@ static void gma_func0_init(struct device *dev) generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); } - - /* Post VBIOS init */ - /* Enable Backlight */ - gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); - else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

1 0

New patch to review for coreboot: nb/intel/gm45: Drop unnecessary panel power handling
by Nico Huber 10 Jan '16

10 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12884 -gerrit commit 85420674b6961e125b8bc4cdcc7e49a67a4a3558 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 9 22:58:44 2016 +0100 nb/intel/gm45: Drop unnecessary panel power handling Skip everything but the final setting of PP_CONTROL, i.e. triggering the power up. The settings with PANEL_UNLOCK_REGS are useless as no lockable registers were touched in between. Also the loop waiting for the panel power up to finish was a no-op as the registers with the power timings were never filled (see follow-up commits). Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/gm45/gma.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index d5a133b..2824cf7 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -397,21 +397,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); - mdelay(1); - write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS - | PANEL_POWER_ON | PANEL_POWER_RESET); - - printk (BIOS_DEBUG, "waiting for panel powerup\n"); - while (1) { - u32 reg32; - reg32 = read32(mmio + PP_STATUS); - if (((reg32 >> 28) & 3) == 0) - break; - } - printk (BIOS_DEBUG, "panel powered up\n"); - write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); /* Enable screen memory. */

1 0

New patch to review for coreboot: nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` style
by Nico Huber 10 Jan '16

10 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12883 -gerrit commit 776931da8354f3ec0c275e0d72dfc41badbd24eb Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 9 23:15:53 2016 +0100 nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` style Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/gm45/gma.c | 153 ++++++++++++++++++++------------------- 1 file changed, 77 insertions(+), 76 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8c97143..d5a133b 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -42,8 +42,6 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - static void power_port(u8 *mmio) { read32(mmio + 0x00061100); // = 0x00000000 @@ -172,33 +170,33 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, target_frequency = mode->lvds_dual_channel ? mode->pixel_clock : (2 * mode->pixel_clock); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -#else - vga_textmode_init(); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } /* Find suitable divisors. */ for (candp1 = 1; candp1 <= 8; candp1++) { @@ -327,17 +325,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); -#else - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0x20000000); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + } mdelay(1); @@ -357,13 +356,14 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); -#else - write32(mmio + VGACNTRL, 0x22c4008e); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0x22c4008e); + } write32(mmio + TRANS_HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -421,14 +421,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); -#endif + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } } -#endif - static void gma_func0_init(struct device *dev) { u32 reg32; @@ -443,30 +442,32 @@ static void gma_func0_init(struct device *dev) struct northbridge_intel_gm45_config *conf = dev->chip_info; -#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); -#else - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); - } + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + } else { + u32 physbase; + struct resource *lfb_res; + struct resource *pio_res; + + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + if (gtt_res && gtt_res->base && physbase && pio_res + && pio_res->base && lfb_res && lfb_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, + pio_res->base, lfb_res->base); + } - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); -#endif + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, + "$VBT IRONLAKE-MOBILE"); + } /* Post VBIOS init */ /* Enable Backlight */

1 0

Patch merged into coreboot/master: buildgcc: Print out all missing tools then halt
by gerrit＠coreboot.org 09 Jan '16

09 Jan '16

the following patch was just integrated into master: commit 8846382cbbbf301e313958aadc4bed2522796c1f Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 11:03:36 2016 -0700 buildgcc: Print out all missing tools then halt Instead of printing out a single tool that needs to be installed each time buildgcc is run, print out the entire list of tools to be installed, then halt. Change-Id: I7761760eef3c45ba371f882a4f987408945bb3e5 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12856 for details. -gerrit

1 0

New patch to review for coreboot: Enable USB 3 controller on ThinkPad X220
by nemo 09 Jan '16

09 Jan '16

nemo (coreboot(a)nemo.ikkoku.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12882 -gerrit commit 427483f499603f65aa1ad1120a994bb1bd077cbe Author: nemo <coreboot(a)nemo.ikkoku.de> Date: Sat Jan 9 18:18:47 2016 +0100 Enable USB 3 controller on ThinkPad X220 Since only X220 with i7 have the USB3 controller this was probably overlooked. Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: nemo <coreboot(a)nemo.ikkoku.de> --- src/mainboard/lenovo/x220/devicetree.cb | 4 +++- src/mainboard/lenovo/x220/romstage.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 9c9ac7c..9f25658 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -109,7 +109,9 @@ chip northbridge/intel/sandybridge end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 + device pci 1c.6 on + subsystemid 0x17aa 0x21db + end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on subsystemid 0x17aa 0x21db diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 1d89d92..ce3f276 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -54,7 +54,7 @@ void pch_enable_lpc(void) void rcba_config(void) { /* Disable unused devices (board specific) */ - RCBA32(FD) = 0x1fe41fe3; + RCBA32(FD) = 0x1fa41fe3; RCBA32(BUC) = 0; }

1 0

Patch set updated for coreboot: cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12878 -gerrit commit 133c7e9533826133c2b77878ba74d119be935f0d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:51:21 2016 -0800 cpu/qemu-x86/romstage_entry.inc: Remove redunant cache-as-ram code This CPU doesn't use cache-as-ram; however, since it uses a C environment bootblock, any such setup would have to be handled in the bootblock anyway. Ramstage is succesfully loaded and executed with this change. Change-Id: Ib9a70fed933ac484f8a5632b6b8f1ab9f69a9ae0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/romstage_entry.inc | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc index fcd2d3b..9d7cf38 100644 --- a/src/cpu/qemu-x86/romstage_entry.inc +++ b/src/cpu/qemu-x86/romstage_entry.inc @@ -19,27 +19,17 @@ #include <cpu/x86/post_code.h> #include <cbmem.h> -#define CACHE_AS_RAM_SIZE 0x10000 -#define CACHE_AS_RAM_BASE 0xd0000 - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) +#define STACK_SIZE 0x10000 +#define STACK_BASE 0xd0000 /* Save the BIST result. */ movl %eax, %ebp -cache_as_ram: +qemu_x86_assembly_entry: post_code(0x20) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - post_code(0x21) /* Set up the stack pointer. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax + movl $(STACK_BASE + STACK_SIZE - 4), %eax movl %eax, %esp /* Restore the BIST result. */

1 0

Patch set updated for coreboot: cpu/qemu-x86: Remove "bist" parameter handling from romstage
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12879 -gerrit commit 6f5ea8b84255f2d7e8b75c252d2bef53e7c66074 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 22:57:58 2016 -0800 cpu/qemu-x86: Remove "bist" parameter handling from romstage This parameter is unused at this point, so there is no reason hauling it around in assembly in order to pass it to C code. Change-Id: Ice3ff6f06f561099a3ed7764062f0ac0521855be Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/romstage.h | 18 ++++++++++++++++++ src/cpu/qemu-x86/romstage_entry.inc | 8 -------- src/mainboard/emulation/qemu-i440fx/romstage.c | 4 ++-- src/mainboard/emulation/qemu-q35/romstage.c | 4 ++-- 4 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/cpu/qemu-x86/romstage.h b/src/cpu/qemu-x86/romstage.h new file mode 100644 index 0000000..ea628c8 --- /dev/null +++ b/src/cpu/qemu-x86/romstage.h @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _CPU_QEMU_X86_ROMSTAGE_H_ +#define _CPU_QEMU_X86_ROMSTAGE_H_ + +/* romstage C entry point */ +void main(void); + +#endif /* _CPU_QEMU_X86_ROMSTAGE_H_ */ diff --git a/src/cpu/qemu-x86/romstage_entry.inc b/src/cpu/qemu-x86/romstage_entry.inc index 9d7cf38..a2aba6a 100644 --- a/src/cpu/qemu-x86/romstage_entry.inc +++ b/src/cpu/qemu-x86/romstage_entry.inc @@ -22,9 +22,6 @@ #define STACK_SIZE 0x10000 #define STACK_BASE 0xd0000 - /* Save the BIST result. */ - movl %eax, %ebp - qemu_x86_assembly_entry: post_code(0x20) @@ -32,11 +29,6 @@ qemu_x86_assembly_entry: movl $(STACK_BASE + STACK_SIZE - 4), %eax movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - before_romstage: post_code(0x29) /* Call romstage.c main function. */ diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 2d2a87e..1aa773d 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -27,8 +27,8 @@ #include "memory.c" -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +#include <cpu/qemu-x86/romstage.h> +void main(void) { int cbmem_was_initted; diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index f6b7b63..bba605e 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -28,8 +28,8 @@ #include "../qemu-i440fx/memory.c" -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +#include <cpu/qemu-x86/romstage.h> +void main(void) { int cbmem_was_initted;

1 0

Patch set updated for coreboot: cpu/qemu-x86: Use run_romstage instead of custom inline assembly
by Alexandru Gagniuc 09 Jan '16

09 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12881 -gerrit commit 9f8d49f2dd87bbc41497f4250c1fb9e71d06949d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 8 23:08:09 2016 -0800 cpu/qemu-x86: Use run_romstage instead of custom inline assembly Now that passing the BIST result to romstage is no longer required, we no longer need to use custom assembly to call into romstage. Instead, a lot of the logic in the bootblock can now be replaced by a single call to run_romstage(). This is another step in converging the bootblock with the generic bootblock logic in lib/. Change-Id: I66436c8fba5121a3758d02955f691ac9d273b049 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/bootblock.c | 34 ++-------------------------------- 1 file changed, 2 insertions(+), 32 deletions(-) diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index b4700a7..056bde4 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -18,32 +18,8 @@ /* Called from assembly. Prototype not needed by external .c file */ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); -/* - * TODO: Implement a generic fallback/normal mechanism - */ -static const char *get_next_stage_name(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) - return CONFIG_CBFS_PREFIX "/romstage"; - - /* BOOTBLOCK_NORMAL not implemented */ - return CONFIG_CBFS_PREFIX "/romstage"; -} - -static void enter_romstage(void *romstage_entry, uint32_t bist) -{ - asm volatile ( - "jmp *%0\n\t" - : : "r" (romstage_entry), "a" (bist) - ); -} - asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) { - void *entry; - struct cbfs_stage *romstage; - const char* target1 = get_next_stage_name(); - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) console_init(); @@ -53,14 +29,8 @@ asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) */ report_bist_failure(bist); - romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + run_romstage(); - /* - * TODO: Do something constructive with tsc_lo and tsc_hi - */ - if (romstage) { - entry = (void *)(uintptr_t)romstage->entry; - enter_romstage(entry, bist); - } + /* Should never be reached, but halt just in case. */ halt(); }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016