coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel/skylake: Remove check for Microcode loaded by ME
by Martin Roth 11 Jan '16

11 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12854 -gerrit commit 147cf9a419a190ac5aa480cf7239d4997031c383 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 6 16:24:49 2016 -0700 intel/skylake: Remove check for Microcode loaded by ME This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/skylake/bootblock/cpu.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index bc9d638..6fc4d92 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -171,32 +171,11 @@ static void check_for_clean_reset(void) soft_reset(); } -static void patch_microcode(void) -{ - const struct microcode *patch; - u32 current_rev; - msr_t msr; - - patch = intel_microcode_find(); - - current_rev = read_microcode_rev(); - - /* If PRMRR/SGX is supported the FIT microcode load step will set - * msr 0x08b with the Patch revision id one less than the id in the - * microcode binary. The PRMRR support is indicated in the MSR - * MTRRCAP[12]. Check for this feature and avoid reloading the - * same microcode during early cpu initialization. - */ - msr = rdmsr(MTRR_CAP_MSR); - if ((msr.lo & PRMRR_SUPPORTED) && (current_rev != patch->rev - 1)) - intel_update_microcode_from_cbfs(); -} - static void bootblock_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - patch_microcode(); + intel_update_microcode_from_cbfs(); }

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New patch to review for coreboot: toolchain.inc: Fix whitespace issues and wrap long lines
by Martin Roth 11 Jan '16

11 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12889 -gerrit commit 520d36f34b52e3fde25748d63bfa3504a92524b4 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 11 10:30:24 2016 -0700 toolchain.inc: Fix whitespace issues and wrap long lines Change-Id: Iad4dc0af8af508a7e3eb0d9227b2f7c54511f130 Signed-off-by: Martin Roth <martinroth(a)google.com> --- toolchain.inc | 88 ++++++++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 63 insertions(+), 25 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index 8bb0aae..eb1f087 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -52,18 +52,18 @@ MAP-libverstage := verstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 -ARCHDIR-x86_64 := x86 +ARCHDIR-x86_64 := x86 ARCHDIR-arm := arm ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv ARCHDIR-mips := mips -CFLAGS_arm += -CFLAGS_arm64 += -mgeneral-regs-only +CFLAGS_arm += +CFLAGS_arm64 += -mgeneral-regs-only CFLAGS_mips += -mips32r2 -G 0 -mno-abicalls -fno-pic CFLAGS_riscv += CFLAGS_x86_32 += -CFLAGS_x86_64 += -mcmodel=large -mno-red-zone +CFLAGS_x86_64 += -mcmodel=large -mno-red-zone # Some boards only provide 2K stacks, so storing lots of data there leads to # problems. Since C rules don't allow us to statically determine the maximum @@ -97,7 +97,10 @@ toolchain_to_dir = \ # parameter to create_class_compiler below in init_standard_toolchain map_stage = $(strip $(if $(MAP-$(1)),$(MAP-$(1)),$(1))) set_stage_toolchain= \ - $(foreach arch,$(ARCH_SUPPORTED),$(eval ARCH-$(1)-$($(shell echo CONFIG_ARCH_$(call map_stage,$(1))_$(arch) | tr '[:lower:]' '[:upper:]')) := $(arch))) + $(foreach arch,$(ARCH_SUPPORTED), \ + $(eval ARCH-$(1)-$($(shell \ + echo CONFIG_ARCH_$(call map_stage,$(1))_$(arch) | \ + tr '[:lower:]' '[:upper:]')) := $(arch))) # create_class_compiler: Used to create compiler tool set for # special classes @@ -140,7 +143,8 @@ init_standard_toolchain = \ $(eval $(call create_class_compiler,$(1),$(ARCH-$(1)-y))) init_stages = \ - $(foreach stage,$(COREBOOT_STANDARD_STAGES),$(eval $(call init_standard_toolchain,$(stage)))) + $(foreach stage,$(COREBOOT_STANDARD_STAGES), \ + $(eval $(call init_standard_toolchain,$(stage)))) $(eval $(call toolchain_to_dir)) @@ -155,21 +159,33 @@ COMPILERFAIL:=0 IASLFAIL:=0 ifneq ($(CONFIG_ANY_TOOLCHAIN),y) -$(foreach arch,$(sort $(foreach stage,$(COREBOOT_STANDARD_STAGES),$(ARCH-$(stage)-y))), \ - $(if $(shell if [ -n "$(CC_$(arch))" ]; then $(CC_$(arch)) -v 2>&1 |grep -q "coreboot toolchain" || echo not-coreboot; else echo not-coreboot; fi), \ - $(eval COMPILERFAIL:=1)$(warning The coreboot toolchain for '$(arch)' architecture was not found.))) +$(foreach arch,$(sort $(foreach stage,\ + $(COREBOOT_STANDARD_STAGES),$(ARCH-$(stage)-y))), \ + $(if $(shell if [ -n "$(CC_$(arch))" ]; then \ + $(CC_$(arch)) -v 2>&1 | grep -q "coreboot toolchain" || \ + echo not-coreboot; else echo not-coreboot; fi), \ + $(eval COMPILERFAIL:=1)\ + $(warning The coreboot toolchain for '$(arch)'\ + architecture was not found.))) #if iasl doesn't match the current coreboot version, fail the test #TODO: Figure out if iasl is even needed for the build. -$(if $(shell if [ -n "$(IASL)" ]; then $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot; else echo not-coreboot; fi), \ - $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1)$(warning The coreboot toolchain version of iasl '$(shell util/crossgcc/buildgcc -s iasl)' was not found)) +$(if $(shell if [ -n "$(IASL)" ]; then \ + $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || \ + echo not-coreboot; else echo not-coreboot; fi), \ + $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1)\ + $(warning The coreboot toolchain version of iasl \ + '$(shell util/crossgcc/buildgcc -s iasl)' was not found)) else #$(CONFIG_ANY_TOOLCHAIN) -$(foreach arch,$(sort $(foreach stage,$(COREBOOT_STANDARD_STAGES),$(ARCH-$(stage)-y))), \ +$(foreach arch,$(sort \ + $(foreach stage,$(COREBOOT_STANDARD_STAGES),$(ARCH-$(stage)-y))), \ $(if $(CC_$(arch)),, $(eval COMPILERFAIL:=1) \ - $(warning No compiler found for '$(arch)' architecture. Install one or use the coreboot toolchain?)) ) + $(warning No compiler found for '$(arch)' architecture. \ + Install one or use the coreboot toolchain?)) ) #if iasl isn't present, fail #TODO: Figure out if iasl is even needed for the build. $(if $(IASL),, $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1) \ - $(warning iasl not found. Please install it or use the coreboot toolchain.)) + $(warning iasl not found. \ + Please install it or use the coreboot toolchain.)) endif ifeq ($(COMPILERFAIL),1) ifneq ($(XGCCPATH),) @@ -184,9 +200,12 @@ endif #($(IASLFAIL),1) $(warning For more toolchain build targets: run 'make help_toolchain') $(warning ) ifneq ($(CONFIG_ANY_TOOLCHAIN),y) -$(warning To try to use any toolchain in your path, run 'make menuconfig', then select) -$(warning the config option: 'General setup', and 'Allow building with any toolchain') -$(warning Note that this is NOT supported. Using it means you're on your own.) +$(warning To try to use any toolchain in your path, \ + run 'make menuconfig', then select) +$(warning the config option: 'General setup', \ + and 'Allow building with any toolchain') +$(warning Note that this is NOT supported. \ + Using it means you're on your own.) $(warning ) endif #($(CONFIG_ANY_TOOLCHAIN),y) $(error Halting the build) @@ -197,14 +216,33 @@ endif #($(NOCOMPILE),1) ifneq ($(MAKECMDGOALS),) ifneq ($(filter test-toolchain,$(MAKECMDGOALS)),) $(foreach arch, $(ARCH_SUPPORTED), \ - $(if $(shell if [ -n "$(GCC_CC_$(arch))" ]; then $(GCC_CC_$(arch)) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s gcc)" || echo not-current; fi), \ - $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of gcc for '$(arch)' architecture is not the current version.)) \ - $(if $(shell if [ -n "$(CLANG_CC_$(arch))" ]; then $(CLANG_CC_$(arch)) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s clang)" || echo not-current; fi), \ - $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of clang for '$(arch)' architecture is not the current version.)) \ - $(if $(shell if [ "$(OBJDUMP_$(arch))" != "invalidobjdump" ]; then $(OBJDUMP_$(arch)) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s binutils)" || echo not-current; fi), \ - $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of binutils for '$(arch)' architecture is not the current version.)) \ + $(if $(shell if [ -n "$(GCC_CC_$(arch))" ]; then \ + $(GCC_CC_$(arch)) -v 2>&1 | \ + grep -q "$(shell util/crossgcc/buildgcc -s gcc)" || \ + echo not-current; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1) \ + $(warning The coreboot toolchain version of gcc for '$(arch)' \ + architecture is not the current version.)) \ + $(if $(shell if [ -n "$(CLANG_CC_$(arch))" ]; then \ + $(CLANG_CC_$(arch)) -v 2>&1 | \ + grep -q "$(shell util/crossgcc/buildgcc -s clang)" || \ + echo not-current; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)\ + $(warning The coreboot toolchain version of clang for \ + '$(arch)' architecture is not the current version.)) \ + $(if $(shell if [ "$(OBJDUMP_$(arch))" != "invalidobjdump" ]; then \ + $(OBJDUMP_$(arch)) -v 2>&1 | \ + grep -q "$(shell util/crossgcc/buildgcc -s binutils)" || \ + echo not-current; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)\ + $(warning The coreboot toolchain version of binutils for \ + '$(arch)' architecture is not the current version.)) \ ) -$(if $(shell if [ -n "$(IASL)" ]; then $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot; fi), \ - $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of iasl is not the current version)) +$(if $(shell if [ -n "$(IASL)" ]; then $(IASL) -v 2>&1 | \ + grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || \ + echo not-coreboot; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)\ + $(warning The coreboot toolchain version of iasl \ + is not the current version)) endif # ifneq ($(filter crossgcc_check%,$(MAKECMDGOALS)),) endif # ifneq ($(MAKECMDGOALS),)

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Patch set updated for coreboot: Makefile: Add toolchain version check
by Martin Roth 11 Jan '16

11 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12846 -gerrit commit 0d0f7fec77ae8566dd0d0e83ba1b1917c5bbb540 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 5 16:07:42 2016 -0700 Makefile: Add toolchain version check This is an initial check for the coreboot toolchain versions. It currently checks binutils, gcc, clang, and iasl. The other components are slightly more difficult to test, but should follow on shortly. If the toolchain is not the correct version, make will halt with an error. Change-Id: I41daf6c4545c01dc21231d78fd081bbcf77c4726 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 9 +++++++++ toolchain.inc | 15 +++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 3b2a75b..d7bb018 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -488,6 +488,7 @@ help_toolchain help:: @echo ' crossgcc-clean - Remove all built coreboot cross-compilers' @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' @echo ' clang - Build coreboot clang compiler' + @echo ' test-toolchain - Reports if toolchain components are out of date' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' @@ -561,6 +562,14 @@ crossgcc-clean: clean-for-update tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) +test-toolchain: +ifeq ($(COMPILER_OUT_OF_DATE),1) + echo "The coreboot toolchain is not the current version." + $(error ) +else + echo "The coreboot toolchain is the current version." +endif # ifeq ($(COMPILER_OUT_OF_DATE),1) + ########################################################################### # Common recipes for all stages ########################################################################### diff --git a/toolchain.inc b/toolchain.inc index 5836a19..8bb0aae 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -193,3 +193,18 @@ $(error Halting the build) endif #($(COMPILERFAIL),1) endif #($(NOCOMPILE),1) + +ifneq ($(MAKECMDGOALS),) +ifneq ($(filter test-toolchain,$(MAKECMDGOALS)),) +$(foreach arch, $(ARCH_SUPPORTED), \ + $(if $(shell if [ -n "$(GCC_CC_$(arch))" ]; then $(GCC_CC_$(arch)) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s gcc)" || echo not-current; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of gcc for '$(arch)' architecture is not the current version.)) \ + $(if $(shell if [ -n "$(CLANG_CC_$(arch))" ]; then $(CLANG_CC_$(arch)) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s clang)" || echo not-current; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of clang for '$(arch)' architecture is not the current version.)) \ + $(if $(shell if [ "$(OBJDUMP_$(arch))" != "invalidobjdump" ]; then $(OBJDUMP_$(arch)) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s binutils)" || echo not-current; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of binutils for '$(arch)' architecture is not the current version.)) \ +) +$(if $(shell if [ -n "$(IASL)" ]; then $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot; fi), \ + $(eval COMPILER_OUT_OF_DATE:=1)$(warning The coreboot toolchain version of iasl is not the current version)) +endif # ifneq ($(filter crossgcc_check%,$(MAKECMDGOALS)),) +endif # ifneq ($(MAKECMDGOALS),)

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Patch set updated for coreboot: ec/lenovo/h8: Add USB Always On fields
by Marian Tietz 11 Jan '16

11 Jan '16

Marian Tietz (mtcoreboot(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12888 -gerrit commit 25c96c684e4c645e2bc9296f8396b14a8b5d2b43 Author: Marian Tietz <mtcoreboot(a)gmail.com> Date: Sat Jan 9 17:41:14 2016 +0100 ec/lenovo/h8: Add USB Always On fields USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN is used for enabling the feature (on PTS) and AOCF is the configuration field for the different modes. The modes are (according to Peter Stuge): 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also activates this feature on the X220. On PTS activate the dedicated charging port to work under AC in all states and in battery under S3. On wake-up the port is set back to USB2 mode. To test this functionality USB devices (e.g. a smartphone) should be able to negotiate full power from the dedicated charging port in S3 using a normal data cable. Without the Always On functionality this is not possible. Change-Id: Ief8de3e41fd6a701c6b3dbce81118d5eeb0fa648 Signed-off-by: Marian Tietz <mtcoreboot(a)gmail.com> --- src/ec/lenovo/h8/acpi/ec.asl | 4 ++++ src/mainboard/lenovo/x220/acpi/platform.asl | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 085492d..9adf6d9 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -32,6 +32,10 @@ Device(EC) HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ + Offset (0x0D), + AOEN, 1, /* USB Always On Enable */ + , 1, + AOCF, 2, /* USB Always On Config */ Offset (0x1a), DKR2, 1, /* Dock register 2 */ Offset (0x2a), diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 3e9225c..70e6088 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -20,6 +20,15 @@ Method(_PTS,1) { \_SB.PCI0.LPCB.EC.RADI(0) + + Store (1, \_SB.PCI0.LPCB.EC.AOEN) + + /* + * 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off + * 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off + * 10, 01 => equivalent to 00 + */ + Store (0, \_SB.PCI0.LPCB.EC.AOCF) } /* The _WAK method is called on system wakeup */ @@ -30,6 +39,9 @@ Method(_WAK,1) Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) + /* Deactivate dedicated charging port, activate USB2.0 */ + Store (0, \_SB.PCI0.LPCB.EC.AOEN) + /* Not implemented. */ Return(Package(){0,0}) }

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Patch merged into coreboot/master: fsp1_1: Remove #if protection in header - It's not needed
by gerrit＠coreboot.org 10 Jan '16

10 Jan '16

the following patch was just integrated into master: commit 229d427c12f99173c75a11699b4fa619254f4594 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 7 15:33:38 2016 -0700 fsp1_1: Remove #if protection in header - It's not needed There's nothing in these files that needs to be hidden if GOP support is disabled. Removing this allows skylake to build when GOP support is turned off. Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12859 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang(a)intel.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/12859 for details. -gerrit

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Patch merged into coreboot/master: lenovo/x220: Enable USB 3 controller
by gerrit＠coreboot.org 10 Jan '16

10 Jan '16

the following patch was just integrated into master: commit 7c6c4df68cf6dd7e79851595491f3f45e4ea611f Author: Marian Tietz <mtcoreboot(a)gmail.com> Date: Sat Jan 9 18:18:47 2016 +0100 lenovo/x220: Enable USB 3 controller Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot(a)gmail.com> Reviewed-on: https://review.coreboot.org/12882 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See https://review.coreboot.org/12882 for details. -gerrit

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Patch set updated for coreboot: mainboard/lenovo: reserve century byte
by Alexander Couzens 10 Jan '16

10 Jan '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11853 -gerrit commit 42c3afa49bb1ccbe9072243a058657e2b627ce1d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Oct 10 16:04:59 2015 +0200 mainboard/lenovo: reserve century byte The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/g505s/cmos.layout | 3 ++- src/mainboard/lenovo/t400/cmos.layout | 7 ++++--- src/mainboard/lenovo/t420s/cmos.layout | 6 ++++-- src/mainboard/lenovo/t430s/cmos.layout | 5 +++-- src/mainboard/lenovo/t520/cmos.layout | 5 +++-- src/mainboard/lenovo/t530/cmos.layout | 6 ++++-- src/mainboard/lenovo/t60/cmos.layout | 10 ++++++---- src/mainboard/lenovo/x200/cmos.layout | 5 ++--- src/mainboard/lenovo/x201/cmos.layout | 6 +++--- src/mainboard/lenovo/x220/cmos.layout | 3 ++- src/mainboard/lenovo/x230/cmos.layout | 6 ++++-- src/mainboard/lenovo/x60/cmos.layout | 10 ++++++---- 12 files changed, 43 insertions(+), 29 deletions(-) diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index d83bb14..61c5690 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -24,7 +24,8 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +#400 8 r 8 reserved for century byte +408 1 e 1 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index e9764a5..8e642f8 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -53,8 +53,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: EC -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 10 sata_mode @@ -82,8 +81,10 @@ entries # coreboot config options: graphics 944 2 e 12 hybrid_graphics_mode +#946 6 r 0 unused -#946 2 r 0 unused +# coreboot config options: EC +952 8 h 0 volume # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index cb76e70..4362840 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused + +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 0d3d089..16b499a 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index bd9fd2a..2cf3629 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index bd9fd2a..e21c197 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused + +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 29ea2ef..e5879d6 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -52,9 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -66,7 +64,11 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused +#938 7 r 0 unused + +# coreboot config options: cpu +944 1 e 2 hyper_threading +#945 7 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 5f50bd4..931cb4a 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -53,8 +53,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: EC -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 10 sata_mode @@ -80,7 +79,7 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size -#944 2 r 0 unused +944 8 h 0 volume # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index d231a11..7d4aeae 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -75,8 +75,8 @@ entries # coreboot config options: northbridge 424 3 e 10 gfx_uma_size - -#427 557 r 0 unused +#427 5 r 0 unused +432 8 h 0 volume # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 8f147cc..ca2c45c 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -78,6 +78,7 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size #435 549 r 0 unused +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index e8cd140..29c2066 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused + +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index e267bb5..54a2799 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -52,9 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -66,7 +64,11 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused +#938 6 r 0 unused + +# coreboot config options: cpu +944 1 e 2 hyper_threading +#945 7 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum

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Patch set updated for coreboot: mainboard/lenovo: reserve century byte
by Alexander Couzens 10 Jan '16

10 Jan '16

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11853 -gerrit commit 2cfe1c3fdcce3b4d0181b5bdf3ac635555dbf148 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Oct 10 16:04:59 2015 +0200 mainboard/lenovo: reserve century byte The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/mainboard/lenovo/g505s/cmos.layout | 3 ++- src/mainboard/lenovo/t400/cmos.layout | 6 +++--- src/mainboard/lenovo/t420s/cmos.layout | 6 ++++-- src/mainboard/lenovo/t430s/cmos.layout | 5 +++-- src/mainboard/lenovo/t520/cmos.layout | 5 +++-- src/mainboard/lenovo/t530/cmos.layout | 6 ++++-- src/mainboard/lenovo/t60/cmos.layout | 10 ++++++---- src/mainboard/lenovo/x200/cmos.layout | 7 +++---- src/mainboard/lenovo/x201/cmos.layout | 4 +++- src/mainboard/lenovo/x220/cmos.layout | 3 ++- src/mainboard/lenovo/x230/cmos.layout | 6 ++++-- src/mainboard/lenovo/x60/cmos.layout | 10 ++++++---- 12 files changed, 43 insertions(+), 28 deletions(-) diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index d83bb14..61c5690 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -24,7 +24,8 @@ entries 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail +#400 8 r 8 reserved for century byte +408 1 e 1 power_on_after_fail 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index e9764a5..4017845 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -53,8 +53,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: EC -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 10 sata_mode @@ -83,7 +82,8 @@ entries # coreboot config options: graphics 944 2 e 12 hybrid_graphics_mode -#946 2 r 0 unused +# coreboot config options: EC +946 8 h 0 volume # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index cb76e70..4362840 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused + +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 0d3d089..16b499a 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index bd9fd2a..2cf3629 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index bd9fd2a..e21c197 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused + +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 29ea2ef..e5879d6 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -52,9 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -66,7 +64,11 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused +#938 7 r 0 unused + +# coreboot config options: cpu +944 1 e 2 hyper_threading +#945 7 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 5f50bd4..e2e3011 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -53,8 +53,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: EC -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 10 sata_mode @@ -79,8 +78,8 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size - -#944 2 r 0 unused +#944 5 r 0 unused +948 8 h 0 volume # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index d231a11..79eb9f8 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -75,6 +75,8 @@ entries # coreboot config options: northbridge 424 3 e 10 gfx_uma_size +#427 1 r 0 unused +432 8 h 0 volume #427 557 r 0 unused diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 8f147cc..ca2c45c 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -78,6 +78,7 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size #435 549 r 0 unused +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index e8cd140..29c2066 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -52,7 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -400 8 h 0 volume +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -77,7 +77,9 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused +#435 5 r 0 unused + +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index e267bb5..d179028 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -52,9 +52,7 @@ entries 395 4 e 6 debug_level #399 1 r 0 unused -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +#400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi @@ -66,7 +64,11 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused +#938 7 r 0 unused + +# coreboot config options: cpu +944 1 e 2 hyper_threading +#945 7 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum

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New patch to review for coreboot: ec/lenovo/h8: Add USB Always On fields
by nemo 10 Jan '16

10 Jan '16

nemo (mtcoreboot(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12888 -gerrit commit cafe06a1f0eba4dbe3f9fe5c33ea13db3c86c8de Author: Marian Tietz <mtcoreboot(a)gmail.com> Date: Sat Jan 9 17:41:14 2016 +0100 ec/lenovo/h8: Add USB Always On fields USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN is used for enabling the feature (on PTS) and AOCF is the configuration field for the different modes. The modes are (according to Peter Stuge): 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 Change-Id: Ief8de3e41fd6a701c6b3dbce81118d5eeb0fa648 Signed-off-by: Marian Tietz <mtcoreboot(a)gmail.com> --- src/ec/lenovo/h8/acpi/ec.asl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 085492d..9adf6d9 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -32,6 +32,10 @@ Device(EC) HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ + Offset (0x0D), + AOEN, 1, /* USB Always On Enable */ + , 1, + AOCF, 2, /* USB Always On Config */ Offset (0x1a), DKR2, 1, /* Dock register 2 */ Offset (0x2a),

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Patch set updated for coreboot: lenovo/x220: Enable USB 3 controller
by nemo 10 Jan '16

10 Jan '16

nemo (mtcoreboot(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12882 -gerrit commit 2416ee6e46aaaf41b3fbe22cabeeee1ec059b3ac Author: Marian Tietz <mtcoreboot(a)gmail.com> Date: Sat Jan 9 18:18:47 2016 +0100 lenovo/x220: Enable USB 3 controller Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot(a)gmail.com> --- src/mainboard/lenovo/x220/devicetree.cb | 4 +++- src/mainboard/lenovo/x220/romstage.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 9c9ac7c..9f25658 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -109,7 +109,9 @@ chip northbridge/intel/sandybridge end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 + device pci 1c.6 on + subsystemid 0x17aa 0x21db + end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on subsystemid 0x17aa 0x21db diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 1d89d92..ce3f276 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -54,7 +54,7 @@ void pch_enable_lpc(void) void rcba_config(void) { /* Disable unused devices (board specific) */ - RCBA32(FD) = 0x1fe41fe3; + RCBA32(FD) = 0x1fa41fe3; RCBA32(BUC) = 0; }

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coreboot-gerrit January 2016