coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503 -gerrit commit e7c0dcf2e104c47af8fe19d9d7e5f984a1012fae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 11:01:17 2015 -0500 x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards Previously, the x86 romstage build process was unconditionally creating a romstage.inc and adding it to crt0s. This step is inherently not necessary in the !ROMCC case becaue the romstage.inc was created by the compiler outputting assembler. That means MAINBOARDDIR/romstage.c is truly a C environment that requires some sort of assembler stub to call into (cache_as_ram.inc from the chipset dirs). Therefore, remove this processing. The result is that MAINBOARDDIR/romstage.c can use the normal build steps in creating an object and linking. The layout of romstage.elf will change but that's only from a symbol perspective. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built multitude of boards. Compared readelf -e output. Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b0546f5..00d8d27 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -125,13 +125,19 @@ endif crt0s += $(cpu_incs-y) -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc +ifneq ($(CONFIG_ROMCC),y) + +romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -ifeq ($(CONFIG_ROMCC),y) +else # CONFIG_ROMCC == y + +# This order matters. The mainboards requiring ROMCC need their mainboard +# code to follow the prior crt0s files for program flow control. The +# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage +# because of the instruction sequen fall-through. +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc -endif -ifeq ($(CONFIG_ROMCC),y) ifeq ($(CONFIG_MMX),y) ifeq ($(CONFIG_SSE),y) ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE @@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" $(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@ -else -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" - $(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - @printf " POST romstage.inc\n" - sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ - -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp - mv $@.tmp $@ endif romstage-srcs += $(objgenerated)/crt0.S

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Patch set updated for coreboot: x86: bootblock: remove linking and program flow from build system
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495 -gerrit commit cac9e96d48182e2362910ef7ed2fd4c8484bb6ea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 00:41:29 2015 -0500 x86: bootblock: remove linking and program flow from build system The build system was previously determining the flow and linking scripts bootblock code by the order of files added to the bootblock_inc bootblock-y variables.Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S and bootblock.ld is added so that bootblock can be built and linked using the default build rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 54 +++++++------------------- src/arch/x86/bootblock.S | 51 ++++++++++++++++++++++++ src/arch/x86/bootblock.ld | 29 ++++++++++++++ src/arch/x86/id.inc | 2 + src/cpu/dmp/vortex86ex/Kconfig | 4 ++ src/cpu/dmp/vortex86ex/Makefile.inc | 2 - src/cpu/dmp/vortex86ex/biosdata.inc | 2 +- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 + src/northbridge/via/vx800/Kconfig | 8 ++++ src/northbridge/via/vx800/Makefile.inc | 1 - src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/Makefile.inc | 1 - src/soc/intel/baytrail/Kconfig | 4 ++ src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/baytrail/bootblock/Makefile.inc | 1 - src/soc/intel/braswell/Kconfig | 4 ++ src/soc/intel/braswell/Makefile.inc | 1 - src/soc/intel/braswell/bootblock/Makefile.inc | 1 - src/soc/intel/broadwell/Kconfig | 4 ++ src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/bootblock/Makefile.inc | 1 - src/soc/intel/skylake/Kconfig | 4 ++ src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/Makefile.inc | 1 - src/southbridge/nvidia/ck804/Kconfig | 5 +++ src/southbridge/nvidia/ck804/Makefile.inc | 1 - src/southbridge/nvidia/mcp55/Kconfig | 4 ++ src/southbridge/nvidia/mcp55/Makefile.inc | 1 - src/southbridge/sis/sis966/Kconfig | 12 +++++- src/southbridge/sis/sis966/Makefile.inc | 1 - src/southbridge/via/k8t890/Kconfig | 4 ++ src/southbridge/via/k8t890/Makefile.inc | 1 - 32 files changed, 155 insertions(+), 58 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a9d708d..b0546f5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) -bootblock-srcs += $(src)/arch/x86/failover.ld -bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld -bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld -bootblock-srcs += $(src)/arch/x86/id.ld -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock-srcs += $(src)/cpu/intel/fit/fit.ld -endif - -# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead? -bootblock_inc = $(src)/arch/x86/prologue.inc -bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc -bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc -bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc -bootblock_inc += $(src)/arch/x86/id.inc -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_inc += $(src)/cpu/intel/fit/fit.inc -endif -bootblock_inc += $(chipset_bootblock_inc) +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated bootblock.inc is a proper +# dependency. Make the same true for the linker sript. +bootblock-y += bootblock.S +$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc -ifeq ($(CONFIG_SSE),y) -bootblock_inc += $(src)/cpu/x86/sse_enable.inc -endif -bootblock_inc += $(objgenerated)/bootblock.inc -bootblock_inc += $(src)/arch/x86/walkcbfs.S +bootblock-y += bootblock.ld +$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ endif -$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) +# This is a hack in case there are no per chipset linker files. +$(objgenerated)/empty: + touch $@ + +$(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock.ld, $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty @printf " GEN $(subst $(obj)/,,$(@))\n" cat $^ >> $@.tmp mv $@.tmp $@ -$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ - -$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $< > $(basename $(a)).disasm - -$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ - $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) - $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld else - $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld endif diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S new file mode 100644 index 0000000..7276c7a --- /dev/null +++ b/src/arch/x86/bootblock.S @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <arch/x86/id.inc> + +#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#include <cpu/intel/fit/fit.inc> +#endif + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generated by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions at the beginning of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> + +#include <arch/x86/walkcbfs.S> diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld new file mode 100644 index 0000000..6835430 --- /dev/null +++ b/src/arch/x86/bootblock.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/x86/failover.ld> +#include <cpu/x86/16bit/entry16.ld> +#include <cpu/x86/16bit/reset16.ld> +#include <arch/x86/id.ld> +#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#include <cpu/intel/fit/fit.ld> +#endif + +/* Include generated .ld files. */ +#include <generated/bootblock.ld> diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc index f8aba0b..a3df25e 100644 --- a/src/arch/x86/id.inc +++ b/src/arch/x86/id.inc @@ -1,3 +1,5 @@ +#include <build.h> + .section ".id", "a", @progbits .globl __id_start diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 2c893ac..3bd6c2c 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -77,4 +77,8 @@ config PLL_500_375_33 endchoice +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "cpu/dmp/vortex86ex/chipset_bootblock.inc" + endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 7924ca4..15ea4ea 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc index 5e6a70f..4f408b4 100644 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ b/src/cpu/dmp/vortex86ex/biosdata.inc @@ -37,7 +37,7 @@ .section ".dmp_kbd_fw_part1", "a", @progbits - #include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc" + #include "dmp_kbd_fw_part1.inc" .previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc new file mode 100644 index 0000000..bdcda1d --- /dev/null +++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc @@ -0,0 +1,2 @@ +#include "biosdata.inc" +#include "biosdata_ex.inc" diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..d7d5349 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT + +if NORTHBRIDGE_VIA_VX800 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx800/romstrap.inc" + +endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 90ab0af..d3c4c7b 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -25,7 +25,6 @@ ramstage-y += vga.c ramstage-y += lpc.c ramstage-y += ide.c -chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 617074f..335c265 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -42,4 +42,8 @@ config VGA_BIOS_ID string default "1106,7122" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx900/romstrap.inc" + endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 6178c11..e761f90 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -46,7 +46,6 @@ ramstage-y += lpc.c ramstage-y += ./../../../drivers/pc80/vga/vga_io.c -chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..921f568 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/baytrail/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 7417526..e8c5022 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc deleted file mode 100644 index 3a40251..0000000 --- a/src/soc/intel/baytrail/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4c9c8aa..ab99a08 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -198,4 +198,8 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/braswell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 9bf6cb2..755c15a 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc deleted file mode 100644 index 17d1ee8..0000000 --- a/src/soc/intel/braswell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 30c0093..c2db2a1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/broadwell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4b14ff8..ca295fc 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc deleted file mode 100644 index 2ca5a45..0000000 --- a/src/soc/intel/broadwell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d53e67e..843cb8a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -200,4 +200,8 @@ config UART_DEBUG select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index defb945..2e119a1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc deleted file mode 100644 index a31f588..0000000 --- a/src/soc/intel/skylake/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 4126355..42dce07 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -41,4 +41,9 @@ config CK804_NUM config HPET_MIN_TICKS hex default 0xfa + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/ck804/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index de1162a..69dd4b2 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c -chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 89aa452..666d3f8 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3 int default 4 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/mcp55/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index fb9c3fb..74ef14c 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif -chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 390589c..20f3bff 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET +if SOUTHBRIDGE_SIS_SIS966 + config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 + default "southbridge/sis/sis966/bootblock.c" config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + default 0xfef00000 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/sis/sis966/romstrap.inc" + +endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 71fff02..e703e1f 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -15,7 +15,6 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..76be0c1 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -51,4 +51,8 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/via/k8t890/romstrap.inc" + endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 18cb5aa..2789499 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c ramstage-y += error.c ramstage-y += chrome.c -chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld endif

1 0

Patch set updated for coreboot: rules.h: add fall through where no ENV_<STAGE> is set
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513 -gerrit commit 4229ee11cb98568ef3bc683b8a9ae4c0b778ab69 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 16:28:15 2015 -0500 rules.h: add fall through where no ENV_<STAGE> is set There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/rules.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/include/rules.h b/src/include/rules.h index 523031a..2e7f88f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,13 +63,23 @@ #define ENV_SECMON 0 #define ENV_VERSTAGE 1 -#else +#elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 + +#else +/* Default case of nothing set for random blob generation using + * create_class_compiler that isn't bound to a stage. */ +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #endif /* For romstage and ramstage always build with simple device model, ie.

1 0

Patch set updated for coreboot: x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524 -gerrit commit 8caecddd634b185ac2aa83f1eb0f5cc9d2287a71 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:45:18 2015 -0500 x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 +--------- src/include/memlayout.h | 6 +++--- src/lib/Makefile.inc | 9 ++++++--- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b018f7c..885bb7f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -276,17 +276,11 @@ ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) -else -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64)) -endif - # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod cp $< $@ -else +endif ramstage-y += memlayout.ld @@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout. @printf " CC $(subst $(obj)/,,$(@))\n" $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld -endif - $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index ef47f6b..82fa73e 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -166,7 +166,7 @@ REGION(watchdog_tombstone, addr, size, 4) \ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); -#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE || ENV_ROMSTAGE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ @@ -176,7 +176,7 @@ #define CBMEM_INIT_HOOKS #endif -#if ENV_RAMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE #define DRIVERS_RODATA \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(pci_drivers) \ @@ -206,7 +206,7 @@ #define DATA_EXTRA \ PROVIDE(_preram_cbmem_console = .); \ PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE || ENV_RMODULE +#elif ENV_RAMSTAGE #define DATA_EXTRA \ SYMBOL_CURRENT_LOC(bs_init_begin) \ KEEP(*(.bs_init)); \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a89f7d4..f4d8c2c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -218,9 +218,12 @@ define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map - -$(strip $(1)).rmod: $(strip $(1)) - $$(RMODTOOL) -i $$^ -o $$@ endef endif + +$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@ + +$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@

1 0

Patch set updated for coreboot: rmodtool: make rmodule parameter section optional
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523 -gerrit commit c71a7cb5d29267a784b9ce9242c07200eb960491 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:39:10 2015 -0500 rmodtool: make rmodule parameter section optional There are currently 2 uses for rmodule programs: stand alone programs that are separate from the coreboot stages and a relocatable ramstage. For the ramstage usage there's no reason to require a rmodule parameter section. Therefore make this optional. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built ramstage w/ normal linking (w/o a rmodule parameter section). No error. Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- util/cbfstool/rmodule.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index c35eff7..1f41d17 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx) static int populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr, - int nsyms, const char *strtab) + int nsyms, const char *strtab, int optional) { int i; Elf64_Sym *syms; @@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr, *addr = syms[i].st_value; return 0; } + + if (optional) { + DEBUG("optional symbol '%s' not found.\n", sym_name); + *addr = 0; + return 0; + } + ERROR("symbol '%s' not found.\n", sym_name); return -1; } @@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx) } if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin, - nsyms, strtab)) + nsyms, strtab, 1)) return -1; if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end, - nsyms, strtab)) + nsyms, strtab, 1)) return -1; - if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab)) + if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0)) return -1; - if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) + if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0)) return -1; /* Honor the entry point within the ELF header. */

1 0

Patch set updated for coreboot: linking: add and use LDFLAGS_common
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522 -gerrit commit 75d89572255b43559c584b38446cefaffac01522 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:15:17 2015 -0500 linking: add and use LDFLAGS_common Add an LDFLAGS_common variable and use that for each stage during linking within all the architectures. All the architectures support gc-sections, and as such they should be linking in the same way. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage. Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/arm/Makefile.inc | 8 ++++---- src/arch/arm64/Makefile.inc | 8 ++++---- src/arch/mips/Makefile.inc | 6 +++--- src/arch/riscv/Makefile.inc | 6 +++--- src/arch/x86/Makefile.inc | 6 +++--- src/cpu/x86/smm/Makefile.inc | 2 +- src/lib/Makefile.inc | 4 ++-- toolchain.inc | 6 ++++++ 8 files changed, 26 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 7a4409e..82ce8b3 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -63,7 +63,7 @@ bootblock-y += clock.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group verstage-y += boot.c verstage-y += div0.c @@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index a625c7a..5294b69 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -73,7 +73,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-y += boot.c verstage-y += div0.c @@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld + $(LD_ramstage) $(LDFLAGS_ramstage) $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index e3aff0c..fab8a05 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_MIPS @@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_MIPS @@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0f3eb0f..5233faa 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -40,7 +40,7 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \ + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) @@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9e5110f..b018f7c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -180,7 +180,7 @@ endif $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \ grep -v "Empty loadable segment detected" && \ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ @@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -292,7 +292,7 @@ ramstage-y += memlayout.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld endif diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 239689e..7b4ad59 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod else # CONFIG_SMM_TSEG $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d8cd1d8..a89f7d4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c -RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic +RMODULE_LDFLAGS := -z defs -Bsymbolic # rmodule_link_rules is a function that should be called with: # (1) the object name to link @@ -216,7 +216,7 @@ RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map $(strip $(1)).rmod: $(strip $(1)) diff --git a/toolchain.inc b/toolchain.inc index 195ed77..d143dd7 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -69,6 +69,11 @@ CFLAGS_riscv += CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone +# Set the LDFLAGS for each arch. +LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +$(foreach arch,$(ARCH_SUPPORTED), \ + $(eval LDFLAGS_$(arch):=$(LDFLAGS_common))) + # Some boards only provide 2K stacks, so storing lots of data there leads to # problems. Since C rules don't allow us to statically determine the maximum # stack use, we use 1.5K as heuristic, assuming that we typically have lots @@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2)) CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) COMPILER_RT_$(1) := $$(COMPILER_RT_$(2)) COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2)) +LDFLAGS_$(1) = $$(LDFLAGS_$(2)) endef # define_class: Allows defining any program as dynamic class and compiler tool

1 0

Patch set updated for coreboot: rmodule: use program.ld for linking
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517 -gerrit commit 75034faafe688b667bd99c9394070405ec377aed Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 12:59:26 2015 -0500 rmodule: use program.ld for linking Bring rmodule linking into the common linking method. The __rmodule_entry symbol was removed while using a more common _start symbol. The rmodtool will honor the entry point found within the ELF header. Add ENV_RMODULE so that one can distinguish the environment when generating linker scripts for rmodules. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- Makefile.inc | 3 + src/arch/arm64/include/arch/header.ld | 10 +++- src/arch/arm64/stage_entry.S | 4 +- src/arch/x86/c_start.S | 2 - src/arch/x86/include/arch/header.ld | 2 +- src/cpu/x86/Makefile.inc | 4 +- src/cpu/x86/sipi_vector.S | 10 ++-- src/cpu/x86/smm/smm_stub.S | 6 +- src/include/memlayout.h | 22 ++++++-- src/include/rmodule.h | 4 +- src/include/rules.h | 16 ++++++ src/lib/rmodule.ld | 101 ++-------------------------------- util/cbfstool/rmodule.c | 8 +-- 13 files changed, 67 insertions(+), 125 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..b5d8309 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) +# Provide a macro to determine environment for free standing rmodules. +$(foreach supported_arch,$(ARCH_SUPPORTED), \ + $(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__)) ####################################################################### # Helper functions for math and various file placement matters. diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index fa8fdfa..b3112e3 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -17,6 +17,8 @@ * Foundation, Inc. */ +#include <rules.h> + /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) @@ -26,7 +28,13 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBTLOCK TARGET(binary) #endif + +/* secmon uses rmodules */ +#if ENV_RMODULE +ENTRY(_start) +#else ENTRY(stage_entry) +#endif diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 4e15dbb..dbc6cad 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment) 2002: .endm -ENTRY(__rmodule_entry) +ENTRY(_start) split_bsp_path /* Save the arguments to secmon in x25 */ mov x25, x0 b arm64_c_environment -ENDPROC(__rmodule_entry) +ENDPROC(_start) /* * Setup SCTLR so that: diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 582966b..ad4589a 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -23,8 +23,6 @@ thread_stacks: .code32 #endif .globl _start - .globl __rmodule_entry -__rmodule_entry: _start: cli lgdt %cs:gdtaddr diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 55547ad..0262c92 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -24,7 +24,7 @@ PHDRS to_load PT_LOAD; } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_RMODULE ENTRY(_start) #elif ENV_ROMSTAGE ENTRY(protected_start) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9ec0768..e9394b2 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) else -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) endif $(SIPI_BIN): $(SIPI_RMOD) diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index c7b1097..0887b0a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -56,10 +56,8 @@ ap_count: .text .code16 -.global ap_start -.global __rmodule_entry -__rmodule_entry: -ap_start: +.global _start +_start: cli xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ @@ -74,9 +72,9 @@ ap_start: /* The gdtaddr needs to be releative to the data segment in order * to properly dereference it. The .text section comes first in an - * rmodule so ap_start can be used as a proxy for the load address. */ + * rmodule so _start can be used as a proxy for the load address. */ movl $(gdtaddr), %ebx - sub $(ap_start), %ebx + sub $(_start), %ebx data32 lgdt (%ebx) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 5fbec28..ead597c 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -59,10 +59,8 @@ fallback_stack_top: .text .code16 -.global smm_handler_start -.global __rmodule_entry -__rmodule_entry: -smm_handler_start: +.global _start +_start: movl $(smm_relocate_gdt), %ebx data32 lgdt (%ebx) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 02f67db..ef47f6b 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -47,9 +47,9 @@ #define ARCH_STAGE_HAS_BSS_SECTION 1 #endif -/* Default is that currently ramstage and smm only has a heap. */ +/* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) #endif #define STR(x) #x @@ -166,7 +166,7 @@ REGION(watchdog_tombstone, addr, size, 4) \ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); -#if ENV_RAMSTAGE || ENV_ROMSTAGE +#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ @@ -176,7 +176,7 @@ #define CBMEM_INIT_HOOKS #endif -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_RMODULE #define DRIVERS_RODATA \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(pci_drivers) \ @@ -206,7 +206,7 @@ #define DATA_EXTRA \ PROVIDE(_preram_cbmem_console = .); \ PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE +#elif ENV_RAMSTAGE || ENV_RMODULE #define DATA_EXTRA \ SYMBOL_CURRENT_LOC(bs_init_begin) \ KEEP(*(.bs_init)); \ @@ -217,8 +217,18 @@ #define DATA_EXTRA #endif +#if ENV_RMODULE +#define RMODULE_PARAMS \ + SYMBOL_CURRENT_LOC(rmodule_params) \ + KEEP(*(.module_parameters)); \ + SYMBOL_CURRENT_LOC(ermodule_params) +#else +#define RMODULE_PARAMS +#endif + #define DATA_SECTION \ BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + RMODULE_PARAMS \ *(.data); \ *(.data.*); \ DATA_EXTRA \ @@ -242,7 +252,7 @@ #if ARCH_STAGE_HAS_HEAP_SECTION #define HEAP_SECTION \ BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ - . += CONFIG_HEAP_SIZE ; \ + . += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); \ END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) #else #define HEAP_SECTION diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 719c6a6..03cdf76 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -73,9 +73,9 @@ struct rmodule { }; #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES) -/* Rmodules have an entry point of named __rmodule_entry. */ +/* Rmodules have an entry point of named _start. */ #define RMODULE_ENTRY(entry_) \ - void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_)))) + void _start(void *) __attribute__((alias (STRINGIFY(entry_)))) #else #define RMODULE_ENTRY(entry_) #endif diff --git a/src/include/rules.h b/src/include/rules.h index 2e7f88f..c9d3f59 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -30,6 +30,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__ROMSTAGE__) #define ENV_BOOTBLOCK 0 @@ -38,6 +39,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__SMM__) #define ENV_BOOTBLOCK 0 @@ -46,6 +48,7 @@ #define ENV_SMM 1 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__SECMON__) #define ENV_BOOTBLOCK 0 @@ -54,6 +57,7 @@ #define ENV_SMM 0 #define ENV_SECMON 1 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__VERSTAGE__) #define ENV_BOOTBLOCK 0 @@ -62,6 +66,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 1 +#define ENV_RMODULE 0 #elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 @@ -70,6 +75,16 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 + +#elif defined(__RMODULE__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 1 #else /* Default case of nothing set for random blob generation using @@ -80,6 +95,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #endif /* For romstage and ramstage always build with simple device model, ie. diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f5d5f06..340fe7a 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -12,103 +12,14 @@ * won't be a consistent mapping between the flat blob and the loaded program. */ -BASE_ADDRESS = 0x00000; - -ENTRY(__rmodule_entry); +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = BASE_ADDRESS; - - .payload : { - /* C code of the module. */ - _program = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - /* C read-only data. */ - . = ALIGN(16); - -#if IS_ENABLED(CONFIG_COVERAGE) - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - LONG(0); - __CTOR_END__ = .; -#endif - - /* The driver sections are to allow linking coreboot's - * ramstage with the rmodule linker. Any changes made in - * ramstage.ld should be made here as well. */ - . = ALIGN(8); - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - . = ALIGN(8); - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - . = ALIGN(8); - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - . = ALIGN(8); - - *(.rodata); - *(.rodata.*); - . = ALIGN(8); - - /* The parameters section can be used to pass parameters - * to a module, however there has to be an prior agreement - * on how to interpret the parameters. */ - _module_params_begin = .; - KEEP(*(.module_parameters)); - _module_params_end = .; - . = ALIGN(8); - - /* Data section. */ - . = ALIGN(64); /* Mirror cache line alignment from ramstage. */ - _sdata = .; - *(.data); - *(.data.*); - . = ALIGN(8); - _edata = .; - - . = ALIGN(8); - } - - .bss (NOLOAD) : { - /* C uninitialized data of the module. */ - _bss = .; - *(.bss); - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(COMMON); - . = ALIGN(8); - _ebss = .; - - /* - * Place the heap after BSS. The heap size is passed in by - * by way of ld --defsym=__heap_size=<> - */ - _heap = .; - . = . + __heap_size; - _eheap = .; - _eprogram = .; - } + SET_COUNTER(rmodule, 0x00000000) - /DISCARD/ : { - /* Drop unnecessary sections. */ - *(.eh_frame); - *(.note); - *(.note.*); - } + /* program.ld is directly included because there's no one particular + * class that rmodule is used on. */ + #include <lib/program.ld> } diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index f93f4f6..c35eff7 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx) break; } - if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin, + if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin, nsyms, strtab)) return -1; - if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end, + if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end, nsyms, strtab)) return -1; @@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx) if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) return -1; - if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab)) - return -1; + /* Honor the entry point within the ELF header. */ + ctx->entry = ehdr->e_entry; /* Link address is the virtual address of the program segment. */ ctx->link_addr = ctx->phdr->p_vaddr;

1 0

Patch set updated for coreboot: x86: link romstage and ramstage with 1 file
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521 -gerrit commit 6ee4e8627cac4c433acb0095490f012905454c9e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 13:31:14 2015 -0500 x86: link romstage and ramstage with 1 file To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 ++++---- src/arch/x86/car.ld | 50 +++++++++++++++++++++++++++++++++++++++ src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 7 ------ src/arch/x86/romstage.ld | 59 ----------------------------------------------- 5 files changed, 97 insertions(+), 71 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0b8058f..9e5110f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-y += romstage.ld +romstage-y += memlayout.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp @@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-y += ramstage.ld +ramstage-y += memlayout.ld -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld endif diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld new file mode 100644 index 0000000..1724a73 --- /dev/null +++ b/src/arch/x86/car.ld @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + SYMBOL_CURRENT_LOC(car_data_start) +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + TIMESTAMP(., 0x100) +#endif + *(.car.global_data); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) + } + + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + + . = 0xffffff00; + .illegal_globals . : { + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + + _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld new file mode 100644 index 0000000..43c5229 --- /dev/null +++ b/src/arch/x86/memlayout.ld @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + /* + * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively + * like other architectures/chipsets it's not possible because of + * the linking games played during romstage creation by trying + * to find the final landing place in CBFS for XIP. Therefore, + * conditionalize with macros. + */ +#if ENV_RAMSTAGE + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + +#elif ENV_ROMSTAGE + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) + + /* Pull in the cache-as-ram rules. */ + #include "car.ld" +#endif +} diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld deleted file mode 100644 index 0d329db..0000000 --- a/src/arch/x86/ramstage.ld +++ /dev/null @@ -1,7 +0,0 @@ -#include <memlayout.h> -#include <arch/header.ld> - -SECTIONS -{ - RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) -} diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld deleted file mode 100644 index 9c44b13..0000000 --- a/src/arch/x86/romstage.ld +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <memlayout.h> -#include <arch/header.ld> - -SECTIONS -{ - /* The 1M size is not allocated. It's just for basic size checking. */ - ROMSTAGE(ROMSTAGE_BASE, 1M) - - . = CONFIG_DCACHE_RAM_BASE; - .car.data . (NOLOAD) : { - SYMBOL_CURRENT_LOC(car_data_start) -#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - TIMESTAMP(., 0x100) -#endif - *(.car.global_data); - POINTER_ALIGN - SYMBOL_CURRENT_LOC(car_data_end) - - PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) - } - - /* Global variables are not allowed in romstage - * This section is checked during stage creation to ensure - * that there are no global variables present - */ - - . = 0xffffff00; - .illegal_globals . : { - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - } - - _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -}

1 0

Patch set updated for coreboot: verstage: use common program.ld for linking
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516 -gerrit commit d54cd08002f2d831e29519b3c827aa17ae3976d5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 10:27:12 2015 -0500 verstage: use common program.ld for linking There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 27 ++++++++++ src/lib/Makefile.inc | 1 + src/soc/broadcom/cygnus/include/soc/memlayout.ld | 1 - src/soc/imgtec/pistachio/include/soc/memlayout.ld | 1 - src/soc/marvell/bg4cd/include/soc/memlayout.ld | 1 - src/soc/nvidia/tegra124/include/soc/memlayout.ld | 1 - .../tegra132/include/soc/memlayout_vboot2.ld | 1 - .../tegra210/include/soc/memlayout_vboot2.ld | 1 - src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 - .../samsung/exynos5250/include/soc/memlayout.ld | 1 - src/vendorcode/google/chromeos/memlayout.h | 54 -------------------- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 2 - src/vendorcode/google/chromeos/vboot2/verstage.ld | 58 ---------------------- 14 files changed, 28 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1a38256..02f67db 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -139,6 +139,33 @@ . += sz; #endif +/* Careful: required work buffer size depends on RW properties such as key size + * and algorithm -- what works for you might stop working after an update. Do + * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ +#define VBOOT2_WORK(addr, size) \ + REGION(vboot2_work, addr, size, 16) \ + _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); + +#if ENV_VERSTAGE + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + _ = ASSERT(_eprogram - _program <= sz, \ + STR(Verstage exceeded its allotted size! (sz))); \ + INCLUDE "lib/program.verstage.ld" + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) +#else + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + . += sz; + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) +#endif + +#define WATCHDOG_TOMBSTONE(addr, size) \ + REGION(watchdog_tombstone, addr, size, 4) \ + _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); + #if ENV_RAMSTAGE || ENV_ROMSTAGE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 464d631..d8cd1d8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -199,6 +199,7 @@ endif romstage-y += program.ld ramstage-y += program.ld +verstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 5e149b4..237ffc6 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 366b20a..59e3017 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld index 15c09d9..45835e2 100644 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 2312cc9..561833d 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 0f98fd2..a8164a9 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index c140e01..dee6798 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index cf417ba..ad0977a 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -19,7 +19,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 0b75932..b96923e 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 3b5b034..4469078 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h deleted file mode 100644 index 29434bd..0000000 --- a/src/vendorcode/google/chromeos/memlayout.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file contains macro definitions for memlayout.ld linker scripts. */ - -#ifndef __CHROMEOS_MEMLAYOUT_H -#define __CHROMEOS_MEMLAYOUT_H - -/* Careful: required work buffer size depends on RW properties such as key size - * and algorithm -- what works for you might stop working after an update. Do - * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ -#define VBOOT2_WORK(addr, size) \ - REGION(vboot2_work, addr, size, 16) \ - _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); - -#ifdef __VERSTAGE__ - #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ - _ = ASSERT(_everstage - _verstage <= sz, \ - STR(Verstage exceeded its allotted size! (sz))); \ - INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld" -#else - #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ - . += sz; -#endif - -#ifdef __VERSTAGE__ - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) -#else - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) -#endif - -#define WATCHDOG_TOMBSTONE(addr, size) \ - REGION(watchdog_tombstone, addr, size, 4) \ - _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); - -#endif /* __CHROMEOS_MEMLAYOUT_H */ diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index b805993..21613ba 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c ramstage-y += common.c -verstage-y += verstage.ld - ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) else diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld deleted file mode 100644 index fcb8af8..0000000 --- a/src/vendorcode/google/chromeos/vboot2/verstage.ld +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _verstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _everstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

1 0

Patch set updated for coreboot: linking: lay the groundwork for a unified linking approach
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507 -gerrit commit d478c79c2f34c6b0efe68f8231b04f6ee45fef44 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 22:49:36 2015 -0500 linking: lay the groundwork for a unified linking approach Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/memlayout.h | 25 +++++++ src/arch/x86/ramstage.ld | 2 +- src/include/memlayout.h | 126 ++++++++++++++++++++++++++++++++-- src/lib/Makefile.inc | 3 +- src/lib/program.ld | 66 ++++++++++++++++++ src/lib/ramstage.ld | 115 ------------------------------- 7 files changed, 217 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fe974ef..9d3f07f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-srcs += $(src)/arch/x86/ramstage.ld +ramstage-y += ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h new file mode 100644 index 0000000..54b8b4a --- /dev/null +++ b/src/arch/x86/include/arch/memlayout.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* Currently empty to satisfy common arch requirements. */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 5fcbbb6..c9b2f17 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -19,7 +19,7 @@ SECTIONS { . = CONFIG_RAMBASE; - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..3b3ff6d 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -22,10 +22,41 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H +#include <rules.h> #include <arch/memlayout.h> +/* Macros that the architecture can override. */ +#ifndef ARCH_POINTER_ALIGN_SIZE +#define ARCH_POINTER_ALIGN_SIZE 8 +#endif + +#ifndef ARCH_CACHELINE_ALIGN_SIZE +#define ARCH_CACHELINE_ALIGN_SIZE 64 +#endif + +#ifndef ARCH_FIRST_TEXT +#define ARCH_FIRST_TEXT +#endif + +/* Default to data as well as bss. */ +#ifndef ARCH_STAGE_HAS_DATA_SECTION +#define ARCH_STAGE_HAS_DATA_SECTION 1 +#endif + +#ifndef ARCH_STAGE_HAS_BSS_SECTION +#define ARCH_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Default is that currently ramstage and smm only has a heap. */ +#ifndef ARCH_STAGE_HAS_HEAP_SECTION +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#endif + #define STR(x) #x +#define ALIGN_COUNTER(align) \ + . = ALIGN(align); + #define SET_COUNTER(name, addr) \ _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ . = addr; @@ -34,6 +65,9 @@ SET_COUNTER(name, addr) \ _##name = .; +#define SYMBOL_CURRENT_LOC(name) \ + _##name = .; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ @@ -58,7 +92,7 @@ /* TODO: This only works if you never access CBFS in romstage before RAM is up! * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__) +#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) @@ -93,16 +127,100 @@ . += sz; #endif -#ifdef __RAMSTAGE__ +#if ENV_RAMSTAGE #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ - _ = ASSERT(_eramstage - _ramstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ . += sz; #endif +#if ENV_RAMSTAGE || ENV_ROMSTAGE +#define CBMEM_INIT_HOOKS \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ + KEEP(*(.rodata.cbmem_init_hooks)); \ + SYMBOL_CURRENT_LOC(ecbmem_init_hooks) +#else +#define CBMEM_INIT_HOOKS +#endif + +#if ENV_RAMSTAGE +#define DRIVERS_RODATA \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(pci_drivers) \ + KEEP(*(.rodata.pci_driver)); \ + SYMBOL_CURRENT_LOC(epci_drivers) \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cpu_drivers) \ + KEEP(*(.rodata.cpu_driver)); \ + SYMBOL_CURRENT_LOC(ecpu_drivers) +#else +#define DRIVERS_RODATA +#endif + +#define BEGIN_SECTION(name, align) \ + .##name : { \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(name) + +#define END_SECTION(name, align) \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(e##name) \ + } + +#if ARCH_STAGE_HAS_DATA_SECTION +#ifdef __PRE_RAM__ +/* Provide these symbols in PRE_RAM environments if not already provided. */ +#define DATA_EXTRA \ + PROVIDE(_preram_cbmem_console = .); \ + PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); +#elif ENV_RAMSTAGE +#define DATA_EXTRA \ + SYMBOL_CURRENT_LOC(bs_init_begin) \ + KEEP(*(.bs_init)); \ + LONG(0); \ + LONG(0); \ + SYMBOL_CURRENT_LOC(ebs_init_begin) +#else +#define DATA_EXTRA +#endif + +#define DATA_SECTION \ + BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + *(.data); \ + *(.data.*); \ + DATA_EXTRA \ + END_SECTION(data, ARCH_POINTER_ALIGN_SIZE) +#else +#define DATA_SECTION +#endif + +#if ARCH_STAGE_HAS_BSS_SECTION +#define BSS_SECTION \ + BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \ + *(.bss) \ + *(.bss.*) \ + *(.sbss) \ + *(.sbss.*) \ + END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) +#else +#define BSS_SECTION +#endif + +#if ARCH_STAGE_HAS_HEAP_SECTION +#define HEAP_SECTION \ + BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ + . += CONFIG_HEAP_SIZE ; \ + END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) +#else +#define HEAP_SECTION +#endif + +#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + #endif /* __MEMLAYOUT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8597667..cd2b70a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += bootblock.ld romstage-y += romstage.ld endif -ramstage-y += ramstage.ld + +ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/lib/program.ld b/src/lib/program.ld new file mode 100644 index 0000000..f4850d3 --- /dev/null +++ b/src/lib/program.ld @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +BEGIN_SECTION(text, 1) + SYMBOL_CURRENT_LOC(program) + ARCH_FIRST_TEXT + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + POINTER_ALIGN + CBMEM_INIT_HOOKS + DRIVERS_RODATA + *(.rodata); + *(.rodata.*); + POINTER_ALIGN +END_SECTION(text, 1) : to_load + +#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +BEGIN_SECTION(ctors, 0x100) + SYMBOL_CURRENT_LOC(__CTOR_LIST__) + KEEP(*(.ctors)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(__CTOR_END__) +END_SECTION(ctors, 1) +#endif + +/* Include data, bss, and heap in that order. Not defined for all stages. */ +DATA_SECTION +BSS_SECTION +HEAP_SECTION +SYMBOL_CURRENT_LOC(eprogram) + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.comment.*) + *(.note) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld deleted file mode 100644 index b224827..0000000 --- a/src/lib/ramstage.ld +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -/* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ -.text : { - _program = .; - _ramstage = .; - _text = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; -} : to_load - -#if IS_ENABLED(CONFIG_COVERAGE) -.ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; -} -#endif - -/* TODO: align data sections to cache lines? (is that really useful?) */ -.rodata : { - _rodata = .; - . = ALIGN(8); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(8); - - _erodata = .; -} - -.data : { - /* Move to different cache line to avoid false sharing with .rodata. */ - . = ALIGN(64); /* May not be actual line size, not that important. */ - _data = .; - *(.data) - *(.data.*) - _edata = .; -} - -.bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; -} - -.heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - _eramstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ - -/DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) -}

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coreboot-gerrit September 2015