coreboot-gerrit September 2015

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Patch set updated for coreboot: linking: add and use LDFLAGS_common
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522 -gerrit commit b25427ae023acf0e6a332347dffdabcec07099b3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:15:17 2015 -0500 linking: add and use LDFLAGS_common Add an LDFLAGS_common variable and use that for each stage during linking within all the architectures. All the architectures support gc-sections, and as such they should be linking in the same way. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage. Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/arm/Makefile.inc | 8 ++++---- src/arch/arm64/Makefile.inc | 8 ++++---- src/arch/mips/Makefile.inc | 6 +++--- src/arch/riscv/Makefile.inc | 6 +++--- src/arch/x86/Makefile.inc | 6 +++--- src/cpu/x86/smm/Makefile.inc | 2 +- src/lib/Makefile.inc | 4 ++-- toolchain.inc | 6 ++++++ 8 files changed, 26 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 7a4409e..82ce8b3 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -63,7 +63,7 @@ bootblock-y += clock.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group verstage-y += boot.c verstage-y += div0.c @@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index a625c7a..e1c84a9 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -73,7 +73,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-y += boot.c verstage-y += div0.c @@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index e3aff0c..fab8a05 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_MIPS @@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_MIPS @@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0f3eb0f..5233faa 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -40,7 +40,7 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \ + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) @@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9e5110f..b018f7c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -180,7 +180,7 @@ endif $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \ grep -v "Empty loadable segment detected" && \ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ @@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -292,7 +292,7 @@ ramstage-y += memlayout.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld endif diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 239689e..7b4ad59 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod else # CONFIG_SMM_TSEG $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d8cd1d8..a89f7d4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c -RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic +RMODULE_LDFLAGS := -z defs -Bsymbolic # rmodule_link_rules is a function that should be called with: # (1) the object name to link @@ -216,7 +216,7 @@ RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map $(strip $(1)).rmod: $(strip $(1)) diff --git a/toolchain.inc b/toolchain.inc index 195ed77..d143dd7 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -69,6 +69,11 @@ CFLAGS_riscv += CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone +# Set the LDFLAGS for each arch. +LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +$(foreach arch,$(ARCH_SUPPORTED), \ + $(eval LDFLAGS_$(arch):=$(LDFLAGS_common))) + # Some boards only provide 2K stacks, so storing lots of data there leads to # problems. Since C rules don't allow us to statically determine the maximum # stack use, we use 1.5K as heuristic, assuming that we typically have lots @@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2)) CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) COMPILER_RT_$(1) := $$(COMPILER_RT_$(2)) COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2)) +LDFLAGS_$(1) = $$(LDFLAGS_$(2)) endef # define_class: Allows defining any program as dynamic class and compiler tool

1 0

Patch set updated for coreboot: x86: link romstage and ramstage with 1 file
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521 -gerrit commit 961deb18c506a4952ce64ddbe17fd7fd48f41168 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 13:31:14 2015 -0500 x86: link romstage and ramstage with 1 file To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 ++++---- src/arch/x86/car.ld | 50 +++++++++++++++++++++++++++++++++++++++ src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 7 ------ src/arch/x86/romstage.ld | 59 ----------------------------------------------- 5 files changed, 97 insertions(+), 71 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0b8058f..9e5110f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-y += romstage.ld +romstage-y += memlayout.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp @@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-y += ramstage.ld +ramstage-y += memlayout.ld -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld endif diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld new file mode 100644 index 0000000..6793ca1 --- /dev/null +++ b/src/arch/x86/car.ld @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + SYMBOL_CURRENT_LOC(car_data_start) +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + TIMESTAMP(., 0x100) +#endif + *(.car.global_data); + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) + } + + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + + . = 0xffffff00; + .illegal_globals . : { + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + + _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld new file mode 100644 index 0000000..43c5229 --- /dev/null +++ b/src/arch/x86/memlayout.ld @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + /* + * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively + * like other architectures/chipsets it's not possible because of + * the linking games played during romstage creation by trying + * to find the final landing place in CBFS for XIP. Therefore, + * conditionalize with macros. + */ +#if ENV_RAMSTAGE + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + +#elif ENV_ROMSTAGE + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) + + /* Pull in the cache-as-ram rules. */ + #include "car.ld" +#endif +} diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld deleted file mode 100644 index 0d329db..0000000 --- a/src/arch/x86/ramstage.ld +++ /dev/null @@ -1,7 +0,0 @@ -#include <memlayout.h> -#include <arch/header.ld> - -SECTIONS -{ - RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) -} diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld deleted file mode 100644 index 4bb7250..0000000 --- a/src/arch/x86/romstage.ld +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <memlayout.h> -#include <arch/header.ld> - -SECTIONS -{ - /* The 1M size is not allocated. It's just for basic size checking. */ - ROMSTAGE(ROMSTAGE_BASE, 1M) - - . = CONFIG_DCACHE_RAM_BASE; - .car.data . (NOLOAD) : { - SYMBOL_CURRENT_LOC(car_data_start) -#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - TIMESTAMP(., 0x100) -#endif - *(.car.global_data); - ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) - SYMBOL_CURRENT_LOC(car_data_end) - - PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) - } - - /* Global variables are not allowed in romstage - * This section is checked during stage creation to ensure - * that there are no global variables present - */ - - . = 0xffffff00; - .illegal_globals . : { - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - } - - _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -}

1 0

Patch set updated for coreboot: rmodule: use program.ld for linking
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517 -gerrit commit 6708549d6f5f9a1a3aee6b5bd26fa1299d7ae272 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 12:59:26 2015 -0500 rmodule: use program.ld for linking Bring rmodule linking into the common linking method. The __rmodule_entry symbol was removed while using a more common _start symbol. The rmodtool will honor the entry point found within the ELF header. Add ENV_RMODULE so that one can distinguish the environment when generating linker scripts for rmodules. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- Makefile.inc | 3 + src/arch/arm64/include/arch/header.ld | 10 +++- src/arch/arm64/stage_entry.S | 4 +- src/arch/x86/c_start.S | 2 - src/arch/x86/include/arch/header.ld | 2 +- src/cpu/x86/Makefile.inc | 4 +- src/cpu/x86/sipi_vector.S | 10 ++-- src/cpu/x86/smm/smm_stub.S | 6 +- src/include/memlayout.h | 4 +- src/include/rmodule.h | 4 +- src/include/rules.h | 16 ++++++ src/lib/program.ld | 15 +++-- src/lib/rmodule.ld | 101 ++-------------------------------- util/cbfstool/rmodule.c | 8 +-- 14 files changed, 64 insertions(+), 125 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..b5d8309 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) +# Provide a macro to determine environment for free standing rmodules. +$(foreach supported_arch,$(ARCH_SUPPORTED), \ + $(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__)) ####################################################################### # Helper functions for math and various file placement matters. diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index fa8fdfa..b3112e3 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -17,6 +17,8 @@ * Foundation, Inc. */ +#include <rules.h> + /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) @@ -26,7 +28,13 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBTLOCK TARGET(binary) #endif + +/* secmon uses rmodules */ +#if ENV_RMODULE +ENTRY(_start) +#else ENTRY(stage_entry) +#endif diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 4e15dbb..dbc6cad 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment) 2002: .endm -ENTRY(__rmodule_entry) +ENTRY(_start) split_bsp_path /* Save the arguments to secmon in x25 */ mov x25, x0 b arm64_c_environment -ENDPROC(__rmodule_entry) +ENDPROC(_start) /* * Setup SCTLR so that: diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 582966b..ad4589a 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -23,8 +23,6 @@ thread_stacks: .code32 #endif .globl _start - .globl __rmodule_entry -__rmodule_entry: _start: cli lgdt %cs:gdtaddr diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 55547ad..0262c92 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -24,7 +24,7 @@ PHDRS to_load PT_LOAD; } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_RMODULE ENTRY(_start) #elif ENV_ROMSTAGE ENTRY(protected_start) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9ec0768..e9394b2 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) else -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) endif $(SIPI_BIN): $(SIPI_RMOD) diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index c7b1097..0887b0a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -56,10 +56,8 @@ ap_count: .text .code16 -.global ap_start -.global __rmodule_entry -__rmodule_entry: -ap_start: +.global _start +_start: cli xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ @@ -74,9 +72,9 @@ ap_start: /* The gdtaddr needs to be releative to the data segment in order * to properly dereference it. The .text section comes first in an - * rmodule so ap_start can be used as a proxy for the load address. */ + * rmodule so _start can be used as a proxy for the load address. */ movl $(gdtaddr), %ebx - sub $(ap_start), %ebx + sub $(_start), %ebx data32 lgdt (%ebx) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 5fbec28..ead597c 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -59,10 +59,8 @@ fallback_stack_top: .text .code16 -.global smm_handler_start -.global __rmodule_entry -__rmodule_entry: -smm_handler_start: +.global _start +_start: movl $(smm_relocate_gdt), %ebx data32 lgdt (%ebx) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index d4be3f8..a25e018 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -47,9 +47,9 @@ #define ARCH_STAGE_HAS_BSS_SECTION 1 #endif -/* Default is that currently ramstage and smm only has a heap. */ +/* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) #endif #define STR(x) #x diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 719c6a6..03cdf76 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -73,9 +73,9 @@ struct rmodule { }; #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES) -/* Rmodules have an entry point of named __rmodule_entry. */ +/* Rmodules have an entry point of named _start. */ #define RMODULE_ENTRY(entry_) \ - void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_)))) + void _start(void *) __attribute__((alias (STRINGIFY(entry_)))) #else #define RMODULE_ENTRY(entry_) #endif diff --git a/src/include/rules.h b/src/include/rules.h index d147d3c..1563f2d 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -30,6 +30,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__ROMSTAGE__) #define ENV_BOOTBLOCK 0 @@ -38,6 +39,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__SMM__) #define ENV_BOOTBLOCK 0 @@ -46,6 +48,7 @@ #define ENV_SMM 1 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__SECMON__) #define ENV_BOOTBLOCK 0 @@ -54,6 +57,7 @@ #define ENV_SMM 0 #define ENV_SECMON 1 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__VERSTAGE__) #define ENV_BOOTBLOCK 0 @@ -62,6 +66,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 1 +#define ENV_RMODULE 0 #elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 @@ -70,6 +75,16 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 + +#elif defined(__RMODULE__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 1 #else /* @@ -84,6 +99,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #endif /* For romstage and ramstage always build with simple device model, ie. diff --git a/src/lib/program.ld b/src/lib/program.ld index 02d017a..43b1fea 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -33,14 +33,14 @@ *(.text); *(.text.*); -#if ENV_RAMSTAGE || ENV_ROMSTAGE +#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(cbmem_init_hooks) KEEP(*(.rodata.cbmem_init_hooks)); SYMBOL_CURRENT_LOC(ecbmem_init_hooks) #endif -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_RMODULE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(pci_drivers) KEEP(*(.rodata.pci_driver)); @@ -74,13 +74,20 @@ .data : { ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE) SYMBOL_CURRENT_LOC(data) + +#if ENV_RMODULE + SYMBOL_CURRENT_LOC(rmodule_params) + KEEP(*(.module_parameters)); + SYMBOL_CURRENT_LOC(ermodule_params) +#endif + *(.data); *(.data.*); #ifdef __PRE_RAM__ PROVIDE(_preram_cbmem_console = .); PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE +#elif ENV_RAMSTAGE || ENV_RMODULE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(bs_init_begin) KEEP(*(.bs_init)); @@ -111,7 +118,7 @@ .heap : { ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(heap) - . += CONFIG_HEAP_SIZE; + . += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(eheap) } diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f5d5f06..340fe7a 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -12,103 +12,14 @@ * won't be a consistent mapping between the flat blob and the loaded program. */ -BASE_ADDRESS = 0x00000; - -ENTRY(__rmodule_entry); +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = BASE_ADDRESS; - - .payload : { - /* C code of the module. */ - _program = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - /* C read-only data. */ - . = ALIGN(16); - -#if IS_ENABLED(CONFIG_COVERAGE) - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - LONG(0); - __CTOR_END__ = .; -#endif - - /* The driver sections are to allow linking coreboot's - * ramstage with the rmodule linker. Any changes made in - * ramstage.ld should be made here as well. */ - . = ALIGN(8); - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - . = ALIGN(8); - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - . = ALIGN(8); - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - . = ALIGN(8); - - *(.rodata); - *(.rodata.*); - . = ALIGN(8); - - /* The parameters section can be used to pass parameters - * to a module, however there has to be an prior agreement - * on how to interpret the parameters. */ - _module_params_begin = .; - KEEP(*(.module_parameters)); - _module_params_end = .; - . = ALIGN(8); - - /* Data section. */ - . = ALIGN(64); /* Mirror cache line alignment from ramstage. */ - _sdata = .; - *(.data); - *(.data.*); - . = ALIGN(8); - _edata = .; - - . = ALIGN(8); - } - - .bss (NOLOAD) : { - /* C uninitialized data of the module. */ - _bss = .; - *(.bss); - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(COMMON); - . = ALIGN(8); - _ebss = .; - - /* - * Place the heap after BSS. The heap size is passed in by - * by way of ld --defsym=__heap_size=<> - */ - _heap = .; - . = . + __heap_size; - _eheap = .; - _eprogram = .; - } + SET_COUNTER(rmodule, 0x00000000) - /DISCARD/ : { - /* Drop unnecessary sections. */ - *(.eh_frame); - *(.note); - *(.note.*); - } + /* program.ld is directly included because there's no one particular + * class that rmodule is used on. */ + #include <lib/program.ld> } diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index f93f4f6..c35eff7 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx) break; } - if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin, + if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin, nsyms, strtab)) return -1; - if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end, + if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end, nsyms, strtab)) return -1; @@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx) if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) return -1; - if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab)) - return -1; + /* Honor the entry point within the ELF header. */ + ctx->entry = ehdr->e_entry; /* Link address is the virtual address of the program segment. */ ctx->link_addr = ctx->phdr->p_vaddr;

1 0

Patch set updated for coreboot: verstage: use common program.ld for linking
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516 -gerrit commit 95548a50de28612c651adf2bba9aeb9ab3d656d5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 10:27:12 2015 -0500 verstage: use common program.ld for linking There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 27 ++++++++++ src/lib/Makefile.inc | 1 + src/soc/broadcom/cygnus/include/soc/memlayout.ld | 1 - src/soc/imgtec/pistachio/include/soc/memlayout.ld | 1 - src/soc/marvell/bg4cd/include/soc/memlayout.ld | 1 - src/soc/nvidia/tegra124/include/soc/memlayout.ld | 1 - .../tegra132/include/soc/memlayout_vboot2.ld | 1 - .../tegra210/include/soc/memlayout_vboot2.ld | 1 - src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 - .../samsung/exynos5250/include/soc/memlayout.ld | 1 - src/vendorcode/google/chromeos/memlayout.h | 54 -------------------- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 2 - src/vendorcode/google/chromeos/vboot2/verstage.ld | 58 ---------------------- 14 files changed, 28 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 5f9c3c1..d4be3f8 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -139,4 +139,31 @@ . += sz; #endif +/* Careful: required work buffer size depends on RW properties such as key size + * and algorithm -- what works for you might stop working after an update. Do + * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ +#define VBOOT2_WORK(addr, size) \ + REGION(vboot2_work, addr, size, 16) \ + _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); + +#if ENV_VERSTAGE + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + _ = ASSERT(_eprogram - _program <= sz, \ + STR(Verstage exceeded its allotted size! (sz))); \ + INCLUDE "lib/program.verstage.ld" + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) +#else + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + . += sz; + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) +#endif + +#define WATCHDOG_TOMBSTONE(addr, size) \ + REGION(watchdog_tombstone, addr, size, 4) \ + _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); + #endif /* __MEMLAYOUT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 464d631..d8cd1d8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -199,6 +199,7 @@ endif romstage-y += program.ld ramstage-y += program.ld +verstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 5e149b4..237ffc6 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 366b20a..59e3017 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld index 15c09d9..45835e2 100644 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 2312cc9..561833d 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 0f98fd2..a8164a9 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index c140e01..dee6798 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index cf417ba..ad0977a 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -19,7 +19,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 0b75932..b96923e 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 3b5b034..4469078 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h deleted file mode 100644 index 29434bd..0000000 --- a/src/vendorcode/google/chromeos/memlayout.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file contains macro definitions for memlayout.ld linker scripts. */ - -#ifndef __CHROMEOS_MEMLAYOUT_H -#define __CHROMEOS_MEMLAYOUT_H - -/* Careful: required work buffer size depends on RW properties such as key size - * and algorithm -- what works for you might stop working after an update. Do - * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ -#define VBOOT2_WORK(addr, size) \ - REGION(vboot2_work, addr, size, 16) \ - _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); - -#ifdef __VERSTAGE__ - #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ - _ = ASSERT(_everstage - _verstage <= sz, \ - STR(Verstage exceeded its allotted size! (sz))); \ - INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld" -#else - #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ - . += sz; -#endif - -#ifdef __VERSTAGE__ - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) -#else - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) -#endif - -#define WATCHDOG_TOMBSTONE(addr, size) \ - REGION(watchdog_tombstone, addr, size, 4) \ - _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); - -#endif /* __CHROMEOS_MEMLAYOUT_H */ diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index b805993..21613ba 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c ramstage-y += common.c -verstage-y += verstage.ld - ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) else diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld deleted file mode 100644 index fcb8af8..0000000 --- a/src/vendorcode/google/chromeos/vboot2/verstage.ld +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _verstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _everstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

1 0

Patch set updated for coreboot: linking: lay the groundwork for a unified linking approach
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507 -gerrit commit 6a2304404ac9d2b948d6a24ee23327de7ba6f989 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 22:49:36 2015 -0500 linking: lay the groundwork for a unified linking approach Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/memlayout.h | 25 +++++++ src/arch/x86/ramstage.ld | 2 +- src/include/memlayout.h | 42 +++++++++-- src/lib/Makefile.inc | 3 +- src/lib/program.ld | 130 ++++++++++++++++++++++++++++++++++ src/lib/ramstage.ld | 115 ------------------------------ 7 files changed, 197 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fe974ef..9d3f07f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-srcs += $(src)/arch/x86/ramstage.ld +ramstage-y += ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h new file mode 100644 index 0000000..54b8b4a --- /dev/null +++ b/src/arch/x86/include/arch/memlayout.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* Currently empty to satisfy common arch requirements. */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 5fcbbb6..c9b2f17 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -19,7 +19,7 @@ SECTIONS { . = CONFIG_RAMBASE; - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..3963339 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -22,10 +22,41 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H +#include <rules.h> #include <arch/memlayout.h> +/* Macros that the architecture can override. */ +#ifndef ARCH_POINTER_ALIGN_SIZE +#define ARCH_POINTER_ALIGN_SIZE 8 +#endif + +#ifndef ARCH_CACHELINE_ALIGN_SIZE +#define ARCH_CACHELINE_ALIGN_SIZE 64 +#endif + +#ifndef ARCH_FIRST_TEXT +#define ARCH_FIRST_TEXT +#endif + +/* Default to data as well as bss. */ +#ifndef ARCH_STAGE_HAS_DATA_SECTION +#define ARCH_STAGE_HAS_DATA_SECTION 1 +#endif + +#ifndef ARCH_STAGE_HAS_BSS_SECTION +#define ARCH_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Default is that currently ramstage and smm only has a heap. */ +#ifndef ARCH_STAGE_HAS_HEAP_SECTION +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#endif + #define STR(x) #x +#define ALIGN_COUNTER(align) \ + . = ALIGN(align); + #define SET_COUNTER(name, addr) \ _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ . = addr; @@ -34,6 +65,9 @@ SET_COUNTER(name, addr) \ _##name = .; +#define SYMBOL_CURRENT_LOC(name) \ + _##name = .; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ @@ -58,7 +92,7 @@ /* TODO: This only works if you never access CBFS in romstage before RAM is up! * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__) +#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) @@ -93,12 +127,12 @@ . += sz; #endif -#ifdef __RAMSTAGE__ +#if ENV_RAMSTAGE #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ - _ = ASSERT(_eramstage - _ramstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8597667..cd2b70a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += bootblock.ld romstage-y += romstage.ld endif -ramstage-y += ramstage.ld + +ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/lib/program.ld b/src/lib/program.ld new file mode 100644 index 0000000..02d017a --- /dev/null +++ b/src/lib/program.ld @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +.text : { + SYMBOL_CURRENT_LOC(program) + SYMBOL_CURRENT_LOC(text) + ARCH_FIRST_TEXT + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + +#if ENV_RAMSTAGE || ENV_ROMSTAGE + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(cbmem_init_hooks) + KEEP(*(.rodata.cbmem_init_hooks)); + SYMBOL_CURRENT_LOC(ecbmem_init_hooks) +#endif + +#if ENV_RAMSTAGE + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(pci_drivers) + KEEP(*(.rodata.pci_driver)); + SYMBOL_CURRENT_LOC(epci_drivers) + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(cpu_drivers) + KEEP(*(.rodata.cpu_driver)); + SYMBOL_CURRENT_LOC(ecpu_drivers) +#endif + + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + *(.rodata); + *(.rodata.*); + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(etext) +} : to_load + +#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +.ctors : { + ALIGN_COUNTER(0x100) + SYMBOL_CURRENT_LOC(__CTOR_LIST__) + KEEP(*(.ctors)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(__CTOR_END__) +} +#endif + +/* Include data, bss, and heap in that order. Not defined for all stages. */ +#if ARCH_STAGE_HAS_DATA_SECTION +.data : { + ALIGN_COUNTER(ARCH_CACHELINE_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(data) + *(.data); + *(.data.*); + +#ifdef __PRE_RAM__ + PROVIDE(_preram_cbmem_console = .); + PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); +#elif ENV_RAMSTAGE + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(bs_init_begin) + KEEP(*(.bs_init)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(ebs_init_begin) +#endif + + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(edata) +} +#endif + +#if ARCH_STAGE_HAS_BSS_SECTION +.bss : { + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(bss) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(ebss) +} +#endif + +#if ARCH_STAGE_HAS_HEAP_SECTION +.heap : { + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(heap) + . += CONFIG_HEAP_SIZE; + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(eheap) +} +#endif + +SYMBOL_CURRENT_LOC(eprogram) + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.comment.*) + *(.note) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld deleted file mode 100644 index b224827..0000000 --- a/src/lib/ramstage.ld +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -/* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ -.text : { - _program = .; - _ramstage = .; - _text = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; -} : to_load - -#if IS_ENABLED(CONFIG_COVERAGE) -.ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; -} -#endif - -/* TODO: align data sections to cache lines? (is that really useful?) */ -.rodata : { - _rodata = .; - . = ALIGN(8); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(8); - - _erodata = .; -} - -.data : { - /* Move to different cache line to avoid false sharing with .rodata. */ - . = ALIGN(64); /* May not be actual line size, not that important. */ - _data = .; - *(.data) - *(.data.*) - _edata = .; -} - -.bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; -} - -.heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - _eramstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ - -/DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) -}

1 0

Patch set updated for coreboot: x86: link romstage like the other architectures
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510 -gerrit commit 03a7b6ddd969085c34b7b03a55ac8e353ed6cc37 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:06:05 2015 -0500 x86: link romstage like the other architectures All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9d3f07f..0b8058f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */ +#include <rules.h> + PHDRS { to_load PT_LOAD; } +#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..4bb7250 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif +romstage-y += program.ld ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y)

1 0

Patch set updated for coreboot: linking: move romstage and bootblock to use program.ld
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509 -gerrit commit bacf9bc031ed25f4c947fddb31d2c0adbdaba879 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:09:49 2015 -0500 linking: move romstage and bootblock to use program.ld Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 12 +++++----- src/lib/Makefile.inc | 4 ++-- src/lib/bootblock.ld | 51 --------------------------------------- src/lib/romstage.ld | 64 ------------------------------------------------- 4 files changed, 8 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 3963339..5f9c3c1 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -103,24 +103,24 @@ #endif /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */ -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ - _ = ASSERT(_ebootblock - _bootblock <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ - INCLUDE "lib/bootblock.bootblock.ld" + INCLUDE "lib/program.bootblock.ld" #else #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ . += sz; #endif -#ifdef __ROMSTAGE__ +#if ENV_ROMSTAGE #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ - _ = ASSERT(_eromstage - _romstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/romstage.romstage.ld" + INCLUDE "lib/program.romstage.ld" #else #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index cd2b70a..4aa6bf8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -194,8 +194,8 @@ secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock and romstage use custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well -bootblock-y += bootblock.ld -romstage-y += romstage.ld +bootblock-y += program.ld +romstage-y += program.ld endif ramstage-y += program.ld diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld deleted file mode 100644 index 42e6d64..0000000 --- a/src/lib/bootblock.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.bootblock . : { - _program = .; - _bootblock = .; - *(.text._start); - *(.text.stage_entry); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; - _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; - _ebootblock = .; - _eprogram = .; -} : to_load = 0xff - -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - *(.MIPS.*) -} diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld deleted file mode 100644 index ba154ef..0000000 --- a/src/lib/romstage.ld +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _romstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - . = ALIGN(8); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - PROVIDE(_preram_cbmem_console = .); - PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _eromstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

1 0

Patch set updated for coreboot: x86: link ramstage like the other architectures
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508 -gerrit commit 2d690cac9075ef091e07c9058cc7765f53ca7625 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 10:19:05 2015 -0500 x86: link ramstage like the other architectures All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 24 +++--------------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld new file mode 100644 index 0000000..dd6cb27 --- /dev/null +++ b/src/arch/x86/include/arch/header.ld @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(_start) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index c9b2f17..0d329db 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -1,25 +1,7 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -ENTRY(_start) - -PHDRS -{ - to_load PT_LOAD; -} +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = CONFIG_RAMBASE; - - INCLUDE "lib/program.ramstage.ld" - - _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) }

1 0

Patch set updated for coreboot: rules.h: add fall through where no ENV_<STAGE> is set
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513 -gerrit commit 4f633859fd732f82ada8dbc823055e90d7318eae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 16:28:15 2015 -0500 rules.h: add fall through where no ENV_<STAGE> is set There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/rules.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/include/rules.h b/src/include/rules.h index 523031a..d147d3c 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,13 +63,27 @@ #define ENV_SECMON 0 #define ENV_VERSTAGE 1 -#else +#elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 + +#else +/* + * Default case of nothing set for random blob generation using + * create_class_compiler that isn't bound to a stage. Also AGES + * apparently builds compeletely separate from our build infrastructure + * hardcoding its own rules. + */ +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #endif /* For romstage and ramstage always build with simple device model, ie.

1 0

Patch set updated for coreboot: x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524 -gerrit commit d12ef8dfad8b39733bab9a0bba4b91ab1a1a24fa Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:45:18 2015 -0500 x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 +--------- src/lib/Makefile.inc | 9 ++++++--- src/lib/program.ld | 6 +++--- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b018f7c..885bb7f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -276,17 +276,11 @@ ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) -else -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64)) -endif - # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod cp $< $@ -else +endif ramstage-y += memlayout.ld @@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout. @printf " CC $(subst $(obj)/,,$(@))\n" $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld -endif - $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a89f7d4..f4d8c2c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -218,9 +218,12 @@ define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map - -$(strip $(1)).rmod: $(strip $(1)) - $$(RMODTOOL) -i $$^ -o $$@ endef endif + +$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@ + +$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@ diff --git a/src/lib/program.ld b/src/lib/program.ld index e30a945..f776541 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -33,14 +33,14 @@ *(.text); *(.text.*); -#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE || ENV_ROMSTAGE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(cbmem_init_hooks) KEEP(*(.rodata.cbmem_init_hooks)); SYMBOL_CURRENT_LOC(ecbmem_init_hooks) #endif -#if ENV_RAMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(pci_drivers) KEEP(*(.rodata.pci_driver)); @@ -87,7 +87,7 @@ #ifdef __PRE_RAM__ PROVIDE(_preram_cbmem_console = .); PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE || ENV_RMODULE +#elif ENV_RAMSTAGE SYMBOL_CURRENT_LOC(bs_init_begin) KEEP(*(.bs_init)); LONG(0);

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coreboot-gerrit September 2015