coreboot-gerrit September 2015

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New patch to review for coreboot: intel: Do not hardcode the position of mrc.cache
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11527 -gerrit commit 0e7badc4289cd72d6f6947e73ba9dbf4e12e582d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 01:54:23 2015 -0700 intel: Do not hardcode the position of mrc.cache The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_0/Kconfig | 11 ----------- src/drivers/intel/fsp1_0/Makefile.inc | 2 +- src/mainboard/intel/bakersport_fsp/Kconfig | 5 ----- src/mainboard/intel/bayleybay_fsp/Kconfig | 5 ----- src/mainboard/intel/minnowmax/Kconfig | 5 ----- src/mainboard/siemens/mc_tcu3/Kconfig | 5 ----- src/northbridge/intel/haswell/Makefile.inc | 2 +- src/northbridge/intel/nehalem/Makefile.inc | 2 +- src/northbridge/intel/sandybridge/Makefile.inc | 6 +----- 9 files changed, 4 insertions(+), 39 deletions(-) diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 020235a..8d3bf4c 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -82,17 +82,6 @@ config MRC_CACHE_SIZE should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in. -config MRC_CACHE_LOC - hex "Fast Boot Data Cache location in CBFS" - default 0xfff50000 - depends on ENABLE_MRC_CACHE - help - The location in CBFS for the MRC data to be cached. - - WARNING: This should be on a sector boundary of the BIOS ROM chip - and nothing else should be included in that sector, or IT WILL BE - ERASED. - config VIRTUAL_ROM_SIZE hex "Virtual ROM Size" default ROM_SIZE diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index ddc6bef..11ff31a 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -42,6 +42,6 @@ $(obj)/mrc.cache: cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := $(CONFIG_MRC_CACHE_LOC) +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index c382bac..3575ab3 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -50,11 +50,6 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP -config MRC_CACHE_LOC - hex - default 0xfff80000 - depends on ENABLE_FSP_FAST_BOOT - config CBFS_SIZE hex default 0x00200000 diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index a5c7605..9897cfc 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -50,11 +50,6 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" -config MRC_CACHE_LOC - hex - default 0xfff80000 - depends on ENABLE_FSP_FAST_BOOT - config CBFS_SIZE hex default 0x00200000 diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 636972f..39f84f1 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -49,11 +49,6 @@ config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" -config MRC_CACHE_LOC - hex - default 0xfff80000 - depends on ENABLE_FSP_FAST_BOOT - config CBFS_SIZE hex default 0x00300000 diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index a4939bf..f46c528 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -49,11 +49,6 @@ config CACHE_ROM_SIZE_OVERRIDE hex default 0x1000000 -config MRC_CACHE_LOC - hex - default 0xfff80000 - depends on ENABLE_FSP_FAST_BOOT - config CBFS_SIZE hex default 0x00e00000 diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ad4b2ba..8d038da 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -50,7 +50,7 @@ $(obj)/mrc.cache: $(obj)/config.h cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := 0xfffe0000 +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index e5b4385..63c49f2 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -42,7 +42,7 @@ $(obj)/mrc.cache: cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := 0xfffe0000 +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 407b61d..52fe23c 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -59,11 +59,7 @@ $(obj)/mrc.cache: $(obj)/config.h cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000 -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000 -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000 -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000 -mrc.cache-position := $(mrc-cache-position-y) +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif

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Patch set updated for coreboot: microcode: Unify rules to add microcode to CBFS once again
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526 -gerrit commit d08a25c56b869148ec05b8408551cc487995505f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:35:55 2015 -0700 microcode: Unify rules to add microcode to CBFS once again Now that cbfstool supports file alignment, we can use the conveniently available <filename>-align handler, and remove the need to have a separate rule in src/Makefile.inc just for adding the microcode. We can also get rid of the layering violation of having the CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile. Note that we still have a layering violation by the use of the CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable for the time being. Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 1 - src/cpu/Makefile.inc | 20 +++++++------------- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 7 insertions(+), 36 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..be6021b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $( -B $(objcbfs)/bootblock.bin \ $(CBFSTOOL_PRE1_OPTS) $(prebuild-files) true - $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index cdd353f..4ac4416 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64)) ## Rules for building the microcode blob in CBFS ################################################################################ -cpu_ucode_cbfs_name = cpu_microcode_blob.bin - # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) @@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin cbfs_include_ucode = y endif -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y) -cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)" -else -cpu_ucode_cbfs_offset = "-b" -endif - # In case we have more than one "source" (cough) files containing microcode, we # link them together in one large blob, so that we get all the microcode updates # in one file. This makes it easier for objcopy in the final step. @@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@ -ifeq ($(cbfs_include_ucode),y) -# Add CPU microcode to specified rom image $(1) -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset) +cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin +cpu_microcode_blob.bin-file := $(cpu_ucode_cbfs_file) +cpu_microcode_blob.bin-type := 0x53 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) else -add-cpu-microcode-to-cbfs = true +cpu_microcode_blob.bin-align := 16 endif diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -

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Patch merged into coreboot/master: cbfstool: Allow adding file with specific alignment requirement
by gerrit＠coreboot.org 07 Sep '15

07 Sep '15

the following patch was just integrated into master: commit 38bc916def3a95f2a32309c5437ac0f868455a94 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:05:44 2015 -0700 cbfstool: Allow adding file with specific alignment requirement Whenever we want to add a file to CBFS with a specific alignment, we have to do two cbfstool invocations: one to find a place for the file, and another to actually add the file to CBFS. Get rid of this nonsense and allow this to be done in one step. Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11525 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11525 for details. -gerrit

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Patch set updated for coreboot: microcode: Unify rules to add microcode to CBFS once again
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526 -gerrit commit 61b725eccbffe006fd7cd4060f3add5ae0d427f1 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:35:55 2015 -0700 microcode: Unify rules to add microcode to CBFS once again Now that cbfstool supports file alignment, we can use the conveniently available <filename>-align handler, and remove the need to have a separate rule in src/Makefile.inc just for adding the microcode. We can also get rid of the layering violation of having the CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile. Note that we still have a layering violation by the use of the CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable for the time being. Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 1 - src/cpu/Makefile.inc | 20 +++++++------------- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 7 insertions(+), 36 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..be6021b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $( -B $(objcbfs)/bootblock.bin \ $(CBFSTOOL_PRE1_OPTS) $(prebuild-files) true - $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index cdd353f..9f28b36 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64)) ## Rules for building the microcode blob in CBFS ################################################################################ -cpu_ucode_cbfs_name = cpu_microcode_blob.bin - # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) @@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin cbfs_include_ucode = y endif -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y) -cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)" -else -cpu_ucode_cbfs_offset = "-b" -endif - # In case we have more than one "source" (cough) files containing microcode, we # link them together in one large blob, so that we get all the microcode updates # in one file. This makes it easier for objcopy in the final step. @@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@ -ifeq ($(cbfs_include_ucode),y) -# Add CPU microcode to specified rom image $(1) -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset) +cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin +cpu_microcode_blob.bin-file = $(cpu_ucode_cbfs_file) +cpu_microcode_blob.bin-type = 0x53 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-position = $(CONFIG_CPU_MICROCODE_CBFS_LOC) else -add-cpu-microcode-to-cbfs = true +cpu_microcode_blob.bin-align = 16 endif diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -

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Patch set updated for coreboot: cbfstool: Allow adding file with specific alignment requirement
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11525 -gerrit commit cbe83ac4aa20848d1d44cd2a233f29140246506d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:05:44 2015 -0700 cbfstool: Allow adding file with specific alignment requirement Whenever we want to add a file to CBFS with a specific alignment, we have to do two cbfstool invocations: one to find a place for the file, and another to actually add the file to CBFS. Get rid of this nonsense and allow this to be done in one step. Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/cbfstool.c | 98 ++++++++++++++++++++++++++++++------------------ 1 file changed, 61 insertions(+), 37 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index a91b600..d6c116a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -328,8 +328,65 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer, return 0; } +static int do_cbfs_locate(int32_t *cbfs_addr) +{ + if (!param.filename) { + ERROR("You need to specify -f/--filename.\n"); + return 1; + } + + if (!param.name) { + ERROR("You need to specify -n/--name.\n"); + return 1; + } + + struct cbfs_image image; + if (cbfs_image_from_buffer(&image, param.image_region, + param.headeroffset)) + return 1; + + if (cbfs_get_entry(&image, param.name)) + WARN("'%s' already in CBFS.\n", param.name); + + struct buffer buffer; + if (buffer_from_file(&buffer, param.filename) != 0) { + ERROR("Cannot load %s.\n", param.filename); + return 1; + } + + int32_t address = cbfs_locate_entry(&image, param.name, buffer.size, + param.pagesize, param.alignment); + buffer_delete(&buffer); + + if (address == -1) { + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); + return 1; + } + + if (param.top_aligned) + address = -convert_to_from_top_aligned(param.image_region, + address); + + *cbfs_addr = address; + return 0; +} + static int cbfs_add(void) { + int32_t address; + + if (param.alignment && param.baseaddress) { + ERROR("Cannot specify both alignment and base address\n"); + return 1; + } + + if (param.alignment) { + if (do_cbfs_locate(&address)) + return 1; + param.baseaddress = address; + } + return cbfs_add_component(param.filename, param.name, param.type, @@ -494,43 +551,10 @@ static int cbfs_create(void) static int cbfs_locate(void) { - if (!param.filename) { - ERROR("You need to specify -f/--filename.\n"); - return 1; - } - - if (!param.name) { - ERROR("You need to specify -n/--name.\n"); - return 1; - } - - struct cbfs_image image; - if (cbfs_image_from_buffer(&image, param.image_region, - param.headeroffset)) - return 1; - - if (cbfs_get_entry(&image, param.name)) - WARN("'%s' already in CBFS.\n", param.name); + int32_t address; - struct buffer buffer; - if (buffer_from_file(&buffer, param.filename) != 0) { - ERROR("Cannot load %s.\n", param.filename); + if (do_cbfs_locate(&address) != 0) return 1; - } - - int32_t address = cbfs_locate_entry(&image, param.name, buffer.size, - param.pagesize, param.alignment); - buffer_delete(&buffer); - - if (address == -1) { - ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", - param.name, param.pagesize, param.alignment); - return 1; - } - - if (param.top_aligned) - address = -convert_to_from_top_aligned(param.image_region, - address); printf("0x%x\n", address); return 0; @@ -781,7 +805,7 @@ static bool cbfs_is_legacy_format(struct buffer *buffer) } static const struct command commands[] = { - {"add", "H:r:f:n:t:c:b:vh?", cbfs_add, true, true}, + {"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true, true}, {"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true}, @@ -896,7 +920,7 @@ static void usage(char *name) " -h Display this help message\n\n" "COMMANDs:\n" " add [-r image,regions] -f FILE -n NAME -t TYPE \\\n" - " [-c compression] [-b base-address] " + " [-c compression] [-b base-address | -a alignment] " "Add a component\n" " add-payload [-r image,regions] -f FILE -n NAME \\\n" " [-c compression] [-b base-address] "

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Patch set updated for coreboot: microcode: Unify rules to add microcode to CBFS once again
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526 -gerrit commit 5081046c0561712badd8cd54e0a0972a855aa300 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:35:55 2015 -0700 microcode: Unify rules to add microcode to CBFS once again Now that cbfstool supports file alignment, we can use the conveniently available <filename>-align handler, and remove the need to have a separate rule in src/Makefile.inc just for adding the microcode. We can also get rid of the layering violation of having the CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile. Note that we still have a layering violation by the use of the CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable for the time being. Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 1 - src/cpu/Makefile.inc | 20 +++++++------------- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 7 insertions(+), 36 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..be6021b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $( -B $(objcbfs)/bootblock.bin \ $(CBFSTOOL_PRE1_OPTS) $(prebuild-files) true - $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index cdd353f..9f28b36 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64)) ## Rules for building the microcode blob in CBFS ################################################################################ -cpu_ucode_cbfs_name = cpu_microcode_blob.bin - # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) @@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin cbfs_include_ucode = y endif -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y) -cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)" -else -cpu_ucode_cbfs_offset = "-b" -endif - # In case we have more than one "source" (cough) files containing microcode, we # link them together in one large blob, so that we get all the microcode updates # in one file. This makes it easier for objcopy in the final step. @@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@ -ifeq ($(cbfs_include_ucode),y) -# Add CPU microcode to specified rom image $(1) -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset) +cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin +cpu_microcode_blob.bin-file = $(cpu_ucode_cbfs_file) +cpu_microcode_blob.bin-type = 0x53 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-position = $(CONFIG_CPU_MICROCODE_CBFS_LOC) else -add-cpu-microcode-to-cbfs = true +cpu_microcode_blob.bin-align = 16 endif diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -

1 0

New patch to review for coreboot: microcode: Unify rules to add microcode to CBFS once again
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11526 -gerrit commit a5c0e0339f4cc82308cd19a1f25ef8631e7d4196 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:35:55 2015 -0700 microcode: Unify rules to add microcode to CBFS once again Now that cbfstool supports file alignment, we can use the conveniently available <filename>-align handler, and remove the need to have a separate rule in src/Makefile.inc just for adding the microcode. We can also get rid of the layering violation of having the CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile. Note that we still have a layering violation by the use of the CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable for the time being. Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 1 - src/cpu/Makefile.inc | 20 +++++++------------- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 7 insertions(+), 36 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..be6021b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -567,7 +567,6 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $( -B $(objcbfs)/bootblock.bin \ $(CBFSTOOL_PRE1_OPTS) $(prebuild-files) true - $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index cdd353f..cb49b27 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -18,8 +18,6 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_64)) ## Rules for building the microcode blob in CBFS ################################################################################ -cpu_ucode_cbfs_name = cpu_microcode_blob.bin - # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) @@ -31,12 +29,6 @@ cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin cbfs_include_ucode = y endif -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0), y) -cpu_ucode_cbfs_offset = "-b $(CONFIG_CPU_MICROCODE_CBFS_LOC)" -else -cpu_ucode_cbfs_offset = "-b" -endif - # In case we have more than one "source" (cough) files containing microcode, we # link them together in one large blob, so that we get all the microcode updates # in one file. This makes it easier for objcopy in the final step. @@ -52,10 +44,12 @@ $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY_cpu_microcode) -j .data -O binary $< $@ -ifeq ($(cbfs_include_ucode),y) -# Add CPU microcode to specified rom image $(1) -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 $(cpu_ucode_cbfs_offset) +cbfs-files-$(cbfs_include_ucode) += cpu_microcode_blob.bin +cpu_microcode_blob.bin-file = $(cpu_ucode_cbfs_file) +cpu_microcode_blob.bin-type = 0x53 + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +cpu_microcode_blob.bin-position = $(CONFIG_CPU_MICROCODE_CBFS_LOC) else -add-cpu-microcode-to-cbfs = true +cpu_microcode_blob.bin-align = 0x10000 endif diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -

1 0

New patch to review for coreboot: cbfstool: Allow adding file with specific alignemt requirement
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11525 -gerrit commit 6f54edb63128ccfe66f498a115149c0b04d7703a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 00:05:44 2015 -0700 cbfstool: Allow adding file with specific alignemt requirement Whenever we want to add a file to CBFS with a specific alignment, we have to do two cbfstool invocations: one to find a place for the file, and another to actually add the file to CBFS. Get rid of this nonsense and allow this to be done in one step. Change-Id: I526483296b494363f15dc169f163d93a6fc71bb0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/cbfstool.c | 98 ++++++++++++++++++++++++++++++------------------ 1 file changed, 61 insertions(+), 37 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index a91b600..d6c116a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -328,8 +328,65 @@ static int cbfstool_convert_mkflatpayload(struct buffer *buffer, return 0; } +static int do_cbfs_locate(int32_t *cbfs_addr) +{ + if (!param.filename) { + ERROR("You need to specify -f/--filename.\n"); + return 1; + } + + if (!param.name) { + ERROR("You need to specify -n/--name.\n"); + return 1; + } + + struct cbfs_image image; + if (cbfs_image_from_buffer(&image, param.image_region, + param.headeroffset)) + return 1; + + if (cbfs_get_entry(&image, param.name)) + WARN("'%s' already in CBFS.\n", param.name); + + struct buffer buffer; + if (buffer_from_file(&buffer, param.filename) != 0) { + ERROR("Cannot load %s.\n", param.filename); + return 1; + } + + int32_t address = cbfs_locate_entry(&image, param.name, buffer.size, + param.pagesize, param.alignment); + buffer_delete(&buffer); + + if (address == -1) { + ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", + param.name, param.pagesize, param.alignment); + return 1; + } + + if (param.top_aligned) + address = -convert_to_from_top_aligned(param.image_region, + address); + + *cbfs_addr = address; + return 0; +} + static int cbfs_add(void) { + int32_t address; + + if (param.alignment && param.baseaddress) { + ERROR("Cannot specify both alignment and base address\n"); + return 1; + } + + if (param.alignment) { + if (do_cbfs_locate(&address)) + return 1; + param.baseaddress = address; + } + return cbfs_add_component(param.filename, param.name, param.type, @@ -494,43 +551,10 @@ static int cbfs_create(void) static int cbfs_locate(void) { - if (!param.filename) { - ERROR("You need to specify -f/--filename.\n"); - return 1; - } - - if (!param.name) { - ERROR("You need to specify -n/--name.\n"); - return 1; - } - - struct cbfs_image image; - if (cbfs_image_from_buffer(&image, param.image_region, - param.headeroffset)) - return 1; - - if (cbfs_get_entry(&image, param.name)) - WARN("'%s' already in CBFS.\n", param.name); + int32_t address; - struct buffer buffer; - if (buffer_from_file(&buffer, param.filename) != 0) { - ERROR("Cannot load %s.\n", param.filename); + if (do_cbfs_locate(&address) != 0) return 1; - } - - int32_t address = cbfs_locate_entry(&image, param.name, buffer.size, - param.pagesize, param.alignment); - buffer_delete(&buffer); - - if (address == -1) { - ERROR("'%s' can't fit in CBFS for page-size %#x, align %#x.\n", - param.name, param.pagesize, param.alignment); - return 1; - } - - if (param.top_aligned) - address = -convert_to_from_top_aligned(param.image_region, - address); printf("0x%x\n", address); return 0; @@ -781,7 +805,7 @@ static bool cbfs_is_legacy_format(struct buffer *buffer) } static const struct command commands[] = { - {"add", "H:r:f:n:t:c:b:vh?", cbfs_add, true, true}, + {"add", "H:r:f:n:t:c:b:a:vh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:vh?", cbfs_add_flat_binary, true, true}, {"add-payload", "H:r:f:n:t:c:b:C:I:vh?", cbfs_add_payload, true, true}, @@ -896,7 +920,7 @@ static void usage(char *name) " -h Display this help message\n\n" "COMMANDs:\n" " add [-r image,regions] -f FILE -n NAME -t TYPE \\\n" - " [-c compression] [-b base-address] " + " [-c compression] [-b base-address | -a alignment] " "Add a component\n" " add-payload [-r image,regions] -f FILE -n NAME \\\n" " [-c compression] [-b base-address] "

1 0

Patch set updated for coreboot: x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524 -gerrit commit f55d0f69940b5dfde3496e8a56e2d4067aaad549 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:45:18 2015 -0500 x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 +--------- src/lib/Makefile.inc | 9 ++++++--- src/lib/program.ld | 6 +++--- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b018f7c..885bb7f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -276,17 +276,11 @@ ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) -else -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64)) -endif - # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod cp $< $@ -else +endif ramstage-y += memlayout.ld @@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout. @printf " CC $(subst $(obj)/,,$(@))\n" $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld -endif - $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a89f7d4..f4d8c2c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -218,9 +218,12 @@ define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map - -$(strip $(1)).rmod: $(strip $(1)) - $$(RMODTOOL) -i $$^ -o $$@ endef endif + +$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@ + +$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@ diff --git a/src/lib/program.ld b/src/lib/program.ld index 43b1fea..794dcf8 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -33,14 +33,14 @@ *(.text); *(.text.*); -#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE || ENV_ROMSTAGE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(cbmem_init_hooks) KEEP(*(.rodata.cbmem_init_hooks)); SYMBOL_CURRENT_LOC(ecbmem_init_hooks) #endif -#if ENV_RAMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(pci_drivers) KEEP(*(.rodata.pci_driver)); @@ -87,7 +87,7 @@ #ifdef __PRE_RAM__ PROVIDE(_preram_cbmem_console = .); PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE || ENV_RMODULE +#elif ENV_RAMSTAGE ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) SYMBOL_CURRENT_LOC(bs_init_begin) KEEP(*(.bs_init));

1 0

Patch set updated for coreboot: rmodtool: make rmodule parameter section optional
by Aaron Durbin 07 Sep '15

07 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523 -gerrit commit eaf1bd0aa281c4972feb842eb9206678d907f8cf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:39:10 2015 -0500 rmodtool: make rmodule parameter section optional There are currently 2 uses for rmodule programs: stand alone programs that are separate from the coreboot stages and a relocatable ramstage. For the ramstage usage there's no reason to require a rmodule parameter section. Therefore make this optional. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built ramstage w/ normal linking (w/o a rmodule parameter section). No error. Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- util/cbfstool/rmodule.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index c35eff7..1f41d17 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx) static int populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr, - int nsyms, const char *strtab) + int nsyms, const char *strtab, int optional) { int i; Elf64_Sym *syms; @@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr, *addr = syms[i].st_value; return 0; } + + if (optional) { + DEBUG("optional symbol '%s' not found.\n", sym_name); + *addr = 0; + return 0; + } + ERROR("symbol '%s' not found.\n", sym_name); return -1; } @@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx) } if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin, - nsyms, strtab)) + nsyms, strtab, 1)) return -1; if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end, - nsyms, strtab)) + nsyms, strtab, 1)) return -1; - if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab)) + if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0)) return -1; - if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) + if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0)) return -1; /* Honor the entry point within the ELF header. */

1 0

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coreboot-gerrit September 2015