coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: skylake: ACPI: Add functions for PCR access
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11531 -gerrit commit b4a6e17f80dd95bd6f0d4666815d336b026cd401 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:03:45 2015 -0700 skylake: ACPI: Add functions for PCR access There are a few places in ACPI that touch PCR registers, either to read a value or to set some magic bits. Expose some functions for this that will keep all the PCR access in one location instead of spread throughout the code. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1 Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295904 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/pch.asl | 2 + src/soc/intel/skylake/acpi/pcr.asl | 75 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 18a41f2..581efa0 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -37,6 +37,8 @@ /* PCIE Ports */ #include "pcie.asl" +/* PCR Access */ +#include "pcr.asl" /* Serial IO */ #include "serialio.asl" diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl new file mode 100644 index 0000000..a6fb46e --- /dev/null +++ b/src/soc/intel/skylake/acpi/pcr.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* + * Calculate PCR register base at specified PID + * Arg0 - PCR Port ID + */ +Method (PCRB, 1, NotSerialized) +{ + Return (Add (PCH_PCR_BASE_ADDRESS, ShiftLeft (Arg0, PCR_PORTID_SHIFT))) +} + +/* + * Read a PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + */ +Method (PCRR, 2, NotSerialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Return (DATA) +} + +/* + * AND a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to AND + */ +Method (PCRA, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + And (DATA, Arg2, DATA) +} + +/* + * OR a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to OR + */ +Method (PCRO, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Or (DATA, Arg2, DATA) +}

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New patch to review for coreboot: skylake: ACPI: Clean up pch.asl
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11530 -gerrit commit 8bd80cd399905cef6863e5925564b5d3598bd872 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:01:08 2015 -0700 skylake: ACPI: Clean up pch.asl Clean up the code in pch.asl: - move all the C header includes into here instead of duplicated in various ASL files included from here - move the trap field definition into platform.asl with the method - alphebetize the includes - move gpio.asl include into pch.asl - remove duplicate irqlinks.asl include from lpc.asl BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295903 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/gpio.asl | 4 ---- src/soc/intel/skylake/acpi/lpc.asl | 3 --- src/soc/intel/skylake/acpi/pch.asl | 40 +++++++++++++++------------------ src/soc/intel/skylake/acpi/platform.asl | 10 +++++++++ src/soc/intel/skylake/acpi/serialio.asl | 1 - 5 files changed, 28 insertions(+), 30 deletions(-) diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 3b4740b..7c2efa6 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -18,10 +18,6 @@ * Foundation, Inc. */ -#include <soc/irq.h> -#include <soc/iomap.h> -#include <soc/pcr.h> -#include <soc/gpio_defs.h> /* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */ Method (PCRR, 2, Serialized) diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index 8332980..877be99 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -19,7 +19,6 @@ * Foundation, Inc. */ -#include <soc/iomap.h> // Intel LPC Bus Device - 0:1f.0 @@ -169,8 +168,6 @@ Device (LPCB) }) } - #include "gpio.asl" - #include "irqlinks.asl" #include <acpi/ec.asl> #include <acpi/superio.asl> } diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 2621eb2..18a41f2 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -20,38 +20,34 @@ */ #include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/gpio_defs.h> +#include <soc/gpe.h> +#include <soc/pcr.h> -Scope (\) -{ - /* IO-Trap at 0x800. - * This is the ACPI->SMI communication interface. - */ - OperationRegion (IO_T, SystemIO, 0x800, 0x10) - Field (IO_T, ByteAcc, NoLock, Preserve) - { - Offset (0x8), - TRP0, 8 /* IO-Trap at 0x808 */ - } -} +/* GPIO Controller */ +#include "gpio.asl" + +/* Interrupt Routing */ +#include "irqlinks.asl" -/* PCI Express Ports 0:1c.x */ +/* LPC 0:1f.0 */ +#include "lpc.asl" + +/* PCIE Ports */ #include "pcie.asl" -/* USB XHCI 0:14.0 */ -#include "xhci.asl" -/* LPC Bridge 0:1f.0 */ -#include "lpc.asl" +/* Serial IO */ +#include "serialio.asl" /* SMBus 0:1f.3 */ #include "smbus.asl" -/* Serial IO */ -#include "serialio.asl" -/* Interrupt Routing */ #include "itss.asl" -#include "irqlinks.asl" +/* USB XHCI 0:14.0 */ +#include "xhci.asl" Method (_OSC, 4) { diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl index 2bbe97b..f0ed4e0 100644 --- a/src/soc/intel/skylake/acpi/platform.asl +++ b/src/soc/intel/skylake/acpi/platform.asl @@ -36,6 +36,16 @@ Field (POST, ByteAcc, Lock, Preserve) DBG0, 8 } +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + /* SMI I/O Trap */ Method (TRAP, 1, Serialized) { diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index c6f5446..e57b937 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc. */ -#include <soc/irq.h> // Intel Serial IO Devices in ACPI Mode

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New patch to review for coreboot: skylake: ACPI: Fix and clean up PCIE _PRT entries
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11529 -gerrit commit f441c0308c5347ac7bf53d018fcdc9ac31627485 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 15:49:12 2015 -0700 skylake: ACPI: Fix and clean up PCIE _PRT entries Fix the code for PCIE _PRT entries to use an actual root port number from the device instead of NVS that was never initialized from zero. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados with pci=nomsi to ensure interrupts work Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295902 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/globalnvs.asl | 14 +- src/soc/intel/skylake/acpi/pcie.asl | 225 +++++++++++++++++++++---------- src/soc/intel/skylake/include/soc/nvs.h | 5 +- 3 files changed, 156 insertions(+), 88 deletions(-) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index b3d1bd2..b41fa42 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -63,19 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - RPA1, 32, // 0x30 - 0x33 - Root port address 1 - RPA2, 32, // 0x34 - 0x37 - Root port address 2 - RPA3, 32, // 0x38 - 0x3b - Root port address 3 - RPA4, 32, // 0x3c - 0x3f - Root port address 4 - RPA5, 32, // 0x40 - 0x43 - Root port address 5 - RPA6, 32, // 0x44 - 0x47 - Root port address 6 - RPA7, 32, // 0x48 - 0x4b - Root port address 7 - RPA8, 32, // 0x4c - 0x4f - Root port address 8 - RPA9, 32, // 0x50 - 0x53 - Root port address 9 - RPAA, 32, // 0x54 - 0x57 - Root port address 10 - RPAB, 32, // 0x58 - 0x5b - Root port address 11 - RPAC, 32, // 0x5c - 0x5f - Root port address 12 - DPTE, 8, // 0x60 - Enable DPTF + DPTE, 8, // 0x30 - Enable DPTF /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 7ab78e0..52b07da 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -24,56 +24,56 @@ Method (IRQM, 1, Serialized) { /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } }) + Name (IQAA, Package () { + Package () { 0x0000ffff, 0, 0, 16 }, + Package () { 0x0000ffff, 1, 0, 17 }, + Package () { 0x0000ffff, 2, 0, 18 }, + Package () { 0x0000ffff, 3, 0, 19 } }) + Name (IQAP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } }) /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } }) + Name (IQBA, Package () { + Package () { 0x0000ffff, 0, 0, 17 }, + Package () { 0x0000ffff, 1, 0, 18 }, + Package () { 0x0000ffff, 2, 0, 19 }, + Package () { 0x0000ffff, 3, 0, 16 } }) + Name (IQBP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } }) /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } }) + Name (IQCA, Package () { + Package () { 0x0000ffff, 0, 0, 18 }, + Package () { 0x0000ffff, 1, 0, 19 }, + Package () { 0x0000ffff, 2, 0, 16 }, + Package () { 0x0000ffff, 3, 0, 17 } }) + Name (IQCP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } }) /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { + Name (IQDA, Package () { + Package () { 0x0000ffff, 0, 0, 19 }, + Package () { 0x0000ffff, 1, 0, 16 }, + Package () { 0x0000ffff, 2, 0, 17 }, + Package () { 0x0000ffff, 3, 0, 18 } }) + Name (IQDP, Package () { + Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 }, + Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } }) + + Switch (ToInteger (Arg0)) + { + Case (Package () { 1, 5, 9 }) { If (PICM) { Return (IQAA) } Else { @@ -81,8 +81,7 @@ Method (IRQM, 1, Serialized) { } } - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { + Case (Package () { 2, 6, 10 }) { If (PICM) { Return (IQBA) } Else { @@ -90,8 +89,7 @@ Method (IRQM, 1, Serialized) { } } - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { + Case (Package () { 3, 7, 11 }) { If (PICM) { Return (IQCA) } Else { @@ -99,8 +97,7 @@ Method (IRQM, 1, Serialized) { } } - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { + Case (Package () { 4, 8, 12 }) { If (PICM) { Return (IQDA) } Else { @@ -120,90 +117,154 @@ Method (IRQM, 1, Serialized) { Device (RP01) { - Name (_ADR, 0x001c0000) + Name (_ADR, 0x001C0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA1)) + Return (IRQM (RPPN)) } } Device (RP02) { - Name (_ADR, 0x001c0001) + Name (_ADR, 0x001C0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA2)) + Return (IRQM (RPPN)) } } Device (RP03) { - Name (_ADR, 0x001c0002) + Name (_ADR, 0x001C0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA3)) + Return (IRQM (RPPN)) } } Device (RP04) { - Name (_ADR, 0x001c0003) + Name (_ADR, 0x001C0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA4)) + Return (IRQM (RPPN)) } } Device (RP05) { - Name (_ADR, 0x001c0004) + Name (_ADR, 0x001C0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA5)) + Return (IRQM (RPPN)) } } Device (RP06) { - Name (_ADR, 0x001c0005) + Name (_ADR, 0x001C0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA6)) + Return (IRQM (RPPN)) } } Device (RP07) { - Name (_ADR, 0x001c0006) + Name (_ADR, 0x001C0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA7)) + Return (IRQM (RPPN)) } } Device (RP08) { - Name (_ADR, 0x001c0007) + Name (_ADR, 0x001C0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPA8)) + Return (IRQM (RPPN)) } } + Device (RP09) { Name (_ADR, 0x001D0000) + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + Method (_PRT) { - Return (IRQM (RPA9)) + Return (IRQM (RPPN)) } } @@ -211,9 +272,16 @@ Device (RP10) { Name (_ADR, 0x001D0001) + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + Method (_PRT) { - Return (IRQM (RPAA)) + Return (IRQM (RPPN)) } } @@ -221,19 +289,32 @@ Device (RP11) { Name (_ADR, 0x001D0002) + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + Method (_PRT) { - Return (IRQM (RPAB)) + Return (IRQM (RPPN)) } } Device (RP12) { - Name (_ADR, 0x001D0003) + Name (_ADR, 0x001D0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } Method (_PRT) { - Return (IRQM (RPAC)) + Return (IRQM (RPPN)) } } - diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 7fef190..2d8129b 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -55,10 +55,9 @@ typedef struct { u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u32 rpa[12]; /* 0x30 - 0x5f - Root Port Address */ - u8 dpte; /* 0x60 - Enable DPTF */ + u8 dpte; /* 0x30 - Enable DPTF */ - u8 unused[159]; + u8 unused[207]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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New patch to review for coreboot: glados: Update 4GB DIMM SPD for 1866
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11528 -gerrit commit 4274c420ffb41059cea66364645c63b9df6845ce Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Aug 21 13:09:10 2015 -0700 glados: Update 4GB DIMM SPD for 1866 Enable 1866 timings in the 4GB Hynix SPD. BUG=chrome-os-partner:44394 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423 Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295174 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex index c296c88..c23ecbd 100644 --- a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex @@ -1,6 +1,6 @@ -91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 50 05 78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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Patch merged into coreboot/master: intel: Do not hardcode the position of mrc.cache
by gerrit＠coreboot.org 07 Sep '15

07 Sep '15

the following patch was just integrated into master: commit 2c482a969a546a70c2787d4d96d1ac212da11eff Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Sep 7 01:54:23 2015 -0700 intel: Do not hardcode the position of mrc.cache The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11527 for details. -gerrit

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Patch merged into coreboot/master: Drop "See file CREDITS..." comment
by gerrit＠coreboot.org 07 Sep '15

07 Sep '15

the following patch was just integrated into master: commit 4460703f59c58626c762a8a1244842b7a3efe0db Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Sat Sep 5 07:51:32 2015 -0700 Drop "See file CREDITS..." comment coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11514 for details. -gerrit

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Patch set updated for coreboot: fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8485 -gerrit commit f644a4dbbd823c8a48bde75b71f67429f93b9b5b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Feb 18 14:51:41 2015 -0600 fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a mess of it, by forcing a build-time error when CONFIG_POST_IO was not being set. fsp 1.0 boards ended 'select'ing this in their Kconfig. Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the "select POST_IO" from boards that have it. Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_0/cache_as_ram.inc | 18 +++++------------- src/mainboard/intel/bakersport_fsp/Kconfig | 1 - src/mainboard/intel/bayleybay_fsp/Kconfig | 1 - src/mainboard/intel/minnowmax/Kconfig | 4 ---- src/mainboard/intel/mohonpeak/Kconfig | 1 - 5 files changed, 5 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index cdbda54..32da60f8 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -29,16 +29,6 @@ # error "CONFIG_FSP_LOC must be set." #endif -#ifndef CONFIG_POST_IO -# error "CONFIG_POST_IO must be set." -#endif - -#if CONFIG_POST_IO -# ifndef CONFIG_POST_IO_PORT -# error "CONFIG_POST_IO_PORT must be set." -# endif -#endif - #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." #endif @@ -145,11 +135,13 @@ halt2: movb $0xBB, %ah .Lhlt: + /* + * Here, we show a 16-bit POST code. %al is the return value from the + * FSP blob, and %ah is an indicator of where we came from. + */ xchg %al, %ah -#if CONFIG_POST_IO +#if IS_ENABLED(CONFIG_POST_IO) outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) #endif movl $LHLT_DELAY, %ecx .Lhlt_Delay: diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index c382bac..c42f7fc 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select TSC_MONOTONIC_TIMER diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index a5c7605..e4a5ace 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select TSC_MONOTONIC_TIMER diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 636972f..c3265d7 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -68,10 +68,6 @@ config VIRTUAL_ROM_SIZE depends on ENABLE_FSP_FAST_BOOT default 0x800000 -config POST_IO - bool - default n - config POST_DEVICE bool default n diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 996cea2..0085da4 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select MMCONF_SUPPORT - select POST_IO select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT config MAINBOARD_DIR

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Patch set updated for coreboot: drivers/pc80: Do not initialize PS2 keyboard by default
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8599 -gerrit commit 4a1dd447e053f574c02278823f458723c56b5398 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Mar 3 22:37:44 2015 -0600 drivers/pc80: Do not initialize PS2 keyboard by default The most common payloads do not need this set, so optimize for the common case. Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/pc80/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 0ed1ecf..18c626c 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -4,7 +4,7 @@ if PC80_SYSTEM config DRIVERS_PS2_KEYBOARD bool "PS/2 keyboard init" - default y + default n help Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

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Patch set updated for coreboot: fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8485 -gerrit commit 782b1ab60f17e089da321b175a771f533f2664d5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Feb 18 14:51:41 2015 -0600 fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a mess of it, by forcing a build-time error when CONFIG_POST_IO was not being set. fsp 1.0 boards ended 'select'ing this in their Kconfig. Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the "select POST_IO" from boards that have it. Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_0/cache_as_ram.inc | 18 +++++------------- src/mainboard/intel/bakersport_fsp/Kconfig | 1 - src/mainboard/intel/bayleybay_fsp/Kconfig | 1 - src/mainboard/intel/minnowmax/Kconfig | 4 ---- src/mainboard/intel/mohonpeak/Kconfig | 1 - 5 files changed, 5 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index cdbda54..b025932 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -29,16 +29,6 @@ # error "CONFIG_FSP_LOC must be set." #endif -#ifndef CONFIG_POST_IO -# error "CONFIG_POST_IO must be set." -#endif - -#if CONFIG_POST_IO -# ifndef CONFIG_POST_IO_PORT -# error "CONFIG_POST_IO_PORT must be set." -# endif -#endif - #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." #endif @@ -145,11 +135,13 @@ halt2: movb $0xBB, %ah .Lhlt: + /* + * Here, we show a 16-bit POST code. %al is the return value from the + * FSP blob, and %ah is an indicator of where we came from. + */ xchg %al, %ah -#if CONFIG_POST_IO +if IS_ENABLED(CONFIG_POST_IO) outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) #endif movl $LHLT_DELAY, %ecx .Lhlt_Delay: diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index c382bac..c42f7fc 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select TSC_MONOTONIC_TIMER diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index a5c7605..e4a5ace 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select TSC_MONOTONIC_TIMER diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 636972f..c3265d7 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -68,10 +68,6 @@ config VIRTUAL_ROM_SIZE depends on ENABLE_FSP_FAST_BOOT default 0x800000 -config POST_IO - bool - default n - config POST_DEVICE bool default n diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 996cea2..0085da4 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select MMCONF_SUPPORT - select POST_IO select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT config MAINBOARD_DIR

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Patch set updated for coreboot: drivers/pc80: Do not initialize PS2 keyboard by default
by Alexandru Gagniuc 07 Sep '15

07 Sep '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8599 -gerrit commit f0c3d7b2eebde37422083e8bd251726e3a926e8f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Mar 3 22:37:44 2015 -0600 drivers/pc80: Do not initialize PS2 keyboard by default The most common payloads do not need this set, so optimize for the common case. Change-Id: I2e5b68d74e9b91b41bbbcffc17d31d5c1bb38fd4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- 3rdparty/arm-trusted-firmware | 1 - 3rdparty/blobs | 1 - 3rdparty/vboot | 1 - src/drivers/pc80/Kconfig | 2 +- 4 files changed, 1 insertion(+), 4 deletions(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware deleted file mode 160000 index 649591b..0000000 --- a/3rdparty/arm-trusted-firmware +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 649591bbabbc737534943136751722307429b7d6 diff --git a/3rdparty/blobs b/3rdparty/blobs deleted file mode 160000 index b4ade40..0000000 --- a/3rdparty/blobs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7 diff --git a/3rdparty/vboot b/3rdparty/vboot deleted file mode 160000 index fbf631c..0000000 --- a/3rdparty/vboot +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fbf631c845c08299f0bcbae3f311c5807d34c0d6 diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 0ed1ecf..18c626c 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -4,7 +4,7 @@ if PC80_SYSTEM config DRIVERS_PS2_KEYBOARD bool "PS/2 keyboard init" - default y + default n help Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

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coreboot-gerrit September 2015