coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: skylake: fix eventlog on resume path
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11541 -gerrit commit 272ccdb7ac76329e92c3b71e5666c2b2dfe634c9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 28 02:14:48 2015 -0500 skylake: fix eventlog on resume path The spi_init() routine needs to be called in all boot paths to allow writes to the SPI part. The reason is that the write enable is done in spi_init(). Moreover, this is also required for a writing a firmware update after a resume. BUG=chrome-os-partner:42115 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Eventlogs show up in resume path. Change-Id: I187baa940bb45ef90ab82e67c02f13d8855d364e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8813ab227395cfcba46ad4109730a1eb5897e538 Original-Change-Id: Ida726fc29e6d49cd9af02c4e57125e09f2599c36 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295238 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/flash_controller.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 549e883..a243eb1 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -457,3 +457,15 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) } #endif +#if ENV_RAMSTAGE +/* + * spi_init() needs run unconditionally in every boot (including resume) to + * allow write protect to be disabled for eventlog and firmware updates. + */ +static void spi_init_cb(void *unused) +{ + spi_init(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, spi_init_cb, NULL); +#endif

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New patch to review for coreboot: skylake: allow timer_monotonic_get() in all stages
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11540 -gerrit commit 37fa5de61c1751104e26eb6f7e5143ce1fd7055c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 28 01:58:18 2015 -0500 skylake: allow timer_monotonic_get() in all stages The timer_monotonic_get() function wasn't being compiled for romstage. To simplify the implementation don't keep track of partial microsecond ticks and just return the MSR value divided by 24 (24MHz clock). BUG=chrome-os-partner:42115 BRANCH=None TEST=Build and booted glados. Used monotonic timers in romstage in subsequent patches. Change-Id: I8294c74abe09947fb4438bf5c1d0fc5265491694 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6d60ef204fc92c26748ab57d4ff37830cd8dc664 Original-Change-Id: Ibdb6b9e20b9f2d48ff0f8a8c782f5c1f7ddde4f7 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295237 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/monotonic_timer.c | 27 ++------------------------- 2 files changed, 3 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index defb945..3bd9823 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -13,6 +13,7 @@ subdirs-y += ../../../cpu/x86/tsc romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += memmap.c +romstage-y += monotonic_timer.c romstage-y += pch.c romstage-y += pcr.c romstage-y += pei_data.c diff --git a/src/soc/intel/skylake/monotonic_timer.c b/src/soc/intel/skylake/monotonic_timer.c index 35ad911..55430ef 100644 --- a/src/soc/intel/skylake/monotonic_timer.c +++ b/src/soc/intel/skylake/monotonic_timer.c @@ -23,12 +23,6 @@ #include <timer.h> #include <soc/msr.h> -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint32_t last_value; -} mono_counter; - static inline uint32_t read_counter_msr(void) { /* @@ -44,23 +38,6 @@ static inline uint32_t read_counter_msr(void) void timer_monotonic_get(struct mono_time *mt) { - uint32_t current_tick; - uint32_t usecs_elapsed; - - if (!mono_counter.initialized) { - mono_counter.last_value = read_counter_msr(); - mono_counter.initialized = 1; - } - - current_tick = read_counter_msr(); - usecs_elapsed = (current_tick - mono_counter.last_value) / 24; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; + /* Always increases. Don't normalize to 0 between stages. */ + mono_time_set_usecs(mt, read_counter_msr() / 24); }

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New patch to review for coreboot: skylake: ACPI: Clean up formatting in ASL code
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11539 -gerrit commit 7bf0922d8ec1746c27de0adba3d6229c04ab0226 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 17:19:24 2015 -0700 skylake: ACPI: Clean up formatting in ASL code Clean up the formatting in various ASL files and remove unused and/or incorrect field definitions. Add back the methods to set the USB power in S3 field in NVS as it is called by the chromium kernel at boot and is currently complaining that the method is not found. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879 Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295952 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/globalnvs.asl | 11 ++ src/soc/intel/skylake/acpi/lpc.asl | 99 +++++-------- src/soc/intel/skylake/acpi/pci_irqs.asl | 230 ++++++++++++++--------------- src/soc/intel/skylake/acpi/systemagent.asl | 172 +++++++-------------- 4 files changed, 216 insertions(+), 296 deletions(-) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 0208198..31711d1 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -68,7 +68,18 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> +} +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) } /* Set flag to enable USB charging in S5 */ diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index 877be99..c841311 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -19,33 +19,16 @@ * Foundation, Inc. */ - -// Intel LPC Bus Device - 0:1f.0 - Device (LPCB) { Name (_ADR, 0x001f0000) + Name (_DDN, "LPC Bus Device") - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) - Field (LPC0, AnyAcc, NoLock, Preserve) - { - Offset (0x02), - PDID, 16, // Device ID - Offset (0x40), - PMBS, 16, // PMBASE - Offset (0x48), - GPBS, 16, // GPIOBASE - - - Offset (0x80), // IO Decode Ranges - IOD0, 8, - IOD1, 8, - } - - Device (DMAC) // DMA Controller + Device (DMAC) { - Name (_HID, EISAID("PNP0200")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0200")) + Name (_DDN, "DMA Controller") + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -55,40 +38,34 @@ Device (LPCB) }) } - Device (FWH) // Firmware Hub + Device (FWH) { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("INT0800")) + Name (_DDN, "Firmware Hub") + Name (_CRS, ResourceTemplate () { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) }) } Device (HPET) { - Name (_HID, EISAID("PNP0103")) - Name (BUF0, ResourceTemplate() + Name (_HID, EISAID ("PNP0103")) + Name (_DDN, "High Precision Event Timer") + Name (_CRS, ResourceTemplate () { - Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) }) - - Method (_STA, 0) // Device Status + Method (_STA, 0) { Return (0xf) } - Method (_CRS, 0, Serialized) // Current resources - { - CreateDWordField (BUF0, ^FED0._BAS, HPT0) - /* TODO: Base address configured need to pass as GNVS */ - Store(HPET_BASE_ADDRESS, HPT0) - - Return(BUF0) - } } - Device(PIC) // 8259 Interrupt Controller + Device (PIC) { - Name (_HID,EISAID("PNP0000")) + Name (_HID, EISAID ("PNP0000")) + Name (_DDN, "8259 Interrupt Controller") Name (_CRS, ResourceTemplate() { IO (Decode16, 0x20, 0x20, 0x01, 0x02) @@ -112,22 +89,23 @@ Device (LPCB) }) } - Device(MATH) // FPU + Device (MATH) { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0C04")) + Name (_DDN, "Floating Point Unit") + Name (_CRS, ResourceTemplate () { IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } + IRQNoFlags () { 13 } }) } - Device(LDRC) // LPC device: Resource consumption + Device (LDRC) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) - - Name (RBUF, ResourceTemplate() + Name (_DDN, "Legacy Device Resources") + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO @@ -141,30 +119,27 @@ Device (LPCB) IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff) }) - - Method (_CRS, 0, NotSerialized) - { - Return (RBUF) - } } - Device (RTC) // Real Time Clock + Device (RTC) { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0B00")) + Name (_DDN, "Real Time Clock") + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x70, 0x70, 1, 8) - //IRQNoFlags() { 8 } }) } - Device (TIMR) // Intel 8254 timer + Device (TIMR) { - Name (_HID, EISAID("PNP0100")) - Name (_CRS, ResourceTemplate() { + Name (_HID, EISAID ("PNP0100")) + Name (_DDN, "8254 Timer") + Name (_CRS, ResourceTemplate () + { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} + IRQNoFlags () {0} }) } diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl index c43e42d..3bf5f3e 100644 --- a/src/soc/intel/skylake/acpi/pci_irqs.asl +++ b/src/soc/intel/skylake/acpi/pci_irqs.asl @@ -19,125 +19,121 @@ * Foundation, Inc. */ -Method(_PRT) +Name (PICP, Package () { + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package () { 0x001FFFFF, 0, 0, 16 }, + Package () { 0x001FFFFF, 1, 0, 17 }, + Package () { 0x001FFFFF, 2, 0, 18 }, + Package () { 0x001FFFFF, 3, 0, 19 }, + /* D30: SerialIo and SCS */ + Package () { 0x001EFFFF, 0, 0, 20 }, + Package () { 0x001EFFFF, 1, 0, 21 }, + Package () { 0x001EFFFF, 2, 0, 22 }, + Package () { 0x001EFFFF, 3, 0, 23 }, + /* D29: PCI Express Port 9-16 */ + Package () { 0x001DFFFF, 0, 0, 16 }, + Package () { 0x001DFFFF, 1, 0, 17 }, + Package () { 0x001DFFFF, 2, 0, 18 }, + Package () { 0x001DFFFF, 3, 0, 19 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, 0, 16 }, + Package () { 0x001CFFFF, 1, 0, 17 }, + Package () { 0x001CFFFF, 2, 0, 18 }, + Package () { 0x001CFFFF, 3, 0, 19 }, + /* D27: PCI Express Port 17-20 */ + Package () { 0x001BFFFF, 0, 0, 16 }, + Package () { 0x001BFFFF, 1, 0, 17 }, + Package () { 0x001BFFFF, 2, 0, 18 }, + Package () { 0x001BFFFF, 3, 0, 19 }, + /* D25: SerialIo */ + Package () { 0x0019FFFF, 0, 0, 32 }, + Package () { 0x0019FFFF, 1, 0, 33 }, + Package () { 0x0019FFFF, 2, 0, 34 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, 0, 16 }, + Package () { 0x0016FFFF, 1, 0, 17 }, + Package () { 0x0016FFFF, 2, 0, 18 }, + Package () { 0x0016FFFF, 3, 0, 19 }, + /* D21: SerialIo */ + Package () { 0x0015FFFF, 0, 0, 16 }, + Package () { 0x0015FFFF, 1, 0, 17 }, + Package () { 0x0015FFFF, 2, 0, 18 }, + Package () { 0x0015FFFF, 3, 0, 19 }, + /* D20: xHCI, OTG, Thermal, Camera */ + Package () { 0x0014FFFF, 0, 0, 16 }, + Package () { 0x0014FFFF, 1, 0, 17 }, + Package () { 0x0014FFFF, 2, 0, 18 }, + Package () { 0x0014FFFF, 3, 0, 19 }, + /* D19: Integrated Sensor Hub */ + Package () { 0x0013FFFF, 0, 0, 20 }, + /* P.E.G. Root Port D1F0 */ + Package () { 0x0001FFFF, 0, 0, 16 }, + Package () { 0x0001FFFF, 1, 0, 17 }, + Package () { 0x0001FFFF, 2, 0, 18 }, + Package () { 0x0001FFFF, 3, 0, 19 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, 0, 16 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, 0, 16 }, + /* SA SkyCam Device */ + Package () { 0x0005FFFF, 0, 0, 16 }, + /* SA GMM Device */ + Package () { 0x0008FFFF, 0, 0, 16 }, +}) + +Name (PICN, Package () { + /* D31: cAVS, SMBus, GbE, Nothpeak */ + Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D29: PCI Express Port 9-16 */ + Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D28: PCI Express Port 1-8 */ + Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D27: PCI Express Port 17-20 */ + Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D23 */ + Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* D22: CSME (HECI, IDE-R, KT redirection */ + Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* D20: xHCI, OTG, Thermal, Camera */ + Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* P.E.G. Root Port D1F0 */ + Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 }, + Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 }, + Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 }, + Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 }, + /* SA IGFX Device */ + Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA Thermal Device */ + Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA Skycam Device */ + Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 }, + /* SA GMM Device */ + Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 }, +}) + +Method (_PRT) { If (PICM) { - Return (Package() { - /* PCI Bridge */ - /* D31: cAVS, SMBus, GbE, Nothpeak */ - Package(){0x001FFFFF, 0, 0, 16 }, - Package(){0x001FFFFF, 1, 0, 17 }, - Package(){0x001FFFFF, 2, 0, 18 }, - Package(){0x001FFFFF, 3, 0, 19 }, - /* D30: SerialIo and SCS */ - Package(){0x001EFFFF, 0, 0, 20 }, - Package(){0x001EFFFF, 1, 0, 21 }, - Package(){0x001EFFFF, 2, 0, 22 }, - Package(){0x001EFFFF, 3, 0, 23 }, - /* D29: PCI Express Port 9-16 */ - Package(){0x001DFFFF, 0, 0, 16 }, - Package(){0x001DFFFF, 1, 0, 17 }, - Package(){0x001DFFFF, 2, 0, 18 }, - Package(){0x001DFFFF, 3, 0, 19 }, - /* D28: PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, 16 }, - Package(){0x001CFFFF, 1, 0, 17 }, - Package(){0x001CFFFF, 2, 0, 18 }, - Package(){0x001CFFFF, 3, 0, 19 }, - /* D27: PCI Express Port 17-20 */ - Package(){0x001BFFFF, 0, 0, 16 }, - Package(){0x001BFFFF, 1, 0, 17 }, - Package(){0x001BFFFF, 2, 0, 18 }, - Package(){0x001BFFFF, 3, 0, 19 }, - /* D25: SerialIo */ - Package(){0x0019FFFF, 0, 0, 32 }, - Package(){0x0019FFFF, 1, 0, 33 }, - Package(){0x0019FFFF, 2, 0, 34 }, - /* D22: CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, 16 }, - Package(){0x0016FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 2, 0, 18 }, - Package(){0x0016FFFF, 3, 0, 19 }, - /* D21: SerialIo */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, - /* D20: xHCI, OTG, - * Thermal Subsystem, Camera IO Host Controller - */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, - /* D19: Integrated Sensor Hub */ - Package(){0x0013FFFF, 0, 0, 20 }, - - /* Host Bridge */ - /* P.E.G. Root Port D1F0 */ - Package(){0x0001FFFF, 0, 0, 16 }, - Package(){0x0001FFFF, 1, 0, 17 }, - Package(){0x0001FFFF, 2, 0, 18 }, - Package(){0x0001FFFF, 3, 0, 19 }, - /* P.E.G. Root Port D1F1 */ - /* P.E.G. Root Port D1F2 */ - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, 16 }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* SA SkyCam Device */ - Package(){0x0005FFFF, 0, 0, 16 }, - /* SA GMM Device */ - Package(){0x0008FFFF, 0, 0, 16 }, - }) + Return (^PICP) } Else { - Return (Package() { - /* D31 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LNKD, 0 }, - /* D29 */ - Package() { 0x001dffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LNKD, 0 }, - /* D28 */ - Package() { 0x001cffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LNKD, 0 }, - /* D27 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x001bffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x001bffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x001bffff, 3, \_SB.PCI0.LNKD, 0 }, - /* D23 */ - Package() { 0x0017ffff, 0, \_SB.PCI0.LNKA, 0 }, - /* D22 */ - Package() { 0x0016ffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0016ffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0016ffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0016ffff, 3, \_SB.PCI0.LNKD, 0 }, - /* D20 */ - Package() { 0x0014ffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0014ffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0014ffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0014ffff, 3, \_SB.PCI0.LNKD, 0 }, - /* Host bridge */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LNKA, 0 }, - Package() { 0x0001ffff, 1, \_SB.PCI0.LNKB, 0 }, - Package() { 0x0001ffff, 2, \_SB.PCI0.LNKC, 0 }, - Package() { 0x0001ffff, 3, \_SB.PCI0.LNKD, 0 }, - /* SA IGFX Device */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LNKA, 0 }, - /* SA Thermal Device */ - Package() { 0x0004ffff, 0, \_SB.PCI0.LNKA, 0 }, - /* SA Skycam Device */ - Package() { 0x0005ffff, 0, \_SB.PCI0.LNKA, 0 }, - /* SA GMM Device */ - Package() { 0x0008ffff, 0, \_SB.PCI0.LNKA, 0 }, - }) + Return (^PICN) } } - diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index b8fec94..9c9fc17 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -24,121 +24,73 @@ #define BASE_32GB 0x800000000 #define SIZE_16GB 0x400000000 -Name (_HID, EISAID ("PNP0A08")) // PCIe -Name (_CID, EISAID ("PNP0A03")) // PCI +Name (_HID, EISAID ("PNP0A08")) /* PCIe */ +Name (_CID, EISAID ("PNP0A03")) /* PCI */ Name (_ADR, 0) Name (_BBN, 0) Device (MCHC) { - Name (_ADR, 0x00000000) // 0:0.0 + Name (_ADR, 0x00000000) OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset(0x40), // EPBAR (0:0:0:40) - EPEN, 1, // Enable - , 11, - EPBR, 20, // EPBAR [31:12] - - Offset(0x48), // MCHBAR (0:0:0:48) - MHEN, 1, // Enable - , 14, - MHBR, 17, // MCHBAR [31:15] - - Offset(0x54), // DEVEN (0:0:0:54) - D0EN, 1, // DEV0 Enable - D1F2, 1, // DEV1 FUN2 Enable - D1F1, 1, // DEV1 FUN1 Enable - D1F0, 1, // DEV1 FUN0 Enable - - Offset(0x60), // PCIEXBAR (0:0:0:60) - PXEN, 1, // Enable - PXSZ, 2, // PCI Express Size - , 23, - PXBR, 6, // PCI Express BAR [31:26] - - Offset(0x68), // DMIBAR (0:0:0:68) - DIEN, 1, // Enable - , 11, - DIBR, 20, // DMIBAR [31:12] - - Offset (0x70), // ME Base Address + Offset(0x40), /* EPBAR (0:0:0:40) */ + EPEN, 1, /* Enable */ + , 11, + EPBR, 20, /* EPBAR [31:12] */ + + Offset(0x48), /* MCHBAR (0:0:0:48) */ + MHEN, 1, /* Enable */ + , 14, + MHBR, 17, /* MCHBAR [31:15] */ + + Offset(0x60), /* PCIEXBAR (0:0:0:60) */ + PXEN, 1, /* Enable */ + PXSZ, 2, /* PCI Express Size */ + , 23, + PXBR, 6, /* PCI Express BAR [31:26] */ + + Offset(0x68), /* DMIBAR (0:0:0:68) */ + DIEN, 1, /* Enable */ + , 11, + DIBR, 20, /* DMIBAR [31:12] */ + + Offset (0x70), /* ME Base Address */ MEBA, 64, - Offset(0x80), // PAM0 Register (0:0:0:80) - PMLK, 1, // PAM Lock bit. - , 3, - PM0H, 2, // PAM 0, High Nibble - , 2, - - Offset(0x81), // PAM1 Register (0:0:0:81) - PM1L, 2, // PAM1, Low Nibble - , 2, - PM1H, 2, // PAM1, High Nibble - , 2, - - Offset(0x82), // PAM2 Register (0:0:0:82) - PM2L, 2, // PAM2, Low Nibble - , 2, - PM2H, 2, // PAM2, High Nibble - , 2, - - Offset(0x83), // PAM3 Register (0:0:0:83) - PM3L, 2, // PAM3, Low Nibble - , 2, - PM3H, 2, // PAM3, High Nibble - , 2, - - Offset(0x84), // PAM4 Register (0:0:0:84) - PM4L, 2, // PAM4, Low Nibble - , 2, - PM4H, 2, // PAM4, High Nibble - , 2, - - Offset(0x85), // PAM5 Register (0:0:0:85) - PM5L, 2, // PAM5, Low Nibble - , 2, - PM5H, 2, // PAM5, High Nibble - , 2, - - Offset(0x86), // PAM6 Register (0:0:0:86) - PM6L, 2, // PAM6, Low Nibble - , 2, - PM6H, 2, // PAM6, High Nibble - , 2, - - Offset (0xa0), // Top of Used Memory + Offset (0xa0), /* Top of Used Memory */ TOM, 64, - Offset (0xa8), // Top of Upper Used Memory + Offset (0xa8), /* Top of Upper Used Memory */ TUUD, 64, - Offset (0xbc), // Top of Low Used Memory + Offset (0xbc), /* Top of Low Used Memory */ TLUD, 32, } } -// Current Resource Settings - Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() + Name (MCRS, ResourceTemplate () { /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) /* VGA memory (0xa0000-0xbffff) */ @@ -278,13 +230,10 @@ Method (_CRS, 0, Serialized) Store (^MCHC.TUUD, Local0) - If (LLessEqual (Local0, BASE_32GB)) - { + If (LLessEqual (Local0, BASE_32GB)) { Store (BASE_32GB, MMIN) Store (SIZE_16GB, MLEN) - } - else - { + } Else { Store (0, MMIN) Store (0, MLEN) } @@ -300,50 +249,45 @@ Name (PC_L, 0) /* to store PCIe BAR Length */ Name (DM_B, 0) /* to store DMI BAR */ /* Get MCH BAR */ -Method (GMHB,0,Serialized) +Method (GMHB, 0, Serialized) { - if (LEqual (MH_B,0)) - { + If (LEqual (MH_B, 0)) { ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) } Return (MH_B) } /* Get EP BAR */ -Method (GEPB,0,Serialized) +Method (GEPB, 0, Serialized) { - if (LEqual (EP_B,0)) - { + If (LEqual (EP_B, 0)) { ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) } Return (EP_B) } /* Get PCIe BAR */ -Method (GPCB,0,Serialized) +Method (GPCB, 0, Serialized) { - if (LEqual (PC_B,0)) - { + If (LEqual (PC_B, 0)) { ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) } Return (PC_B) } /* Get PCIe Length */ -Method (GPCL,0,Serialized) +Method (GPCL, 0, Serialized) { - if (LEqual (PC_L,0)) - { + If (LEqual (PC_L, 0)) { ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) } Return (PC_L) } /* Get DMI BAR */ -Method (GDMB,0,Serialized) +Method (GDMB, 0, Serialized) { - if (LEqual (DM_B,0)) - { + If (LEqual (DM_B, 0)) { ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) } Return (DM_B) @@ -352,10 +296,10 @@ Method (GDMB,0,Serialized) /* PCI Device Resource Consumption */ Device (PDRC) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (BUF0,ResourceTemplate() + Name (BUF0, ResourceTemplate () { /* MCH BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.48h @@ -398,8 +342,8 @@ Device (PDRC) /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) - /* Reserve HPET address decode range */ - Memory32Fixed (ReadWrite, 0, 0, HPET) + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) /* Debug Base Address * Base Address for ACPI debug output memory buffer @@ -407,28 +351,22 @@ Device (PDRC) Memory32Fixed (ReadWrite, 0, 0, DBAD) }) - // Current Resource Settings Method (_CRS, 0, Serialized) { CreateDwordField (BUF0, ^MCHB._BAS, MBR0) - Store (\_SB.PCI0.GMHB(), MBR0) + Store (\_SB.PCI0.GMHB (), MBR0) CreateDwordField (BUF0, ^DMIB._BAS, DBR0) - Store (\_SB.PCI0.GDMB(), DBR0) + Store (\_SB.PCI0.GDMB (), DBR0) CreateDwordField (BUF0, ^EGPB._BAS, EBR0) - Store (\_SB.PCI0.GEPB(), EBR0) + Store (\_SB.PCI0.GEPB (), EBR0) CreateDwordField (BUF0, ^PCIX._BAS, XBR0) - Store (\_SB.PCI0.GPCB(), XBR0) + Store (\_SB.PCI0.GPCB (), XBR0) CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) - Store (\_SB.PCI0.GPCL(), XSZ0) - - CreateDwordField (BUF0, ^HPET._BAS, HBAS) - CreateDwordField (BUF0, ^HPET._LEN, HLEN) - Store (0xfed00000, HBAS) - Store (0x400, HLEN) + Store (\_SB.PCI0.GPCL (), XSZ0) Return (BUF0) }

1 0

New patch to review for coreboot: skylake: ACPI: Clean up GPIO controller
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11538 -gerrit commit c679e9bbd542318dd588cded1988fced69091a63 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 17:15:00 2015 -0700 skylake: ACPI: Clean up GPIO controller Switch the GPIO controller to use the PCR functions that are defined in pcr.asl. Have the default memory regions declare a size of zero and be fixed up in the _CRS in order to fix compile issues on some versions of iasl. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ic82fcb00285aeb2515e24001ef69a882c3df1417 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: be24d9ccd9db62ca694f3a67436af25a73f59c5a Original-Change-Id: I13acd891427f467e289d5671add5617befef4380 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295951 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/gpio.asl | 64 ++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 7c2efa6..fed25c3 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -18,54 +18,44 @@ * Foundation, Inc. */ - -/* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */ -Method (PCRR, 2, Serialized) -{ - Add (ShiftLeft (Arg0, PCR_PORTID_SHIFT), Arg1, Local0) - Add (PCH_PCR_BASE_ADDRESS, Local0, Local0) - OperationRegion (PCR0, SystemMemory, Local0, 0x4) - - Field(PCR0, DWordAcc, Lock, Preserve) - { - Offset(0x00), - DAT0, 32 - } - Return (DAT0) -} - Device (GPIO) { - /* GPIO Controller */ Name (_HID, "INT344B") Name (_UID, 1) + Name (_DDN, "GPIO Controller") Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R0) - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R1) - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R3) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _R4) - { - GPIO_IRQ14, - } + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { 0 } }) - Method (_CRS, 0, NotSerialized) /* _CRS: Current Resource Settings */ + Method (_CRS, 0, NotSerialized) { - CreateDWordField (^RBUF, ^_R0._BAS, COM0) - CreateDWordField (^RBUF, ^_R1._BAS, COM1) - CreateDWordField (^RBUF, ^_R3._BAS, COM3) - CreateDWordField (^RBUF, ^_R4._INT, IRQN) + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) - Store (Add (PCH_PCR_BASE_ADDRESS, - ShiftLeft (PID_GPIOCOM0, PCR_PORTID_SHIFT)), COM0) - Store (Add (PCH_PCR_BASE_ADDRESS, - ShiftLeft (PID_GPIOCOM1, PCR_PORTID_SHIFT)), COM1) - Store (Add (PCH_PCR_BASE_ADDRESS, - ShiftLeft (PID_GPIOCOM3, PCR_PORTID_SHIFT)), COM3) - Store (And (PCRR (PID_GPIOCOM0, MISCCFG_OFFSET), - GPIO_DRIVER_IRQ_ROUTE_MASK), Local0) + CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) + And (^^PCRR (PID_GPIOCOM0, MISCCFG_OFFSET), + GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { Store (GPIO_IRQ14, IRQN)

1 0

New patch to review for coreboot: skylake: ACPI: Clean up and fix XHCI ACPI Device
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11537 -gerrit commit d86a0ea1774a5d9c67ce970ef8ad031aa6f94be5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 17:09:02 2015 -0700 skylake: ACPI: Clean up and fix XHCI ACPI Device - Remove the old workarounds for XHCI from broadwell - Add PMC device to expose bits needed for XHCI workarounds - Implement the new workarounds for XHCI, the first will set a bit in the XHCI MMIO and the second will send a message to the PMC if a bit is set indicating the workaround is available. - Clean up the HS/SS port defines and remove unnecessary methods to determine the port count since we only support SPT-LP. BUG=chrome-os-partner:44622,chrome-os-partner:44518 BRANCH=none TEST=build and boot on glados, verify that D0 and D3 can be made to work (by disabling unused USB and the misbehaving camera) Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88 Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295950 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/pch.asl | 3 + src/soc/intel/skylake/acpi/pmc.asl | 45 +++++ src/soc/intel/skylake/acpi/xhci.asl | 369 ++++++++++++------------------------ 3 files changed, 165 insertions(+), 252 deletions(-) diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index f2c1a16..951b97a 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -40,6 +40,9 @@ /* PCR Access */ #include "pcr.asl" +/* PMC 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl" diff --git a/src/soc/intel/skylake/acpi/pmc.asl b/src/soc/intel/skylake/acpi/pmc.asl new file mode 100644 index 0000000..2d826f6 --- /dev/null +++ b/src/soc/intel/skylake/acpi/pmc.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device (PMC) +{ + Name (_ADR, 0x001f0002) + Name (_DDN, "Power Management Controller") + + OperationRegion (PMCP, PCI_Config, 0x00, 0x100) + Field (PMCP, AnyAcc, NoLock, Preserve) + { + Offset (0x48), + , 12, + PWRM, 20, /* PWRMBASE */ + } + + OperationRegion (PMCM, SystemMemory, ShiftLeft (PWRM, 12), 0x3f) + Field (PMCM, DWordAcc, NoLock, Preserve) + { + Offset (0x1c), /* PCH_PM_STS */ + , 24, + PMFS, 1, /* PMC_MSG_FULL_STS */ + Offset (0x20), + MPMC, 32, /* MTPMC */ + Offset (0x24), /* PCH_PM_STS2 */ + , 20, + UWAB, 1, /* USB2 Workaround Available */ + } +} diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index f0ee414..5e49087 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -25,297 +25,162 @@ Device (XHCI) { Name (_ADR, 0x00140000) - Name (PLSD, 5) /* Port Link State - RxDetect */ - Name (PLSP, 7) /* Port Link State - Polling */ + Name (_PRW, Package () { GPE0_PME_B0, 3 }) + + Method (_DSW, 3) + { + Store (Arg0, PMEE) + } + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S4D, 3) /* D3 supported in S4 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + Name (_S4W, 3) /* D3 can wake system from S4 */ OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { Offset (0x0), - DVID, 16, + DVID, 16, /* VENDORID */ Offset (0x10), , 16, XMEM, 16, /* MEM_BASE */ Offset (0x74), - D0D3, 2, + D0D3, 2, /* POWERSTATE */ , 6, PMEE, 1, /* PME_EN */ , 6, PMES, 1, /* PME_STS */ - Offset (0xA8), - , 13, - MW13, 1, - MW14, 1, - , 17, - Offset (0xb0), - , 13, - MB13, 1, - MB14, 1, - , 17, - Offset (0xd0), - PR2, 32, /* USB2PR */ - PR2M, 32, /* USB2PRM */ - PR3, 32, /* USB3PR */ - PR3M, 32, /* USB3PRM */ } - Method (USRA,0){ - Return(11) + OperationRegion (XREG, SystemMemory, + Add (ShiftLeft (XMEM, 16), 0x8000), 0x200) + Field (XREG, DWordAcc, Lock, Preserve) + { + Offset (0x1c4), /* USB2PMCTRL */ + , 2, + UPSW, 2, /* U2PSUSPGP */ } - Method (SSPA,0){ - Return (13) + Method (_PSC, 0, Serialized) + { + Return (^D0D3) } - /* Clear status bits */ - Method (LPCL, 0, Serialized) + Method (_PS0, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) - Field (XREG, DWordAcc, Lock, Preserve) - { - Offset (0x510), /* PORTSCNUSB3[0]*/ - PSC0, 32, - Offset (0x520), /* PORTSCNUSB3[1]*/ - PSC1, 32, - Offset (0x530), /* PORTSCNUSB3[2]*/ - PSC2, 32, - Offset (0x540), /* PORTSCNUSB3[3]*/ - PSC3, 32, + If (LEqual (^DVID, 0xFFFF)) { + Return + } + If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + Return } - /* Port Enabled/Disabled (Bit 1)*/ - Name (PEDB, ShiftLeft (1, 1)) - - /* Change Status (Bits 23:17)*/ - Name (CHST, ShiftLeft (0x7f, 17)) - - /* Port 0 */ - And (PSC0, Not (PEDB), Local0) - Or (Local0, CHST, PSC0) - - /* Port 1 */ - And (PSC1, Not (PEDB), Local0) - Or (Local0, CHST, PSC1) - - /* Port 2 */ - And (PSC2, Not (PEDB), Local0) - Or (Local0, CHST, PSC2) + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, ^D0D3) + Store (^D0D3, Local0) + } - /* Port 3 */ - And (PSC3, Not (PEDB), Local0) - Or (Local0, CHST, PSC3) + /* Disable USB2 PHY SUS Well Power Gating */ + Store (Zero, ^UPSW) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC disable power gating */ + Store (1, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } + } } - Method (LPS0, 0, Serialized) + Method (_PS3, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) - Field (XREG, DWordAcc, Lock, Preserve) - { - Offset (0x510), // PORTSCNUSB3 - , 5, - PLS1, 4, // [8:5] Port Link State - PPR1, 1, // [9] Port Power - , 7, - CSC1, 1, // [17] Connect Status Change - , 1, - WRC1, 1, // [19] Warm Port Reset Change - , 11, - WPR1, 1, // [31] Warm Port Reset - Offset (0x520), // PORTSCNUSB3 - , 5, - PLS2, 4, // [8:5] Port Link State - PPR2, 1, // [9] Port Power - , 7, - CSC2, 1, // [17] Connect Status Change - , 1, - WRC2, 1, // [19] Warm Port Reset Change - , 11, - WPR2, 1, // [31] Warm Port Reset - Offset (0x530), // PORTSCNUSB3 - , 5, - PLS3, 4, // [8:5] Port Link State - PPR3, 1, // [9] Port Power - , 7, - CSC3, 1, // [17] Connect Status Change - , 1, - WRC3, 1, // [19] Warm Port Reset Change - , 11, - WPR3, 1, // [31] Warm Port Reset - Offset (0x540), // PORTSCNUSB3 - , 5, - PLS4, 4, // [8:5] Port Link State - PPR4, 1, // [9] Port Power - , 7, - CSC4, 1, // [17] Connect Status Change - , 1, - WRC4, 1, // [19] Warm Port Reset Change - , 11, - WPR4, 1, // [31] Warm Port Reset + If (LEqual (^DVID, 0xFFFF)) { + Return } - - /* Wait for all powered ports to finish polling*/ - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), - LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), - LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), - LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) - { - If (LEqual (Local0, 0)) { - Break - } - Decrement (Local0) - Stall (10) + If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + Return } - /* For each USB3 Port:*/ - /* If port is disconnected (PLS=5 PP=1 CSC=0)*/ - /* 1) Issue warm reset (WPR=1)*/ - /* 2) Poll for warm reset complete (WRC=0)*/ - /* 3) Write 1 to port status to clear*/ + /* Clear PME Status */ + Store (1, ^PMES) - /* Local# indicate if port is reset*/ - Store (0, Local1) - Store (0, Local2) - Store (0, Local3) - Store (0, Local4) + /* Enable PME */ + Store (1, ^PMEE) - If (LAnd (LEqual (PLS1, PLSD), - LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) /* Issue warm reset*/ - Store (1, Local1) - } - If (LAnd (LEqual (PLS2, PLSD), - LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) /* Issue warm reset*/ - Store (1, Local2) - } - If (LAnd (LEqual (PLS3, PLSD), - LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) /* Issue warm reset*/ - Store (1, Local3) - } - If (LAnd (LEqual (PLS4, PLSD), - LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) /* Issue warm reset*/ - Store (1, Local4) + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, ^D0D3) + Store (^D0D3, Local0) } - /* Poll for warm reset complete on all ports that were reset*/ - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), - LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), - LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), - LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) - { - If (LEqual (Local0, 0)) { - Break + /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ + Store (3, ^UPSW) + + /* Now put device in D3 */ + Store (3, ^D0D3) + Store (^D0D3, Local0) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + * This code assumes XDCI is disabled, if it is enabled + * then this must also check if it is in D3 state too. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC enable power gating */ + Store (3, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) } - Decrement (Local0) - Stall (10) } - - /* Clear status bits in all ports */ - LPCL () } - Method (_PSC, 0, NotSerialized) - { - Return (^D0D3) - } - - Method (_PS0, 0, Serialized) + /* Root Hub for Skylake-LP PCH */ + Device (RHUB) { - } - Method (_PS3, 0, Serialized) - { - } + Name (_ADR, Zero) - Name (_PRW, Package(){ 0x6d, 3 }) + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } - /* Leave USB ports on for to allow Wake from USB */ + /* USBr */ + Device (USR1) { Name (_ADR, 11) } + Device (USR2) { Name (_ADR, 12) } - Method (_S3D,0) /* Highest D State in S3 State*/ - { - Return (3) - } - - Method (_S4D,0) /* Highest D State in S4 State*/ - { - Return (3) - } - Device (HS01) - { - Name(_ADR, 0x01) - } - Device (HS02) - { - Name(_ADR, 0x02) - } - Device (HS03) - { - Name(_ADR, 0x03) - } - Device (HS04) - { - Name(_ADR, 0x04) - } - Device (HS05) - { - Name(_ADR, 0x05) - } - Device (HS06) - { - Name(_ADR, 0x06) - } - Device (HS07) - { - Name(_ADR, 0x07) - } - Device (HS08) - { - Name(_ADR, 0x08) - } - Device (HS09) - { - Name(_ADR, 0x09) - } - Device (HS10) - { - Name(_ADR, 0x10) - } - Device (USR1) - { - Method(_ADR) { Return (Add(USRA(),0)) } - } - Device (USR2) - { - Method(_ADR) { Return (Add(USRA(),1)) } - } - Device (SS01) - { - Method(_ADR) { Return (Add(SSPA(),0)) } - } - Device (SS02) - { - Method(_ADR) { Return (Add(SSPA(),1)) } - } - Device (SS03) - { - Method(_ADR) { Return (Add(SSPA(),2)) } - } - Device (SS04) - { - Method(_ADR) { Return (Add(SSPA(),3)) } - } - Device (SS05) - { - Method(_ADR) { Return (Add(SSPA(),4)) } - } - Device (SS06) - { - Method(_ADR) { Return (Add(SSPA(),5)) } + /* USB3 */ + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } + Device (SS05) { Name (_ADR, 17) } + Device (SS06) { Name (_ADR, 18) } } } -

1 0

New patch to review for coreboot: skylake: ACPI: Remove SerialIO ACPI mode code
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11536 -gerrit commit 73c4a6dd93d45298cd436aa45bd2dfc1db4cfa26 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:58:23 2015 -0700 skylake: ACPI: Remove SerialIO ACPI mode code Skylake moves back to having SerialIO devices be enumerated as PCI devices instead of putting them all in ACPI mode. There is currently no code that populates the device_nvs fields so all the ACPI code to support that is dead. Additionally because it contains _PS0/_PS3 methods that causes the kernel to not use the standard PCIe PME handlers and results in confusing messages at boot about not being able to transition to a non-D0 state from D3. BUG=chrome-os-partner:44622 BRANCH=none TEST=build and boot on glados and ensure I2C devices work Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295909 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/device_nvs.asl | 60 ---- src/soc/intel/skylake/acpi/globalnvs.asl | 3 - src/soc/intel/skylake/acpi/serialio.asl | 552 +----------------------------- src/soc/intel/skylake/include/soc/nvs.h | 5 +- 4 files changed, 20 insertions(+), 600 deletions(-) diff --git a/src/soc/intel/skylake/acpi/device_nvs.asl b/src/soc/intel/skylake/acpi/device_nvs.asl deleted file mode 100644 index e84d25a..0000000 --- a/src/soc/intel/skylake/acpi/device_nvs.asl +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Device Enabled in ACPI Mode */ - -S0EN, 8, // I2C0 Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // SPI0 Enable -S7EN, 8, // SPI1 Enable -S8EN, 8, // UART0 Enable -S9EN, 8, // UART1 Enable -SAEN, 8, // UART2 Enable - -/* BAR 0 */ -S0B0, 32, // I2C0 BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // SPI0 BAR0 -S7B0, 32, // SPI1 BAR0 -S8B0, 32, // UART0 BAR0 -S9B0, 32, // UART1 BAR0 -SAB0, 32, // UART2 BAR0 - -/* BAR 1 */ -S0B1, 32, // I2C0 BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // SPI0 BAR1 -S7B1, 32, // SPI1 BAR1 -S8B1, 32, // UART0 BAR1 -S9B1, 32, // UART1 BAR1 -SAB1, 32, // UART2 BAR1 - diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index b41fa42..0208198 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -69,9 +69,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - /* Device specific */ - Offset (0x1000), - #include "device_nvs.asl" } /* Set flag to enable USB charging in S5 */ diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index d3dca7f..da38891 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -18,603 +18,89 @@ * Foundation, Inc. */ -// Intel Serial IO Devices in ACPI Mode - -/* Serial IO Device BAR0 and BAR1 is 4KB */ -#define SIO_BAR_LEN 0x1000 - -/* Put SerialIO device in D0 state */ -/* Arg0 - BAR1 of device */ -/* Arg1 - Set if device is in ACPI mode */ - -Method (LPD0, 2, Serialized) -{ - /* PCI mode devices will be handled by OS PCI bus driver */ - If (LEqual (Arg1, 0)) { - Return - } - - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - - And (SPCS, 0xFFFFFFFC, SPCS) - /* Read back after writing */ - Store (SPCS, Local0) -} - -/* Put SerialIO device in D3 state */ -/* Arg0 - BAR1 of device */ -/* Arg1 - Set if device is in ACPI mode */ - -Method (LPD3, 2, Serialized) -{ - /* PCI mode devices will be handled by OS PCI bus driver */ - If (LEqual (Arg1, 0)) { - Return - } - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) - Field (SPRT, DWordAcc, NoLock, Preserve) - { - SPCS, 32 - } - Or (SPCS, 0x3, SPCS) - Store (SPCS, Local0) // Read back after writing -} - -/* Serial IO Resource Consumption for BAR1 */ -Device (SIOR) -{ - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 5) - Method(ADDB,3,Serialized) { - Name (BUFF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0x00000000, 0x1000, BUF) - }) - CreateDWordField(BUFF,BUF._BAS,ADDR) - CreateDWordField(BUFF,BUF._LEN,LENG) - Store(ResourceTemplate(){}, Local0) - //Return (RBUF) - } -} +/* Intel Serial IO Devices */ Device (I2C0) { - /* Serial IO I2C0 Controller */ - Name (_HID,"INT3442") - Name (_UID, 1) Name (_ADR, 0x00150000) + Name (_DDN, "Serial IO I2C Controller 0") + Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_I2C0_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S0B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S0B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S0EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S0B1, \S0EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S0B1, \S0EN) - } - } Device (I2C1) { - /* Serial IO I2C1 Controller */ - Name (_HID,"INT3443") - Name (_UID, 1) Name (_ADR, 0x00150001) + Name (_DDN, "Serial IO I2C Controller 1") + Name (SSCN, Package () { 528, 640, 30 }) Name (FMCN, Package () { 128, 160, 30 }) Name (FPCN, Package () { 48, 64, 30}) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_I2C1_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S1B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S1B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S1EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S1B1, \S1EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S1B1, \S1EN) - } } - Device (I2C2) { - /* Serial IO I2C1 Controller */ - Name (_HID,"INT3444") - Name (_UID, 1) Name (_ADR, 0x00150002) + Name (_DDN, "Serial IO I2C Controller 2") + Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_I2C2_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S2B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S2B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S2EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S2B1, \S2EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S2B1, \S2EN) - } } Device (I2C3) { - /* Serial IO I2C3 Controller */ - Name (_HID,"INT3445") - Name (_UID, 1) Name (_ADR, 0x00150003) + Name (_DDN, "Serial IO I2C Controller 3") + Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_I2C3_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S3B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S3B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S3EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S3B1, \S3EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S3B1, \S3EN) - } - } Device (I2C4) { - /* Serial IO I2C4 Controller */ - Name (_HID,"INT3446") - Name (_UID, 1) Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO I2C Controller 4") + Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_I2C4_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS*/ - If (LNotEqual (\S4B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S4B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S4EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S4B1, \S4EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S4B1, \S4EN) - } } Device (I2C5) { - /* Serial IO I2C1 Controller */ - Name (_HID,"INT3447") - Name (_UID, 1) Name (_ADR, 0x00190002) + Name (_DDN, "Serial IO I2C Controller 5") + Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_I2C5_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (0xFE02A000, B0AD) - Store (SIO_BAR_LEN, B0LN) - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S5EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S5B1, \S5EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S5B1, \S5EN) - } } Device (SPI0) { - /* Serial IO PI0 Controller */ - Name (_HID,"INT3440") - Name (_UID, 1) Name (_ADR, 0x001E0002) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_SPI0_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S6B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S6B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S6EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S6B1, \S6EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S6B1, \S6EN) - } + Name (_DDN, "Serial IO SPI Controller 0") } Device (SPI1) { - /* Serial IO SPI1 Controller */ - Name (_HID,"INT3441") - Name (_UID, 1) Name (_ADR, 0x001E0003) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_SPI1_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S7B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S7EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S7B1, \S7EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S7B1, \S7EN) - } + Name (_DDN, "Serial IO SPI Controller 1") } Device (UAR0) { - /* Serial IO UART0 Controller */ - Name (_HID,"INT3448") - Name (_UID, 1) Name (_ADR, 0x001E0000) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_UART0_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\S8B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S8B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S8EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S8B1, \S8EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S8B1, \S8EN) - } + Name (_DDN, "Serial IO UART Controller 0") } Device (UAR1) { - /* Serial IO UART1 Controller */ - Name (_HID,"INT3449") - Name (_UID, 1) Name (_ADR, 0x001E0001) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_UART1_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - // Update BAR0 address and length if set in NVS - If (LNotEqual (\S9B0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S9B0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\S9EN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\S9B1, \S9EN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\S9B1, \S9EN) - } + Name (_DDN, "Serial IO UART Controller 1") } Device (UAR2) { - /* Serial IO UART1 Controller */ - Name (_HID,"INT344A") - Name (_UID, 1) Name (_ADR, 0x00190000) - - /* BAR0 is assigned during PCI enumeration and saved into NVS */ - Name (RBUF, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { LPSS_UART2_IRQ } - }) - - Method (_CRS, 0, NotSerialized) - { - /* Update BAR0 address and length if set in NVS */ - If (LNotEqual (\SAB0, Zero)) { - CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) - CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\SAB0, B0AD) - Store (SIO_BAR_LEN, B0LN) - } - - Return (RBUF) - } - - Method (_STA, 0, NotSerialized) - { - If (LEqual (\SAEN, 0)) { - Return (0x0) - } Else { - Return (0xF) - } - } - - Method (_PS0, 0, Serialized) - { - ^^LPD0 (\SAB1, \SAEN) - } - - Method (_PS3, 0, Serialized) - { - ^^LPD3 (\SAB1, \SAEN) - } + Name (_DDN, "Serial IO UART Controller 2") } diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 2d8129b..c9fcb4e 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -24,7 +24,6 @@ #include <rules.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <soc/device_nvs.h> typedef struct { /* Miscellaneous */ @@ -61,12 +60,10 @@ typedef struct { /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; - - /* Device specific (0x1000) */ - device_nvs_t dev; } __attribute__((packed)) global_nvs_t; void acpi_create_gnvs(global_nvs_t *gnvs); + #if ENV_SMM /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void);

1 0

New patch to review for coreboot: skylake: ACPI: Move storage controllers to separate file
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11535 -gerrit commit b554ae8eedfea1c8c961391ea58522eeef253343 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:53:45 2015 -0700 skylake: ACPI: Move storage controllers to separate file Move the storage controller devices out of serialio.asl and into a new scs.asl file and implement the power gating workarounds for D0 and D3 transitions. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529 Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295908 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/pch.asl | 2 + src/soc/intel/skylake/acpi/scs.asl | 125 ++++++++++++++++++++++++++++++++ src/soc/intel/skylake/acpi/serialio.asl | 29 -------- 3 files changed, 127 insertions(+), 29 deletions(-) diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index c72a704..f2c1a16 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -46,6 +46,8 @@ /* SMBus 0:1f.3 */ #include "smbus.asl" +/* Storage Controllers */ +#include "scs.asl" /* USB XHCI 0:14.0 */ #include "xhci.asl" diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl new file mode 100644 index 0000000..4eb9683 --- /dev/null +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Intel Storage Controllers */ + +Device (EMMC) +{ + Name (_ADR, 0x001E0004) + Name (_DDN, "eMMC Controller") + + OperationRegion (EMCR, PCI_Config, 0x00, 0x100) + Field (EMCR, DWordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + D0D3, 2, /* POWERSTATE */ + Offset (0xa2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method (_PS0, 0, Serialized) + { + /* Disable Power Good */ + Store (0, ^PGEN) + + /* Clear bits 31, 6, 2, 0 */ + ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA) + Sleep (2) + + /* Set bits 31, 6, 2, 0 */ + ^^PCRO (PID_SCS, 0x600, 0x80000045) + + /* Set Power State to D0 */ + Store (0, ^D0D3) + Store (^D0D3, Local0) + } + + Method (_PS3, 0, Serialized) + { + /* Enable Power Good */ + Store (1, ^PGEN) + + /* Set Power State to D0 */ + Store (3, ^D0D3) + Store (^D0D3, Local0) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device (SDXC) +{ + Name (_ADR, 0x001E0006) + Name (_DDN, "SD Controller") + + OperationRegion (SDCR, PCI_Config, 0x00, 0x100) + Field (SDCR, DWordAcc, NoLock, Preserve) + { + Offset (0x84), /* PMECTRLSTATUS */ + D0D3, 2, /* POWERSTATE */ + Offset (0xa2), /* PG_CONFIG */ + , 2, + PGEN, 1, /* PG_ENABLE */ + } + + Method (_PS0, 0, Serialized) + { + /* Disable Power Good */ + Store (0, ^PGEN) + + /* Clear bits 8, 7, 2, 0 */ + ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) + Sleep (2) + + /* Set bits 31, 6, 2, 0 */ + ^^PCRO (PID_SCS, 0x600, 0x00000185) + + /* Set Power State to D0 */ + Store (0, ^D0D3) + Store (^D0D3, Local0) + } + + Method (_PS3, 0, Serialized) + { + /* Enable Power Good */ + Store (1, ^PGEN) + + /* Set Power State to D0 */ + Store (3, ^D0D3) + Store (^D0D3, Local0) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } +} diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index e57b937..d3dca7f 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -618,32 +618,3 @@ Device (UAR2) ^^LPD3 (\SAB1, \SAEN) } } - - -Device (PEMC) -{ - Name (_ADR, 0x001E0004) - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0x0, NotSerialized) - { - Return (0) - } - } -} - -/* SD controller */ -Device (PSDC) -{ - Name (_ADR, 0x001E0006) - Device (CARD) - { - Name (_ADR, 0x00000008) - Method (_RMV, 0x0, NotSerialized) - { - Return (1) - } - } -} -

1 0

New patch to review for coreboot: skylake: ACPI: Remove itss.asl and cleanup irqlinks.asl
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11534 -gerrit commit ded08000f5e8aa68491ef019193c7f43d726d51b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:48:11 2015 -0700 skylake: ACPI: Remove itss.asl and cleanup irqlinks.asl Move the itss.asl code that was exporting PIRQ routing control registers into irqlinks.asl and use the PCR access methods to find the appropriate address. At the same time clean up the code in irqlinks.asl to follow formatting rules. Also now that the GPIO code in itss.asl is unused the file can be removed. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I1af7d730542fd0e79b9f3db9f0796e7c701c59e6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 39a96063d01d00ab768db1c723f78b5af9ed6513 Original-Change-Id: Iafa03c276cb276ec8c00c24ed2dba48d0dc9612b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295907 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/irqlinks.asl | 337 +++++++++++++------------------- src/soc/intel/skylake/acpi/itss.asl | 96 --------- src/soc/intel/skylake/acpi/pch.asl | 1 - 3 files changed, 137 insertions(+), 297 deletions(-) diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index 1f6e623..b7a78f0 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -19,475 +19,412 @@ * Foundation, Inc. */ +/* PIRQ routing control is in PCR ITSS region */ +OperationRegion (ITSS, SystemMemory, + Add (PCRB (PID_ITSS), R_PCH_PCR_ITSS_PIRQA_ROUT), 8) +Field (ITSS, ByteAcc, NoLock, Preserve) +{ + PIRA, 8, /* PIRQA Routing Control */ + PIRB, 8, /* PIRQB Routing Control */ + PIRC, 8, /* PIRQC Routing Control */ + PIRD, 8, /* PIRQD Routing Control */ + PIRE, 8, /* PIRQE Routing Control */ + PIRF, 8, /* PIRQF Routing Control */ + PIRG, 8, /* PIRQG Routing Control */ + PIRH, 8, /* PIRQH Routing Control */ +} + +Name (IREN, 0x80) /* Interrupt Routing Enable */ +Name (IREM, 0x0f) /* Interrupt Routing Mask */ + Device (LNKA) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 1) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PARC, 0x80, \_SB.PARC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLA, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - - // Clear the WordField Store (Zero, IRQ0) - // Set the bit from PRTA - ShiftLeft (1, And (\_SB.PARC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0) Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PARC) + Decrement (Local0) + Store (Local0, ^^PIRA) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PARC, 0x80)) { + If (And (^^PIRA, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRA, ^^IREN, ^^PIRA) + } } Device (LNKB) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 2) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PBRC, 0x80, \_SB.PBRC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLB, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLB, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTB - ShiftLeft (1, And (\_SB.PBRC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0) - Return (RTLB) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PBRC) + Decrement (Local0) + Store (Local0, ^^PIRB) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PBRC, 0x80)) { + If (And (^^PIRB, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRB, ^^IREN, ^^PIRB) + } } Device (LNKC) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 3) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PCRC, 0x80, \_SB.PCRC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLC, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLC, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTC - ShiftLeft (1, And (\_SB.PCRC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0) - Return (RTLC) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PCRC) + Decrement (Local0) + Store (Local0, ^^PIRC) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PCRC, 0x80)) { + If (And (^^PIRC, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRC, ^^IREN, ^^PIRC) + } } Device (LNKD) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 4) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PDRC, 0x80, \_SB.PDRC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLD, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLD, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTD - ShiftLeft (1, And (\_SB.PDRC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0) - Return (RTLD) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PDRC) + Decrement (Local0) + Store (Local0, ^^PIRD) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PDRC, 0x80)) { + If (And (^^PIRD, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRD, ^^IREN, ^^PIRD) + } } Device (LNKE) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 5) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PERC, 0x80, \_SB.PERC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLE, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLE, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTE - ShiftLeft (1, And (\_SB.PERC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0) - Return (RTLE) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PERC) + Decrement (Local0) + Store (Local0, ^^PIRE) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PERC, 0x80)) { + If (And (^^PIRE, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRE, ^^IREN, ^^PIRE) + } } Device (LNKF) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 6) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PFRC, 0x80, \_SB.PFRC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLF, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLF, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTF - ShiftLeft (1, And (\_SB.PFRC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0) - Return (RTLF) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PFRC) + Decrement (Local0) + Store (Local0, ^^PIRF) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PFRC, 0x80)) { + If (And (^^PIRF, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRF, ^^IREN, ^^PIRF) + } } Device (LNKG) { - Name (_HID, EISAID("PNP0C0F")) + Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 7) - // Disable method - Method (_DIS, 0, Serialized) - { - Or (\_SB.PGRC, 0x80, \_SB.PGRC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLG, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLG, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTG - ShiftLeft (1, And (\_SB.PGRC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0) - Return (RTLG) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PGRC) + Decrement (Local0) + Store (Local0, ^^PIRG) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PGRC, 0x80)) { + If (And (^^PIRG, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } -} -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method Method (_DIS, 0, Serialized) { - Or (\_SB.PHRC, 0x80, \_SB.PHRC) + Or (^^PIRG, ^^IREN, ^^PIRG) } +} - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() +Device (LNKH) +{ + Name (_HID, EISAID ("PNP0C0F")) + Name (_UID, 1) + + Name (_PRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 10, 12, 14, 15 } }) - // Current Resource Settings for this link Method (_CRS, 0, Serialized) { - Name (RTLH, ResourceTemplate() + Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLH, 1, IRQ0) - - // Clear the WordField + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) - // Set the bit from PRTH - ShiftLeft (1, And (\_SB.PHRC, 0x0f), IRQ0) + /* Set the bit from PIRQ Routing Register */ + ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0) - Return (RTLH) + Return (RTLA) } - // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, \_SB.PHRC) + Decrement (Local0) + Store (Local0, ^^PIRH) } - // Status Method (_STA, 0, Serialized) { - If(And (\_SB.PHRC, 0x80)) { + If (And (^^PIRH, ^^IREN)) { Return (0x9) } Else { Return (0xb) } } -} + Method (_DIS, 0, Serialized) + { + Or (^^PIRH, ^^IREN, ^^PIRH) + } +} diff --git a/src/soc/intel/skylake/acpi/itss.asl b/src/soc/intel/skylake/acpi/itss.asl deleted file mode 100644 index 8ba9513..0000000 --- a/src/soc/intel/skylake/acpi/itss.asl +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is part of the coreboot project. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* ITSS */ -/* Define the needed ITSS registers used by ASL on Interrupt */ - -Scope (\_SB) -{ - OperationRegion (ITSS, SystemMemory, 0xfdc43100, 0x8) - Field (ITSS, ByteAcc, NoLock, Preserve) - { - PARC, 8, - PBRC, 8, - PCRC, 8, - PDRC, 8, - PERC, 8, - PFRC, 8, - PGRC, 8, - PHRC, 8, - } - - /* - * Pin# = group_pad# + group# * 24. - * For instance, GPP_A_6 would be pin#6, - * GPP_D_23 would be 23+(3*24), pin#95. - */ - Name (GPPG, Package (0x02) - { - Package (0x08) - { - 0x18, - 0x18, - 0x18, - 0x18, - 0x18, - 0x18, - 0x08, - 0x0C - }, - - Package (0x0A) - { - 0x18, - 0x18, - 0x18, - 0x18, - 0x0D, - 0x18, - 0x18, - 0x18, - 0x0B, - 0x0C - } - }) - - Method (GNMB, 1, Serialized) - { - Return (And (Arg0, 0xFFFF)) - } - - Method (GGRP, 1, Serialized) - { - ShiftRight (And (Arg0, 0x00FF0000), 0x10, Local0) - Return (Local0) - } - - /* Convert GPIO PAD name to GPIO number */ - Method (INUM, 1, NotSerialized) - { - Store (One, Local0) - Store (GNMB (Arg0), Local1) - Store (GGRP (Arg0), Local2) - Store (Zero, Local3) - - While (LLess (Local3, Local2)) - { - Add (DerefOf (Index (DerefOf (Index - (GPPG, Local0)), Local3)), - Local1, Local1) - Increment (Local3) - } - - Return (Add (0x18, Mod (Local1, 0x60))) - } -} diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 581efa0..c72a704 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -47,7 +47,6 @@ #include "smbus.asl" -#include "itss.asl" /* USB XHCI 0:14.0 */ #include "xhci.asl"

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New patch to review for coreboot: skylake: iomap: Remove unused RCBA region
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11533 -gerrit commit f5567159bdf275eba08a3b349ccca7a08a6bb3a1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:39:31 2015 -0700 skylake: iomap: Remove unused RCBA region Remove the now unused RCBA base and size from iomap.h and fix a trivial typo that doesn't seem to get used anywhere. BUG=chrome-os-partner:44622 BRANCH=none TEST=emege-glados coreboot Change-Id: If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ee7b1a8a75a9e9dc191c16ddc32b6a38acec398c Original-Change-Id: I0c49803d47105c3c55121caedaffaa249c4f0189 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295906 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/iomap.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 916719d..333906b 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -28,7 +28,7 @@ #define MCFG_BASE_SIZE 0x4000000 #define PCH_PCR_BASE_ADDRESS 0xfd000000 -#define PCH_BCR_BASE_SIZE 0x1000000 +#define PCH_PCR_BASE_SIZE 0x1000000 #define UART_DEBUG_BASE_ADDRESS 0xfe034000 #define UART_DEBUG_BASE_SIZE 0x1000 @@ -48,10 +48,6 @@ #define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000 -/* TODO: need to remove RCBA code after ASL clean up */ -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x4000 - #define HPET_BASE_ADDRESS 0xfed00000 #define PCH_PWRM_BASE_ADDRESS 0xfe000000

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New patch to review for coreboot: skylake: PCR: Add Port ID for SCS
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11532 -gerrit commit 36afa64e8c8573178c3c91d09a6250bf2c3184ef Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 27 16:35:06 2015 -0700 skylake: PCR: Add Port ID for SCS Add the PCR Port ID for the storage controllers and reformat to put the PCR PIDs in increasing order. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9 Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295905 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/pcr.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index c8a4425..bf3161b 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -78,9 +78,10 @@ #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE #define PID_GPIOCOM0 0xAF -#define PID_LPC 0xC7 -#define PID_ITSS 0xC4 +#define PID_SCS 0xC0 #define PID_RTC 0xC3 +#define PID_ITSS 0xC4 +#define PID_LPC 0xC7 #define PID_SERIALIO 0xCB #define PID_DMI 0xEF

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coreboot-gerrit September 2015