coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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859 discussions

New patch to review for coreboot: kunimitsu: Modify DQ/DQS mapping
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11551 -gerrit commit bc8a9d1fa1e9431b2fa366419f2e5b78821295ef Author: Mike M Hsieh <mike.m.hsieh(a)intel.com> Date: Fri Aug 28 09:27:22 2015 +0800 kunimitsu: Modify DQ/DQS mapping Modify DQ Byte Map and DQS Byte Swizzling to match up with design BUG=chrome-os-partner:44647 BRANCH=none TEST=System boot up and pass memory initialization Signed-off-by: Mike Hsieh <mike.m.hsieh(a)intel.com> Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78 Original-Reviewed-on: https://chromium-review.googlesource.com/295518 Original-Commit-Ready: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/pei_data.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index af9462f..00451bf 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -29,12 +29,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u8 dq_map[2][12] = { {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00}, - {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC , - 0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} }; - /* DQS CPU<>DRAM map for sklrvp board */ + {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , + 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} }; + /* DQS CPU<>DRAM map for kunimitsu board */ const u8 dqs_map[2][8] = { - {0, 1, 3, 2, 4, 5, 6, 7}, - {1, 0, 4, 5, 2, 3, 6, 7} }; + {0, 1, 3, 2, 6, 5, 4, 7}, + {2, 3, 0, 1, 6, 7, 4, 5} }; /* Rcomp resistor*/ const u16 RcompResistor[3] = {200, 81, 162 };

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New patch to review for coreboot: Skylake:Set DISB inside romstage after mrc init
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11550 -gerrit commit 91722e80f765821ac5b32e3a77f7f5554c424091 Author: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Date: Thu Aug 27 17:13:19 2015 +0530 Skylake:Set DISB inside romstage after mrc init Set DISB inside romstage right after successful mrc init such that any reset events afterwards can take fast boot path and in turn achieve better boot performance BRANCH=NONE BUG=chrome-os-partner:43637 TEST=Built for kunimitsu and tested DISB is set correctly and fast boot path is taken. Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61 Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00 Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295509 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma(a)intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/pmc.c | 2 -- src/soc/intel/skylake/romstage/romstage.c | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 2704956..fb09589 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -47,8 +47,6 @@ static const struct reg_script pch_pmc_misc_init_script[] = { DIS_SLP_X_STRCH_SUS_UP), /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), - /* Indicate DRAM init done for MRC */ - REG_PCI_OR32(GEN_PMCON_A, DISB), REG_SCRIPT_END }; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 91a496e..6c5d64a 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_def.h> #include <elog.h> #include <reset.h> @@ -37,6 +38,7 @@ #include <soc/pci_devs.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> +#include <soc/pmc.h> #include <soc/serialio.h> #include <soc/romstage.h> #include <soc/spi.h> @@ -405,3 +407,18 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); soc_display_upd_value("RMT", 1, old->RMT, new->RMT); } + +/* SOC initialization after RAM is enabled. */ +void soc_after_ram_init(struct romstage_params *params) +{ + /* Set the DISB as soon as possible after DRAM + * init and MRC cache is saved. + */ + u32 disb_val = 0; + device_t dev = PCH_DEV_PMC; + disb_val = pci_read_config32(dev, GEN_PMCON_A); + disb_val |= DISB; + /* Preserve bits which get cleared up if written 1 */ + disb_val &= ~(GBL_RST_STS | MS4V); + pci_write_config32(dev, GEN_PMCON_A, disb_val); +}

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New patch to review for coreboot: kunimitsu: Disable unused USB ports
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11549 -gerrit commit 8df84475b3b3a8c4d4471ece035b867078ce0fba Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Aug 28 17:48:11 2015 -0700 kunimitsu: Disable unused USB ports Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296036 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/devicetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 6d0e2f4..1c3cf67 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -15,6 +15,18 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" + register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */ + register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */ + register "PortUsb20Enable[2]" = "1" /* Bluetooth */ + register "PortUsb20Enable[4]" = "1" /* Type-A Port (card) */ + register "PortUsb20Enable[6]" = "1" /* Camera */ + register "PortUsb20Enable[8]" = "1" /* Type-A Port (board) */ + + register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */ + register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */ + register "PortUsb30Enable[2]" = "1" /* Type-A Port (card) */ + register "PortUsb30Enable[3]" = "1" /* Type-A Port (board) */ + register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" register "pirqc_routing" = "0x8b"

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New patch to review for coreboot: glados: Disable unused USB ports
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11548 -gerrit commit ea7d9f3ae48fc3d9b29bb3e4256591a773efc9e8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Aug 28 17:22:04 2015 -0700 glados: Disable unused USB ports Enable only the USB ports that are connected on-board or to an external port, all others will be disabled. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados, ensure expected USB ports still work Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163 Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296035 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/devicetree.cb | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 9bb065d..2c6d997 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -20,6 +20,18 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" + register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */ + register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */ + register "PortUsb20Enable[2]" = "1" /* Bluetooth */ + register "PortUsb20Enable[4]" = "1" /* Type-A Port 1 */ + register "PortUsb20Enable[6]" = "1" /* Camera */ + register "PortUsb20Enable[8]" = "1" /* Type-A Port 2 */ + + register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */ + register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */ + register "PortUsb30Enable[2]" = "1" /* Type-A Port 1 */ + register "PortUsb30Enable[3]" = "1" /* Type-A Port 2 */ + # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" register "PcieRpEnable[4]" = "1"

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New patch to review for coreboot: skylake: Apply USB2 and USB3 port enable/disable settings
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11547 -gerrit commit 7a5a9e8da19b2e3f624dfe641355aadf51e12d1b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Aug 28 17:21:07 2015 -0700 skylake: Apply USB2 and USB3 port enable/disable settings The USB port enable/disable settings were never getting applied to the UPD configuration and so were not getting used by FSP. BUG=chrome-os-partner:44662 BRANCH=none TEST=build and boot on glados Change-Id: I13d4eb901215308de4b59083339832d29ce0049f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4 Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296034 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8bd62b4..2c49883 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -26,6 +26,7 @@ #include <fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <string.h> static void pci_domain_set_resources(device_t dev) { @@ -69,18 +70,15 @@ struct chip_operations soc_intel_skylake_ops = { /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - const struct device *dev; - const struct soc_intel_skylake_config *config; - int i; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = dev->chip_info; - /* Set the parameters for SiliconInit */ - dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; - - for (i = 0; i < PchSerialIoIndexMax; i++) - params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + memcpy(params->PortUsb20Enable, config->PortUsb20Enable, + sizeof(params->PortUsb20Enable)); + memcpy(params->PortUsb30Enable, config->PortUsb30Enable, + sizeof(params->PortUsb30Enable)); params->SataSalpSupport = config->SataSalpSupport; params->SataPortsEnable[0] = config->SataPortsEnable[0];

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New patch to review for coreboot: braswell: acpi: Allow DPTF thresholds to be defined at board-level
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11546 -gerrit commit 142849ef81a8268b5cd8bf11acfb7ef5b0926029 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Aug 25 18:03:31 2015 -0700 braswell: acpi: Allow DPTF thresholds to be defined at board-level Similar to Skylake, allow braswell mainboards to override the default DPTF thresholds. BUG=chrome-os-partner:43884 TEST=Build for Strago BRANCH=Strago Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17 Original-Reviewed-on: https://chromium-review.googlesource.com/296033 Original-Commit-Ready: Shawn N <shawnn(a)chromium.org> Original-Tested-by: Shawn N <shawnn(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/braswell/acpi/cpu.asl | 11 ------ src/soc/intel/braswell/acpi/dptf/cpu.asl | 63 +++++++++++++++++++++++++------- 2 files changed, 49 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index 0ae51f2..c9cb83b 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -18,17 +18,6 @@ * Foundation, Inc. */ -/* CPU */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 - /* These devices are created at runtime */ External (\_PR.CP00, DeviceObj) External (\_PR.CP01, DeviceObj) diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 018144c..3e51c29 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,3 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif + External (\_PR.CP00._TSS, MethodObj) External (\_PR.CP00._TPC, MethodObj) External (\_PR.CP00._PTC, PkgObj) @@ -127,52 +175,39 @@ Device (B0DB) { Return (\_SB.MPPC) } -#ifdef DPTF_CPU_CRITICAL + Method (_CRT) { Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL)) } -#endif -#ifdef DPTF_CPU_PASSIVE Method (_PSV) { Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE)) } -#endif -#ifdef DPTF_CPU_ACTIVE_AC0 Method (_AC0) { Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0)) } -#endif -#ifdef DPTF_CPU_ACTIVE_AC1 Method (_AC1) { Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1)) } -#endif -#ifdef DPTF_CPU_ACTIVE_AC2 Method (_AC2) { Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2)) } -#endif -#ifdef DPTF_CPU_ACTIVE_AC3 Method (_AC3) { Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3)) } -#endif -#ifdef DPTF_CPU_ACTIVE_AC4 Method (_AC4) { Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4)) } -#endif }

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New patch to review for coreboot: FSP: Pass FSP image base address to find_fsp
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11545 -gerrit commit fc61046cfaaf5ec36bb89ae3a068207b876285cd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Aug 26 14:58:29 2015 -0700 FSP: Pass FSP image base address to find_fsp Add a parameter to find_fsp which is the image base address. Adjust the fake stack in cache_as_ram.inc to pass in the read-only FSP image base address. In fsp_notify, pass in the read-only FSP image base address when the FSP header pointer is NULL. In find_fsp, validate the FSP binary image starting from the specified image base address. BRANCH=none BUG=None TEST=Build and run on Skylake Change-Id: Iac43c8aac8491390479af551765b514ca919928a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95 Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295593 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 + src/drivers/intel/fsp1_1/fsp_util.c | 8 ++++---- src/drivers/intel/fsp1_1/fsp_util.h | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6af30ce..d4df67b 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -342,6 +342,7 @@ halt3: .align 4 fake_fsp_stack: .long find_fsp_ret + .long CONFIG_FSP_LOC /* FSP base address */ CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index bce4337..f699569 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -25,7 +25,7 @@ #include <timestamp.h> /* Locate the FSP binary in the coreboot filesystem */ -FSP_INFO_HEADER *find_fsp(void) +FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address) { union { EFI_FFS_FILE_HEADER *ffh; @@ -40,7 +40,7 @@ FSP_INFO_HEADER *find_fsp(void) for (;;) { /* Get the FSP binary base address in CBFS */ - fsp_ptr.u8 = (u8 *)CONFIG_FSP_LOC; + fsp_ptr.u32 = fsp_base_address; /* Check the FV signature, _FVH */ if (fsp_ptr.fvh->Signature != 0x4856465F) { @@ -74,7 +74,7 @@ FSP_INFO_HEADER *find_fsp(void) fsp_ptr.u8 += sizeof(EFI_RAW_SECTION); /* Verify that the FSP base address.*/ - if (fsp_ptr.fih->ImageBase != CONFIG_FSP_LOC) { + if (fsp_ptr.fih->ImageBase != fsp_base_address) { fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH; break; } @@ -143,7 +143,7 @@ void fsp_notify(u32 phase) fsp_header_ptr = fsp_get_fih(); if (fsp_header_ptr == NULL) { - fsp_header_ptr = (void *)find_fsp(); + fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ post_code(0x4F); diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h index 8f6f77a..51ecb98 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.h +++ b/src/drivers/intel/fsp1_1/fsp_util.h @@ -42,7 +42,7 @@ #include <soc/chipset_fsp_util.h> /* find_fsp() should only be called from assembly code. */ -FSP_INFO_HEADER *find_fsp(void); +FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address); /* Set FSP's runtime information. */ void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list); /* Use a new FSP_INFO_HEADER at runtime. */

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New patch to review for coreboot: skylake: Remove dead code
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11544 -gerrit commit c139a3472626ae654862b32ad6c75f275696412e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Aug 20 19:04:31 2015 -0700 skylake: Remove dead code Remove dead code not called by any part of coreboot. BRANCH=none BUG=None TEST=Build and run on skylake Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294953 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/romstage.h | 1 - src/soc/intel/skylake/romstage/spi.c | 20 -------------------- 2 files changed, 21 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index f030301..d1c846b 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -33,7 +33,6 @@ void intel_early_me_status(void); void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_spi_read_wpsr(u8 *sr); void mainboard_fill_spd_data(struct pei_data *pei_data); diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index 2194d21..41a144b 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -21,26 +21,6 @@ #include <soc/flash_controller.h> #include <soc/romstage.h> -int early_spi_read(u32 offset, u32 size, u8 *buffer) -{ - u32 current = 0; - - spi_init(); - while (size > 0) { - u8 count = (size < 64) ? size : 64; - /* sending NULL for spiflash struct parameter since we are not - * calling HWSEQ read() call via Probe. - */ - if (pch_hwseq_read(NULL, offset + current, count, - buffer + current) != 0) - return -1; - size -= count; - current += count; - } - - return 0; -} - /* * Minimal set of commands to read WPSR from SPI. * Returns 0 on success, < 0 on failure.

1 0

New patch to review for coreboot: skylake: refactor flash_controller code
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11543 -gerrit commit b1972b7daaf5714100b10211b0c04db064730b0b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 27 14:30:22 2015 -0500 skylake: refactor flash_controller code There's no need to add any typedefs nor guard code with ENV_ROMSTAGE. The linker will garbage collect unused functions. Additionally there were a few errors in the code including the operation mask wasn't wide enough to clear out old operations as well as component size decoding was incorrect. The big difference in the code flow is that the operation setup is now in one place. The stopwatch API is also used in order to not open code time calculations. BUG=chrome-os-partner:42115 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted. Suspended and resumed. event log is populated for all. Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489 Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295980 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/flash_controller.c | 349 +++++++++------------ .../intel/skylake/include/soc/flash_controller.h | 17 +- 2 files changed, 158 insertions(+), 208 deletions(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index dac5df8..26d8a1f 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -24,73 +24,135 @@ #include <stdlib.h> #include <string.h> #include <bootstate.h> -#include <delay.h> -#include <device/pci_ids.h> #include <spi_flash.h> -#include <spi-generic.h> +#include <timer.h> #include <soc/flash_controller.h> #include <soc/pci_devs.h> #include <soc/spi.h> -#if !(ENV_ROMSTAGE) -typedef struct spi_slave pch_spi_slave; -static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi); -#endif +static inline uint16_t spi_read_hsfs(pch_spi_regs * const regs) +{ + return readw_(&regs->hsfs); +} -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +static inline void spi_clear_status(pch_spi_regs * const regs) { - pch_spi_regs *spi_bar; + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(spi_read_hsfs(regs), &regs->hsfs); +} - spi_bar = get_spi_bar(); - return min(sizeof(spi_bar->fdata), buf_len); +static inline uint16_t spi_read_hsfc(pch_spi_regs * const regs) +{ + return readw_(&regs->hsfc); } -#if !(ENV_ROMSTAGE) -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +static inline uint32_t spi_read_faddr(pch_spi_regs * const regs) { - pch_spi_slave *slave = malloc(sizeof(*slave)); + return readl_(&regs->faddr) & SPIBAR_FADDR_MASK; +} - if (!slave) { - printk(BIOS_DEBUG, "PCH SPI: Bad allocation\n"); - return NULL; +/* + * Polls for Cycle Done Status, Flash Cycle Error + * Resets all error flags in HSFS. + * Returns 0 if the cycle completes successfully without errors within + * timeout, 1 on errors. + */ +static int wait_for_completion(pch_spi_regs * const regs, int timeout_ms, + size_t len) +{ + uint16_t hsfs; + uint16_t hsfc; + uint32_t addr; + struct stopwatch sw; + int timeout = 0; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + while (!(timeout = stopwatch_expired(&sw))) { + hsfs = spi_read_hsfs(regs); + + if ((hsfs & (HSFS_FDONE | HSFS_FCERR))) + break; } - memset(slave, 0, sizeof(*slave)); + if (timeout) { + addr = spi_read_faddr(regs); + hsfc = spi_read_hsfc(regs); + printk(BIOS_ERR, "%ld ms Transaction timeout between offset " + "0x%08x and 0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", + stopwatch_duration_msecs(&sw), addr, addr + len - 1, + addr, len - 1, hsfc, hsfs); + return 1; + } - slave->bus = bus; - slave->cs = cs; - slave->force_programmer_specific = 1; - slave->programmer_specific_probe = spi_flash_hwseq_probe; + if (hsfs & HSFS_FCERR) { + addr = spi_read_faddr(regs); + hsfc = spi_read_hsfc(regs); + printk(BIOS_ERR, "Transaction error between offset 0x%08x and " + "0x%08x (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", + addr, addr + len - 1, addr, len - 1, + hsfc, hsfs); + return 1; + } - return slave; + return 0; } -#endif -static u32 spi_get_flash_size(pch_spi_regs *spi_bar) +/* Start operation returning 0 on success, non-zero on error or timeout. */ +static int spi_do_operation(int op, size_t offset, size_t size, int timeout_ms) +{ + uint16_t hsfc; + pch_spi_regs * const regs = get_spi_bar(); + + /* Clear status prior to operation. */ + spi_clear_status(regs); + + /* Set the FADDR */ + writel_(offset & SPIBAR_FADDR_MASK, &regs->faddr); + + hsfc = readw_(&regs->hsfc); + /* Clear then set the correct op. */ + hsfc &= ~HSFC_FCYCLE_MASK; + hsfc |= op; + /* Set the size field */ + hsfc &= ~HSFC_FDBC_MASK; + /* Check for sizes of confirming operations. */ + if (size && size <= SPI_FDATA_BYTES) + hsfc |= ((size - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC_MASK; + /* start operation */ + hsfc |= HSFC_FGO; + writew_(hsfc, &regs->hsfc); + + return wait_for_completion(regs, timeout_ms, size); +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(SPI_FDATA_BYTES, buf_len); +} + +static size_t spi_get_flash_size(pch_spi_regs *spi_bar) { uint32_t flcomp; - u32 size; + size_t size; writel_(SPIBAR_FDOC_COMPONENT, &spi_bar->fdoc); flcomp = readl_(&spi_bar->fdod); - printk(BIOS_DEBUG, "flcomp = %x\n", flcomp); switch (flcomp & FLCOMP_C0DEN_MASK) { case FLCOMP_C0DEN_8MB: - size = 0x100000; + size = 8*MiB; break; case FLCOMP_C0DEN_16MB: - size = 0x1000000; + size = 16*MiB; break; case FLCOMP_C0DEN_32MB: - size = 0x10000000; + size = 32*MiB; break; default: - size = 0x1000000; + size = 16*MiB; } - printk(BIOS_DEBUG, "flash size 0x%x bytes\n", size); - return size; } @@ -105,16 +167,6 @@ void spi_init(void) { uint8_t bios_cntl; device_t dev = PCH_DEV_SPI; - pch_spi_regs *spi_bar; - uint16_t hsfs; - - /* Root Complex Register Block */ - spi_bar = get_spi_bar(); - hsfs = readw_(&spi_bar->hsfs); - if (hsfs & HSFS_FDV) { - /* Select Flash Descriptor Section Index to 1 */ - writel_(SPIBAR_FDOC_FDSI_1, &spi_bar->fdoc); - } /* Disable the BIOS write protect so write commands are allowed. */ pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl); @@ -134,64 +186,11 @@ void spi_release_bus(struct spi_slave *slave) /* Handled by PCH automatically. */ } -static void pch_hwseq_set_addr(uint32_t addr, pch_spi_regs *spi_bar) -{ - uint32_t addr_old = readl_(&spi_bar->faddr) & ~SPIBAR_FADDR_MASK; - writel_((addr & SPIBAR_FADDR_MASK) | addr_old, &spi_bar->faddr); -} - -/* - * Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. - * Resets all error flags in HSFS. - * Returns 0 if the cycle completes successfully without errors within - * timeout us, 1 on errors. - */ -static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len, pch_spi_regs *spi_bar) -{ - uint16_t hsfs; - uint32_t addr; - - timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&spi_bar->hsfs)) & - (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { - udelay(8); - } - writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); - - if (!timeout) { - uint16_t hsfc; - addr = readl_(&spi_bar->faddr) & SPIBAR_FADDR_MASK; - hsfc = readw_(&spi_bar->hsfc); - printk(BIOS_ERR, "Transaction timeout between offset 0x%08x \ - and 0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", - addr, addr + len - 1, addr, len - 1, - hsfc, hsfs); - return 1; - } - - if (hsfs & HSFS_FCERR) { - uint16_t hsfc; - addr = readl_(&spi_bar->faddr) & SPIBAR_FADDR_MASK; - hsfc = readw_(&spi_bar->hsfc); - printk(BIOS_ERR, "Transaction error between offset 0x%08x and \ - 0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", - addr, addr + len - 1, addr, len - 1, - hsfc, hsfs); - return 1; - } - return 0; -} - int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; int ret; - uint16_t hsfc; - uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ - pch_spi_regs *spi_bar; - spi_bar = get_spi_bar(); erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); @@ -209,27 +208,13 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) end = start + len; while (offset < end) { - /* - * Make sure FDONE, FCERR, AEL are - * cleared by writing 1 to them. - */ - writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); - - pch_hwseq_set_addr(offset, spi_bar); - - offset += erase_size; - - hsfc = readw_(&spi_bar->hsfc); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ - hsfc |= HSFC_FCYCLE; /* set erase operation */ - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &spi_bar->hsfc); - if (pch_hwseq_wait_for_cycle_complete(timeout, len, spi_bar)) { - printk(BIOS_ERR, "SF: Erase failed at %x\n", - offset - erase_size); + if (spi_do_operation(HSFC_FCYCLE_4KE, offset, 0, 5000)) { + printk(BIOS_ERR, "SF: Erase failed at %x\n", offset); ret = -1; goto out; } + + offset += erase_size; } printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", @@ -240,11 +225,14 @@ out: return ret; } -static void pch_read_data(uint8_t *data, int len, pch_spi_regs *spi_bar) +static void pch_read_data(uint8_t *data, int len) { int i; + pch_spi_regs *spi_bar; uint32_t temp32 = 0; + spi_bar = get_spi_bar(); + for (i = 0; i < len; i++) { if ((i % 4) == 0) temp32 = readl_((uint8_t *)spi_bar->fdata + i); @@ -252,16 +240,12 @@ static void pch_read_data(uint8_t *data, int len, pch_spi_regs *spi_bar) data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } } -int pch_hwseq_read(struct spi_flash *flash, - u32 addr, size_t len, void *buf) + +int pch_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) { - uint16_t hsfc; - uint16_t timeout = 100 * 60; /* 6 mili secs timeout */ uint8_t block_len; - pch_spi_regs *spi_bar; - spi_bar = get_spi_bar(); - if (addr + len > spi_get_flash_size(spi_bar)) { + if (addr + len > spi_get_flash_size(get_spi_bar())) { printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", (unsigned) addr, @@ -269,26 +253,18 @@ int pch_hwseq_read(struct spi_flash *flash, return -1; } - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); - while (len > 0) { - block_len = min(len, sizeof(spi_bar->fdata)); + const int timeout_ms = 6; + + block_len = min(len, SPI_FDATA_BYTES); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; - pch_hwseq_set_addr(addr, spi_bar); - hsfc = readw_(&spi_bar->hsfc); - hsfc &= ~HSFC_FCYCLE; /* set read operation */ - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &spi_bar->hsfc); - - if (pch_hwseq_wait_for_cycle_complete - (timeout, block_len, spi_bar)) + + if (spi_do_operation(HSFC_FCYCLE_RD, addr, block_len, + timeout_ms)) return -1; - pch_read_data(buf, block_len, spi_bar); + + pch_read_data(buf, block_len); addr += block_len; buf += block_len; len -= block_len; @@ -329,8 +305,6 @@ static void pch_fill_data(const uint8_t *data, int len) int pch_hwseq_write(struct spi_flash *flash, u32 addr, size_t len, const void *buf) { - uint16_t hsfc; - uint16_t timeout = 100 * 60; /* 6 mili secs timeout */ uint8_t block_len; uint32_t start = addr; pch_spi_regs *spi_bar; @@ -344,28 +318,16 @@ int pch_hwseq_write(struct spi_flash *flash, return -1; } - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); - while (len > 0) { + const int timeout_ms = 6; + block_len = min(len, sizeof(spi_bar->fdata)); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; - pch_hwseq_set_addr(addr, spi_bar); - pch_fill_data(buf, block_len); - hsfc = readw_(&spi_bar->hsfc); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ - hsfc |= HSFC_FCYCLE_WR; /* set write operation */ - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &spi_bar->hsfc); - - if (pch_hwseq_wait_for_cycle_complete - (timeout, block_len, spi_bar)) { + if (spi_do_operation(HSFC_FCYCLE_WR, addr, block_len, + timeout_ms)) { printk(BIOS_ERR, "SF: write failure at %x\n", addr); return -1; } @@ -380,44 +342,21 @@ int pch_hwseq_write(struct spi_flash *flash, int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg) { - uint16_t hsfc; - uint16_t timeout = 100 * 60; /* 6 mili secs timeout */ - uint8_t block_len = SPI_READ_STATUS_LENGTH; - pch_spi_regs *spi_bar; + size_t block_len = SPI_READ_STATUS_LENGTH; + const int timeout_ms = 6; - spi_bar = get_spi_bar(); - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); - - hsfc = readw_(&spi_bar->hsfc); - hsfc &= ~HSFC_FCYCLE; /* set read operation */ - /* read status register */ - hsfc |= HSFC_FCYCLE_RS; - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &spi_bar->hsfc); - - if (pch_hwseq_wait_for_cycle_complete(timeout, - block_len, spi_bar)) + if (spi_do_operation(HSFC_FCYCLE_RS, 0, block_len, timeout_ms)) return -1; - pch_read_data(reg, block_len, spi_bar); - /* clear read status register */ - writew_(readw_(&spi_bar->hsfc) & - ~HSFC_FCYCLE_RS, &spi_bar->hsfc); + + pch_read_data(reg, block_len); return 0; } -#if !(ENV_ROMSTAGE) static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) { - struct spi_flash *flash = NULL; - u32 berase; - pch_spi_regs *spi_bar; + struct spi_flash *flash; - spi_bar = get_spi_bar(); flash = malloc(sizeof(*flash)); if (!flash) { printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); @@ -431,31 +370,33 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) flash->erase = pch_hwseq_erase; flash->read = pch_hwseq_read; flash->status = pch_hwseq_read_status; - pch_hwseq_set_addr(0, spi_bar); - berase = ((readw_(&spi_bar->hsfs)) >> SPIBAR_HSFS_BERASE_OFFSET) & - SPIBAR_HSFS_BERASE_MASK; + /* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */ + flash->sector_size = 4*KiB; - switch (berase) { - case 0: - flash->sector_size = 256; - break; - case 1: - flash->sector_size = 4096; - break; - case 2: - flash->sector_size = 8192; - break; - case 3: - flash->sector_size = 65536; - break; + flash->size = spi_get_flash_size(get_spi_bar()); + + return flash; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + printk(BIOS_DEBUG, "PCH SPI: Bad allocation\n"); + return NULL; } - flash->size = spi_get_flash_size(spi_bar); + memset(slave, 0, sizeof(*slave)); + + slave->bus = bus; + slave->cs = cs; + slave->force_programmer_specific = 1; + slave->programmer_specific_probe = spi_flash_hwseq_probe; - return flash; + return slave; } -#endif #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h index 25cbce9..91693e3 100644 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -121,22 +121,31 @@ static void writel_(u32 b, void *addr) pci_write_config32(dev, reg, val) #endif /* ENV_SMM */ -#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_MASK (0xf << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_RD (0x0 << HSFC_FCYCLE_SHIFT) #define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_4KE (0x3 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_64KE (0x4 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_SFDP (0x5 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_JEDECID (0x6 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_WS (0x7 << HSFC_FCYCLE_SHIFT) #define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT) -#define HSFC_FDBC (0x3f << HSFC_FDBC_SHIFT) +#define HSFC_FDBC_MASK (0x3f << HSFC_FDBC_SHIFT) #define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */ #define WPSR_MASK_SRP0_BIT 0x80 +#define SPI_FDATA_REGS 16 +#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t)) + typedef struct pch_spi_regs { uint32_t bfpr; uint16_t hsfs; uint16_t hsfc; uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; + uint32_t dlock; + uint32_t fdata[SPI_FDATA_REGS]; uint32_t frap; uint32_t freg[6]; uint32_t _reserved1[6];

1 0

New patch to review for coreboot: skylake: move flash_controller.h to the proper place
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11542 -gerrit commit 11c79f01c018c3bef32b2b6770f7f07e725551b4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 27 14:28:35 2015 -0500 skylake: move flash_controller.h to the proper place I missed this in code review. This should be under the soc directory. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built glados. Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295239 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/flash_controller.c | 2 +- src/soc/intel/skylake/include/flash_controller.h | 176 --------------------- .../intel/skylake/include/soc/flash_controller.h | 176 +++++++++++++++++++++ src/soc/intel/skylake/romstage/spi.c | 2 +- 4 files changed, 178 insertions(+), 178 deletions(-) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index a243eb1..dac5df8 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -26,9 +26,9 @@ #include <bootstate.h> #include <delay.h> #include <device/pci_ids.h> -#include <flash_controller.h> #include <spi_flash.h> #include <spi-generic.h> +#include <soc/flash_controller.h> #include <soc/pci_devs.h> #include <soc/spi.h> diff --git a/src/soc/intel/skylake/include/flash_controller.h b/src/soc/intel/skylake/include/flash_controller.h deleted file mode 100644 index c79d265..0000000 --- a/src/soc/intel/skylake/include/flash_controller.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., - */ - -#ifndef _FLASH_CONTROLLER__H_ -#define _FLASH_CONTROLLER__H_ - -#include <rules.h> -#include <arch/io.h> -#include <console/console.h> -#include <spi_flash.h> - -int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len); -int pch_hwseq_write(struct spi_flash *flash, - u32 addr, size_t len, const void *buf); - -int pch_hwseq_read(struct spi_flash *flash, - u32 addr, size_t len, void *buf); -int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg); - - -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) -static u8 readb_(const void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -#if ENV_SMM -#define pci_read_config_byte(dev, reg, targ)\ - (*(targ) = pci_read_config8(dev, reg)) -#define pci_read_config_word(dev, reg, targ)\ - (*(targ) = pci_read_config16(dev, reg)) -#define pci_read_config_dword(dev, reg, targ)\ - (*(targ) = pci_read_config32(dev, reg)) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !ENV_SMM */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - (*(targ) = pci_read_config8(dev, reg)) -#define pci_read_config_word(dev, reg, targ)\ - (*(targ) = pci_read_config16(dev, reg)) -#define pci_read_config_dword(dev, reg, targ)\ - (*(targ) = pci_read_config32(dev, reg)) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* ENV_SMM */ - -#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT) -#define HSFC_FDBC (0x3f << HSFC_FDBC_SHIFT) - -#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */ - -#define WPSR_MASK_SRP0_BIT 0x80 - -typedef struct pch_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[6]; - uint32_t _reserved1[6]; - uint32_t pr[5]; - uint32_t gpr0; - uint32_t _reserved2; - uint32_t _reserved3; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __attribute__((packed)) pch_spi_regs; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_FDV = 0x4000, -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_SHIFT = 8, -}; -#endif /* _FLASH_CONTROLLER__H_ */ diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h new file mode 100644 index 0000000..25cbce9 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + */ + +#ifndef _SOC_FLASH_CONTROLLER__H_ +#define _SOC_FLASH_CONTROLLER__H_ + +#include <rules.h> +#include <arch/io.h> +#include <console/console.h> +#include <spi_flash.h> + +int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len); +int pch_hwseq_write(struct spi_flash *flash, + u32 addr, size_t len, const void *buf); + +int pch_hwseq_read(struct spi_flash *flash, + u32 addr, size_t len, void *buf); +int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg); + + +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +static u8 readb_(const void *addr) +{ + u8 v = read8(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = read16(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = read32(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, void *addr) +{ + write8(addr, b); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, void *addr) +{ + write16(addr, b); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, void *addr) +{ + write32(addr, b); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ + +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) + +#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ + +#if ENV_SMM +#define pci_read_config_byte(dev, reg, targ)\ + (*(targ) = pci_read_config8(dev, reg)) +#define pci_read_config_word(dev, reg, targ)\ + (*(targ) = pci_read_config16(dev, reg)) +#define pci_read_config_dword(dev, reg, targ)\ + (*(targ) = pci_read_config32(dev, reg)) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#else /* !ENV_SMM */ +#include <device/device.h> +#include <device/pci.h> +#define pci_read_config_byte(dev, reg, targ)\ + (*(targ) = pci_read_config8(dev, reg)) +#define pci_read_config_word(dev, reg, targ)\ + (*(targ) = pci_read_config16(dev, reg)) +#define pci_read_config_dword(dev, reg, targ)\ + (*(targ) = pci_read_config32(dev, reg)) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* ENV_SMM */ + +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT) +#define HSFC_FDBC (0x3f << HSFC_FDBC_SHIFT) + +#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */ + +#define WPSR_MASK_SRP0_BIT 0x80 + +typedef struct pch_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[6]; + uint32_t _reserved1[6]; + uint32_t pr[5]; + uint32_t gpr0; + uint32_t _reserved2; + uint32_t _reserved3; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) pch_spi_regs; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_FDV = 0x4000, +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_SHIFT = 8, +}; +#endif /* _SOC_FLASH_CONTROLLER__H_ */ diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index be6db41..2194d21 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -18,7 +18,7 @@ * Foundation, Inc. */ -#include <flash_controller.h> +#include <soc/flash_controller.h> #include <soc/romstage.h> int early_spi_read(u32 offset, u32 size, u8 *buffer)

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coreboot-gerrit September 2015