07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11561
-gerrit
commit a507eef6fc0da1b7eed8d42d8a43c8cb257c2954
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Sep 3 16:04:09 2015 -0700
glados: Clean up devicetree.cb
Clean up the PCI device list comments to be consistent between
the skylake mainboards.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0080ab21db006365f34995db06480dae68ac547d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d
Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297338
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/glados/devicetree.cb | 138 ++++++++++++++++--------------
1 file changed, 72 insertions(+), 66 deletions(-)
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 40fe2b1..1d2f8bf 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -5,32 +5,40 @@ chip soc/intel/skylake
register "deep_s5_enable" = "1"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
- # Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoPci, \
- }"
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
- register "PortUsb20Enable[0]" = "1" # Type-C Port 1
- register "PortUsb20Enable[1]" = "1" # Type-C Port 2
- register "PortUsb20Enable[2]" = "1" # Bluetooth
- register "PortUsb20Enable[4]" = "1" # Type-A Port 1
- register "PortUsb20Enable[6]" = "1" # Camera
- register "PortUsb20Enable[8]" = "1" # Type-A Port 2
+ # EC host command range is in 0x800-0x8ff
+ register "gen1_dec" = "0x00fc0801"
- register "PortUsb30Enable[0]" = "1" # Type-C Port 1
- register "PortUsb30Enable[1]" = "1" # Type-C Port 2
- register "PortUsb30Enable[2]" = "1" # Type-A Port 1
- register "PortUsb30Enable[3]" = "1" # Type-A Port 2
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "XdciEnable" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "2"
+ register "IshEnable" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
@@ -42,35 +50,32 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
- register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "0"
- register "ScsSdCardEnabled" = "1"
- register "EnableAzalia" = "1"
- register "DspEnable" = "1"
- register "IoBufferOwnership" = "3"
-
- register "ProbelessTrace" = "0"
- register "EnableTraceHub" = "0"
- register "EnableLan" = "0"
- register "EnableSata" = "0"
- register "IshEnable" = "0"
- register "XdciEnable" = "0"
- register "SsicPortEnable" = "0"
- register "SmbusEnable" = "1"
- register "Cio2Enable" = "0"
- register "PttSwitch" = "0"
- register "SkipExtGfxScan" = "1"
+ register "PortUsb20Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb20Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb20Enable[2]" = "1" # Bluetooth
+ register "PortUsb20Enable[4]" = "1" # Type-A Port 1
+ register "PortUsb20Enable[6]" = "1" # Camera
+ register "PortUsb20Enable[8]" = "1" # Type-A Port 2
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_C"
- register "gpe0_dw1" = "GPP_D"
- register "gpe0_dw2" = "GPP_E"
+ register "PortUsb30Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb30Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb30Enable[2]" = "1" # Type-A Port 1
+ register "PortUsb30Enable[3]" = "1" # Type-A Port 2
- # Embedded Controller host command window
- register "gen1_dec" = "0x00fc0801"
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoPci, \
+ }"
device cpu_cluster 0 on
device lapic 0 on end
@@ -78,22 +83,22 @@ chip soc/intel/skylake
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB 3.0 xHCI Controller
- device pci 14.1 off end # USB Device Controller (OTG)
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C Controller #0
- device pci 15.1 on end # I2C Controller #1
- device pci 15.2 off end # I2C Controller #2
- device pci 15.3 off end # I2C Controller #3
- device pci 16.0 off end # Management Engine Interface 1
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Intel MEI #3
- device pci 17.0 on end # SATA Controller
- device pci 19.0 on end # UART Controller #2
- device pci 19.1 off end # I2C Controller #5
- device pci 19.2 on end # I2C Controller #4
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end # I2C #4
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
@@ -111,6 +116,7 @@ chip soc/intel/skylake
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard
device pci 1f.0 on
chip drivers/pc80/tpm
@@ -121,9 +127,9 @@ chip soc/intel/skylake
end
end # LPC Interface
device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel High Definition Audio
- device pci 1f.4 on end # SMBus Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE Controller
+ device pci 1f.6 off end # GbE
end
end
1
0
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11560
-gerrit
commit ea87bb296013551d8d1b7aea1b2a61f2f658334f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Sep 3 16:03:09 2015 -0700
sklrvp: Clean up devicetree.cb
Remove devicetree.cb settings that do not apply to skylake so
they can be removed from chip.h and clean up the pci device
comments and add missing devices.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot
Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509
Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297337
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/intel/sklrvp/devicetree.cb | 59 ++++++++++++--------------------
1 file changed, 21 insertions(+), 38 deletions(-)
diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb
index cfa51a8..deb3ed7 100644
--- a/src/mainboard/intel/sklrvp/devicetree.cb
+++ b/src/mainboard/intel/sklrvp/devicetree.cb
@@ -45,24 +45,6 @@ chip soc/intel/skylake
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
- # EC range is 0x800-0x9ff
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x00fc0901"
-
- # GPE configuration
- register "gpe0_en_1" = "0x00000000"
- # EC_SCI is GPIO36
- register "gpe0_en_2" = "0x00000010"
- register "gpe0_en_3" = "0x00000000"
- register "gpe0_en_4" = "0x00000000"
-
- # Force enable ASPM for PCIe Port 3
- register "pcie_port_force_aspm" = "0x04"
- register "pcie_port_coalesce" = "1"
-
- # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
- register "icc_clock_disable" = "0x013b0000"
-
# Enable S0ix
register "s0ix_enable" = "0"
@@ -113,25 +95,24 @@ chip soc/intel/skylake
device lapic 0 on end
end
device domain 0 on
- # Refered from SKL EDS Vol 1 : Page No: 31-32
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB 3.0 xHCI Controller
- device pci 14.1 off end # USB Device Controller (OTG)
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C Controller #0
- device pci 15.1 on end # I2C Controller #1
- device pci 15.2 on end # I2C Controller #2
- device pci 15.3 on end # I2C Controller #3
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
- device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
- device pci 16.4 off end # Management Engine Intel MEI #3
- device pci 17.0 off end # SATA Controller
- device pci 19.0 on end # UART Controller #2
- device pci 19.1 on end # I2C Controller #5
- device pci 19.2 on end # I2C Controller #4
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT-Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 on end # I2C #4
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
@@ -146,14 +127,16 @@ chip soc/intel/skylake
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 on end # UART #1
- device pci 1e.2 on end # SPI #0
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard
- device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1)
- device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
- device pci 1f.4 off end # SMBus Controller
- device pci 1f.5 on end # SPI
- device pci 1f.6 off end # GbE Controller
+ device pci 1f.0 on end # LPC Interface
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 off end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
end
end
1
0
New patch to review for coreboot: drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO level
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11559
-gerrit
commit a72a989d4b427ac30aecc0bfa1d1b010a320cb0d
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Sep 3 16:00:49 2015 -0700
drivers/pc80/tpm: Set "Found TPM" message to BIOS_INFO level
Having no supplied printk level makes this info message
printed at all levels and so it shows up when booting with
DEFAULT_CONSOLE_LOGLEVEL=3.
BUG=chrome-os-partner:40635
BRANCH=none
TEST="USE=quiet-cb emerge-glados coreboot"
Change-Id: I6c52aafbe47fdf297e2caeb05b4d79a40a9a4b9d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e6cffc6d5a9fcda60a04f8a31f2b2ffe4b620c77
Original-Change-Id: Ie6715d15f950d184805149619bebe328d528e55a
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297336
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/pc80/tpm/tpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index ba2561d..be616a2 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -410,7 +410,7 @@ static u32 tis_probe(void)
break;
}
/* this will have to be converted into debug printout */
- printf("Found TPM %s by %s\n", device_name, vendor_name);
+ printk(BIOS_INFO, "Found TPM %s by %s\n", device_name, vendor_name);
return 0;
}
1
0
New patch to review for coreboot: skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11558
-gerrit
commit 716abff6ccf8f5c2c8314dbb607169708cdfac1c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Sep 3 15:57:56 2015 -0700
skylake: dptf: Add TSR3 thermal sensor and CPU code cleanup
- glados has more thermal sensors that could be used so add
another entry in the DTPF thermal sensor ACPI code.
- fix indentation block in cpu.asl.
- declare \_SB.MPDL as external (it is already CondRefOf)
so it does not need to be present in mainboard config if
the mainboard does not want to override the default.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I1afe7013a24ee1215f5e968e25594f746bbdd17c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 8d357437d06349039a94869b088c3c50b32933c0
Original-Change-Id: Ie87d52e735bf930a003e525cf1918789920922a5
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297335
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/acpi/dptf/cpu.asl | 13 +++---
src/soc/intel/skylake/acpi/dptf/thermal.asl | 64 +++++++++++++++++++++++++++++
2 files changed, 71 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl
index 56a0d07..872ef1a 100644
--- a/src/soc/intel/skylake/acpi/dptf/cpu.asl
+++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl
@@ -50,6 +50,7 @@ External (\_PR.CPU0._TSS, MethodObj)
External (\_PR.CPU0._TPC, MethodObj)
External (\_PR.CPU0._PTC, PkgObj)
External (\_PR.CPU0._TSD, PkgObj)
+External (\_SB.MPDL, IntObj)
Device (B0D4)
{
@@ -146,12 +147,12 @@ Device (B0D4)
{
If (CondRefOf (\_PR.CP00._PSS)) {
Return (\_PR.CP00._PSS)
- } Else {
- Return (Package ()
- {
- Package () { 0, 0, 0, 0, 0, 0 }
- })
- }
+ } Else {
+ Return (Package ()
+ {
+ Package () { 0, 0, 0, 0, 0, 0 }
+ })
+ }
}
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index a6ab847..99c10da 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -38,6 +38,11 @@ Method (TEVT, 1, NotSerialized)
Notify (^TSR2, 0x90)
}
#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+ If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) {
+ Notify (^TSR3, 0x90)
+ }
+#endif
}
/* Thermal device initialization - Disable Aux Trip Points */
@@ -52,6 +57,9 @@ Method (TINI)
#ifdef DPTF_TSR2_SENSOR_ID
^TSR2.PATD ()
#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+ ^TSR3.PATD ()
+#endif
}
#ifdef DPTF_TSR0_SENSOR_ID
@@ -221,3 +229,59 @@ Device (TSR2)
}
}
#endif
+
+#ifdef DPTF_TSR3_SENSOR_ID
+Device (TSR3)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 4)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR3_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME))
+ Name (GTSH, 20) /* 2 degree hysteresis */
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Method (_PSV)
+ {
+ Return (CTOK (DPTF_TSR3_PASSIVE))
+ }
+
+ Method (_CRT)
+ {
+ Return (CTOK (DPTF_TSR3_CRITICAL))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+
+ /* Disable Aux Trip Point */
+ Method (PATD, 0, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+ }
+}
+#endif
1
0
New patch to review for coreboot: cbfs: read cbfs offset and size from sysinfo
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11557
-gerrit
commit 6e80dfee3faacb7bc8ed1e59cf1dac4ba6b4d143
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Sep 2 10:53:13 2015 -0700
cbfs: read cbfs offset and size from sysinfo
This change allows libpayload to read cbfs offset and size from sysinfo.
Legacy way of locating cbfs reagion is still supported in case sysinfo
doesn't store the offset and the size.
BUG=none
BRANCH=master
TEST=tested on samus and smaug
Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296993
Original-Commit-Ready: Daisuke Nojiri <dnojiri(a)google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri(a)google.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
payloads/libpayload/libcbfs/cbfs_core.c | 70 +++++++++++++++++++++------------
1 file changed, 45 insertions(+), 25 deletions(-)
diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
index 7926d9d..90f600c 100644
--- a/payloads/libpayload/libcbfs/cbfs_core.c
+++ b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -47,6 +47,7 @@
#include <cbfs.h>
#include <string.h>
+#include <sysinfo.h>
/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS
* on failure */
@@ -94,52 +95,71 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
return header;
}
-/* public API starts here*/
-struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end,
+ struct cbfs_media *media)
{
- const char *file_name;
- uint32_t offset, romsize, name_len;
const struct cbfs_header *header;
- struct cbfs_file file, *file_ptr;
- struct cbfs_media default_media;
- if (media == CBFS_DEFAULT_MEDIA) {
- media = &default_media;
- if (init_default_cbfs_media(media) != 0) {
- ERROR("Failed to initialize default media.\n");
- return NULL;
- }
+ if (lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) {
+ *offset = lib_sysinfo.cbfs_offset;
+ *cbfs_end = *offset + lib_sysinfo.cbfs_size;
+ return 0;
}
- if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media)))
- return NULL;
-
+ /*
+ * If sysinfo doesn't have offset or size, we read them from
+ * a master header.
+ */
+ DEBUG("CBFS offset & size not found in sysinfo\n");
+ header = cbfs_get_header(media);
+ if (header == CBFS_HEADER_INVALID_ADDRESS)
+ return -1;
// Logical offset (for source media) of first file.
- offset = ntohl(header->offset);
- romsize = ntohl(header->romsize);
-
- // TODO Add a "size" in CBFS header for a platform independent way to
- // determine the end of CBFS data.
+ *offset = ntohl(header->offset);
+ *cbfs_end = ntohl(header->romsize);
#if IS_ENABLED(CONFIG_LP_ARCH_X86)
// resolve actual length of ROM used for CBFS components
// the bootblock size was not taken into account
- romsize -= ntohl(header->bootblocksize);
+ *cbfs_end -= ntohl(header->bootblocksize);
// fine tune the length to handle alignment positioning.
// using (bootblock size) % align, to derive the
// number of bytes the bootblock is off from the alignment size.
if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT))
- romsize -= (CBFS_ALIGNMENT -
+ *cbfs_end -= (CBFS_ALIGNMENT -
(ntohl(header->bootblocksize) % CBFS_ALIGNMENT));
else
- romsize -= 1;
+ *cbfs_end -= 1;
#endif
+ return 0;
+}
+
+/* public API starts here*/
+struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name)
+{
+ const char *file_name;
+ uint32_t offset, cbfs_end, name_len;
+ struct cbfs_file file, *file_ptr;
+ struct cbfs_media default_media;
+
+ if (media == CBFS_DEFAULT_MEDIA) {
+ media = &default_media;
+ if (init_default_cbfs_media(media) != 0) {
+ ERROR("Failed to initialize default media.\n");
+ return NULL;
+ }
+ }
+
+ if (get_cbfs_range(&offset, &cbfs_end, media)) {
+ ERROR("Failed to find cbfs range\n");
+ return NULL;
+ }
- DEBUG("CBFS location: 0x%x~0x%x\n", offset, romsize);
+ DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end);
DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset);
media->open(media);
- while (offset < romsize &&
+ while (offset < cbfs_end &&
media->read(media, &file, offset, sizeof(file)) == sizeof(file)) {
if (memcmp(CBFS_FILE_MAGIC, file.magic,
sizeof(file.magic)) != 0) {
1
0
New patch to review for coreboot: braswell: Tristate CFIO 139 and CFIO 140
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11556
-gerrit
commit afe2fd6e2baaa042101e4f8fa6239cf0d519a219
Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
Date: Tue Aug 11 14:06:15 2015 -0700
braswell: Tristate CFIO 139 and CFIO 140
CFIO 139 and CFIO 140 are consuming ~5 during stanndby. The reason
for this leakage is internally it is configured to 1K PU. So there
is leakage of ~2mW in standby. Total impact ~2.5 mw in Srandby.
Configure these CFIOs as tristate for ~5mW power saving at platform
level.
BRANCH=none
TEST=PnP Team to verify that the CFIO's are tri-stated.
Change-Id: I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f11eb98cb36c504dfebe6f0fa53e9af120d21f24
Original-Change-Id: Ib309ad0c6abffa4515fdf2a2f2d9174fad7f8e8d
Original-Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292863
Original-Commit-Ready: Rajmohan Mani <rajmohan.mani(a)intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/braswell/include/soc/gpio.h | 2 ++
src/soc/intel/braswell/smihandler.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 5dda732..3cc5cf0 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -110,6 +110,8 @@
#define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68)
#define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62)
#define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67)
+#define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64)
+#define CFIO_140_MMIO_OFFSET GPIO_OFFSET(67)
/* GPIO Security registers offset */
#define GPIO_READ_ACCESS_POLICY_REG 0x0000
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index eb8ee63..576e118 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -127,6 +127,12 @@ static void tristate_gpios(uint32_t val)
HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
write32((void *)COMMUNITY_GPNORTH_BASE +
HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
+
+ /* Tri-state CFIO 139 and 140 */
+ write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
+ CFIO_139_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
+ CFIO_140_MMIO_OFFSET, val);
}
1
0
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11555
-gerrit
commit b0faa14653c98b67d18d0a210a2e4733a98dc72a
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Aug 28 14:34:09 2015 -0700
veyron: Unify identical mainboards
This patch removes a lot of code duplication between the virtually
identical Veyron Chromebook variants by merging the code into a single
directory and handling the different names solely within Kconfig. This
also allows us to easily add all the other Chromebook variants that have
only been kept in Google's firmware branch to avoid cluttering coreboot
too much, making it possible to build these boards with upstream
coreboot out of the box.
The only effective change this will have on the affected boards is
removing quirks for early board revisions (since revision numbers differ
between variants). Since all those quirks concerned early pre-MP
revisions, I doubt this will bother anyone (and the old code is still
available through the Google firmware branch if anyone needs it). It
will also expand a recent fix in Jerry that increased an LCD power-on
delay to make it compatible with another kind of panel to all boards,
which is probably not a bad idea anyway.
Leaving all non-Chromebook boards as they are for now since they often
contain more extensive differences.
BRANCH=None
BUG=None
TEST=Booted Jerry.
Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9
Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296053
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/veyron/Kconfig | 88 +++++++++
src/mainboard/google/veyron/Kconfig.name | 39 ++++
src/mainboard/google/veyron/Makefile.inc | 42 ++++
src/mainboard/google/veyron/board.h | 31 +++
src/mainboard/google/veyron/boardid.c | 49 +++++
src/mainboard/google/veyron/bootblock.c | 78 ++++++++
src/mainboard/google/veyron/chromeos.c | 148 ++++++++++++++
src/mainboard/google/veyron/devicetree.cb | 26 +++
src/mainboard/google/veyron/mainboard.c | 148 ++++++++++++++
src/mainboard/google/veyron/memlayout.ld | 1 +
src/mainboard/google/veyron/reset.c | 30 +++
src/mainboard/google/veyron/romstage.c | 117 +++++++++++
src/mainboard/google/veyron/sdram_configs.c | 54 ++++++
.../veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 ++++++++
.../veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 ++++++++
.../veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 ++++++++
.../google/veyron/sdram_inf/sdram-unused.inc | 3 +
src/mainboard/google/veyron_jerry/Kconfig | 85 --------
src/mainboard/google/veyron_jerry/Kconfig.name | 2 -
src/mainboard/google/veyron_jerry/Makefile.inc | 42 ----
src/mainboard/google/veyron_jerry/board.h | 31 ---
src/mainboard/google/veyron_jerry/boardid.c | 49 -----
src/mainboard/google/veyron_jerry/bootblock.c | 78 --------
src/mainboard/google/veyron_jerry/chromeos.c | 148 --------------
src/mainboard/google/veyron_jerry/devicetree.cb | 26 ---
src/mainboard/google/veyron_jerry/mainboard.c | 167 ----------------
src/mainboard/google/veyron_jerry/memlayout.ld | 1 -
src/mainboard/google/veyron_jerry/reset.c | 30 ---
src/mainboard/google/veyron_jerry/romstage.c | 117 -----------
src/mainboard/google/veyron_jerry/sdram_configs.c | 54 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 --------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 --------
.../google/veyron_jerry/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_mighty/Kconfig | 85 --------
src/mainboard/google/veyron_mighty/Kconfig.name | 2 -
src/mainboard/google/veyron_mighty/Makefile.inc | 42 ----
src/mainboard/google/veyron_mighty/board.h | 31 ---
src/mainboard/google/veyron_mighty/boardid.c | 49 -----
src/mainboard/google/veyron_mighty/bootblock.c | 78 --------
src/mainboard/google/veyron_mighty/chromeos.c | 148 --------------
src/mainboard/google/veyron_mighty/devicetree.cb | 26 ---
src/mainboard/google/veyron_mighty/mainboard.c | 167 ----------------
src/mainboard/google/veyron_mighty/memlayout.ld | 1 -
src/mainboard/google/veyron_mighty/reset.c | 30 ---
src/mainboard/google/veyron_mighty/romstage.c | 117 -----------
src/mainboard/google/veyron_mighty/sdram_configs.c | 54 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 --------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 --------
.../veyron_mighty/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_minnie/Kconfig | 85 --------
src/mainboard/google/veyron_minnie/Kconfig.name | 2 -
src/mainboard/google/veyron_minnie/Makefile.inc | 42 ----
src/mainboard/google/veyron_minnie/board.h | 31 ---
src/mainboard/google/veyron_minnie/board_info.txt | 1 -
src/mainboard/google/veyron_minnie/boardid.c | 49 -----
src/mainboard/google/veyron_minnie/bootblock.c | 78 --------
src/mainboard/google/veyron_minnie/chromeos.c | 148 --------------
src/mainboard/google/veyron_minnie/devicetree.cb | 26 ---
src/mainboard/google/veyron_minnie/mainboard.c | 148 --------------
src/mainboard/google/veyron_minnie/memlayout.ld | 1 -
src/mainboard/google/veyron_minnie/reset.c | 30 ---
src/mainboard/google/veyron_minnie/romstage.c | 118 ------------
src/mainboard/google/veyron_minnie/sdram_configs.c | 54 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 --------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 --------
.../veyron_minnie/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_pinky/Kconfig | 85 --------
src/mainboard/google/veyron_pinky/Kconfig.name | 2 -
src/mainboard/google/veyron_pinky/Makefile.inc | 42 ----
src/mainboard/google/veyron_pinky/board.h | 31 ---
src/mainboard/google/veyron_pinky/boardid.c | 49 -----
src/mainboard/google/veyron_pinky/bootblock.c | 78 --------
src/mainboard/google/veyron_pinky/chromeos.c | 149 --------------
src/mainboard/google/veyron_pinky/devicetree.cb | 26 ---
src/mainboard/google/veyron_pinky/mainboard.c | 213 ---------------------
src/mainboard/google/veyron_pinky/memlayout.ld | 1 -
src/mainboard/google/veyron_pinky/reset.c | 30 ---
src/mainboard/google/veyron_pinky/romstage.c | 125 ------------
src/mainboard/google/veyron_pinky/sdram_configs.c | 54 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 --------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 --------
.../google/veyron_pinky/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_shark/Kconfig | 85 --------
src/mainboard/google/veyron_shark/Kconfig.name | 2 -
src/mainboard/google/veyron_shark/Makefile.inc | 42 ----
src/mainboard/google/veyron_shark/board.h | 31 ---
src/mainboard/google/veyron_shark/boardid.c | 49 -----
src/mainboard/google/veyron_shark/bootblock.c | 78 --------
src/mainboard/google/veyron_shark/chromeos.c | 148 --------------
src/mainboard/google/veyron_shark/devicetree.cb | 26 ---
src/mainboard/google/veyron_shark/mainboard.c | 157 ---------------
src/mainboard/google/veyron_shark/memlayout.ld | 1 -
src/mainboard/google/veyron_shark/reset.c | 30 ---
src/mainboard/google/veyron_shark/romstage.c | 118 ------------
src/mainboard/google/veyron_shark/sdram_configs.c | 54 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 --------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 --------
.../google/veyron_shark/sdram_inf/sdram-unused.inc | 3 -
src/mainboard/google/veyron_speedy/Kconfig | 85 --------
src/mainboard/google/veyron_speedy/Kconfig.name | 2 -
src/mainboard/google/veyron_speedy/Makefile.inc | 42 ----
src/mainboard/google/veyron_speedy/board.h | 31 ---
src/mainboard/google/veyron_speedy/boardid.c | 49 -----
src/mainboard/google/veyron_speedy/bootblock.c | 78 --------
src/mainboard/google/veyron_speedy/chromeos.c | 148 --------------
src/mainboard/google/veyron_speedy/devicetree.cb | 26 ---
src/mainboard/google/veyron_speedy/mainboard.c | 167 ----------------
src/mainboard/google/veyron_speedy/memlayout.ld | 1 -
src/mainboard/google/veyron_speedy/reset.c | 30 ---
src/mainboard/google/veyron_speedy/romstage.c | 118 ------------
src/mainboard/google/veyron_speedy/sdram_configs.c | 54 ------
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 --------
.../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 --------
.../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 --------
.../veyron_speedy/sdram_inf/sdram-unused.inc | 3 -
176 files changed, 1710 insertions(+), 10164 deletions(-)
diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig
new file mode 100644
index 0000000..c474bd6
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig
@@ -0,0 +1,88 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards
+ def_bool n
+
+if BOARD_GOOGLE_VEYRON
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ID_AUTO
+ select COMMON_CBFS_SPI_WRAPPER
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_SPI
+ select RAM_CODE_SUPPORT
+ select SOC_ROCKCHIP_RK3288
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_DO_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_CHROMEOS
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_HARD_RESET
+ select SPI_FLASH
+ select SPI_FLASH_GIGADEVICE
+ select SPI_FLASH_WINBOND
+
+config CHROMEOS
+ select CHROMEOS_VBNV_EC
+ select EC_SOFTWARE_SYNC
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/veyron
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Veyron"
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ hex
+ default 0
+
+config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
+ int
+ default 100
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 2
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x20
+
+config CONSOLE_SERIAL_UART_ADDRESS
+ hex
+ depends on DRIVERS_UART
+ default 0xFF690000
+
+config PMIC_BUS
+ int
+ default 0
+
+endif # BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name
new file mode 100644
index 0000000..5c7a44b
--- /dev/null
+++ b/src/mainboard/google/veyron/Kconfig.name
@@ -0,0 +1,39 @@
+config BOARD_GOOGLE_VEYRON_GUS
+ bool "Veyron_Gus"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_JAQ
+ bool "Veyron_Jaq"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_JERRY
+ bool "Veyron_Jerry"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_MIGHTY
+ bool "Veyron_Mighty"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_MINNIE
+ bool "Veyron_Minnie"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_NICKY
+ bool "Veyron_Nicky"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_PINKY
+ bool "Veyron_Pinky"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_SHARK
+ bool "Veyron_Shark"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_SPEEDY
+ bool "Veyron_Speedy"
+ select BOARD_GOOGLE_VEYRON
+
+config BOARD_GOOGLE_VEYRON_THEA
+ bool "Veyron_Thea"
+ select BOARD_GOOGLE_VEYRON
diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc
new file mode 100644
index 0000000..ea1c606
--- /dev/null
+++ b/src/mainboard/google/veyron/Makefile.inc
@@ -0,0 +1,42 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+bootblock-y += bootblock.c
+bootblock-y += boardid.c
+bootblock-y += chromeos.c
+bootblock-y += reset.c
+
+verstage-y += boardid.c
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += boardid.c
+romstage-y += chromeos.c
+romstage-y += romstage.c
+romstage-y += sdram_configs.c
+romstage-y += reset.c
+
+ramstage-y += boardid.c
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += reset.c
+
+bootblock-y += memlayout.ld
+verstage-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron/board.h b/src/mainboard/google/veyron/board.h
new file mode 100644
index 0000000..a200e16
--- /dev/null
+++ b/src/mainboard/google/veyron/board.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_VEYRON_BOARD_H
+#define __MAINBOARD_GOOGLE_VEYRON_BOARD_H
+
+#include <boardid.h>
+#include <gpio.h>
+
+#define GPIO_BACKLIGHT GPIO(7, A, 2)
+#define GPIO_RESET GPIO(0, B, 5)
+
+void setup_chromeos_gpios(void);
+
+#endif /* __MAINBOARD_GOOGLE_VEYRON_BOARD_H */
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
new file mode 100644
index 0000000..f7cddcc
--- /dev/null
+++ b/src/mainboard/google/veyron/boardid.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <stdlib.h>
+
+uint8_t board_id(void)
+{
+ static int id = -1;
+ static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
+ [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
+
+ if (id < 0) {
+ id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+ printk(BIOS_SPEW, "Board ID: %d.\n", id);
+ }
+
+ return id;
+}
+
+uint32_t ram_code(void)
+{
+ uint32_t code;
+ static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
+ [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
+
+ code = gpio_base2_value(pins, ARRAY_SIZE(pins));
+ printk(BIOS_SPEW, "RAM Config: %u.\n", code);
+
+ return code;
+}
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
new file mode 100644
index 0000000..ae74972
--- /dev/null
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <delay.h>
+#include <reset.h>
+#include <soc/clock.h>
+#include <soc/i2c.h>
+#include <soc/grf.h>
+#include <soc/pmu.h>
+#include <soc/rk808.h>
+#include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+void bootblock_mainboard_early_init()
+{
+ if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
+ assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
+ }
+
+}
+
+void bootblock_mainboard_init(void)
+{
+ if (rkclk_was_watchdog_reset())
+ reboot_from_watchdog();
+
+ /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
+ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+ setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+ assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
+ i2c_init(CONFIG_PMIC_BUS, 400*KHz);
+
+ /* Slowly raise to max CPU voltage to prevent overshoot */
+ rk808_configure_buck(1, 1200);
+ udelay(175);/* Must wait for voltage to stabilize,2mV/us */
+ rk808_configure_buck(1, 1400);
+ udelay(100);/* Must wait for voltage to stabilize,2mV/us */
+ rkclk_configure_cpu();
+
+ /* i2c1 for tpm */
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
+ i2c_init(1, 400*KHz);
+
+ /* spi2 for firmware ROM */
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
+ rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
+ /* spi0 for chrome ec */
+ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
+ rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
+
+ setup_chromeos_gpios();
+}
diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c
new file mode 100644
index 0000000..5489639
--- /dev/null
+++ b/src/mainboard/google/veyron/chromeos.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <gpio.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+#define GPIO_WP GPIO(7, A, 6)
+#define GPIO_LID GPIO(0, A, 6)
+#define GPIO_POWER GPIO(0, A, 5)
+#define GPIO_RECOVERY GPIO(0, B, 1)
+#define GPIO_ECINRW GPIO(0, A, 7)
+#define GPIO_ECIRQ GPIO(7, A, 7)
+
+void setup_chromeos_gpios(void)
+{
+ gpio_input(GPIO_WP);
+ gpio_input_pullup(GPIO_LID);
+ gpio_input(GPIO_POWER);
+ gpio_input_pullup(GPIO_RECOVERY);
+ gpio_input(GPIO_ECIRQ);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = GPIO_WP.raw;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get(GPIO_WP);
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active low */
+ gpios->gpios[count].port = GPIO_RECOVERY.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Lid: active high */
+ gpios->gpios[count].port = GPIO_LID.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Power:GPIO active high */
+ gpios->gpios[count].port = GPIO_POWER.raw;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* EC in RW: GPIO active high */
+ gpios->gpios[count].port = GPIO_ECINRW.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "EC in RW",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* EC interrupt: GPIO active high */
+ gpios->gpios[count].port = GPIO_ECIRQ.raw;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "EC interrupt",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Reset: GPIO active high (output) */
+ gpios->gpios[count].port = GPIO_RESET.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "reset",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Backlight: GPIO active high (output) */
+ gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "backlight",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ uint32_t ec_events;
+
+ /* The GPIO is active low. */
+ if (!gpio_get(GPIO_RECOVERY))
+ return 1;
+
+ ec_events = google_chromeec_get_events_b();
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ return !gpio_get(GPIO_WP);
+}
diff --git a/src/mainboard/google/veyron/devicetree.cb b/src/mainboard/google/veyron/devicetree.cb
new file mode 100644
index 0000000..b958e26
--- /dev/null
+++ b/src/mainboard/google/veyron/devicetree.cb
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Rockchip Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# TODO fill with Versatile Express board data in QEMU.
+chip soc/rockchip/rk3288
+ device cpu_cluster 0 on end
+ register "vop_id" = "1"
+ register "vop_mode" = "VOP_MODE_EDP"
+ register "framebuffer_bits_per_pixel" = "16"
+end
diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c
new file mode 100644
index 0000000..b8f9aae
--- /dev/null
+++ b/src/mainboard/google/veyron/mainboard.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cache.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <edid.h>
+#include <elog.h>
+#include <gpio.h>
+#include <soc/display.h>
+#include <soc/grf.h>
+#include <soc/soc.h>
+#include <soc/pmu.h>
+#include <soc/clock.h>
+#include <soc/rk808.h>
+#include <soc/spi.h>
+#include <soc/i2c.h>
+#include <symbols.h>
+#include <vbe.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+static void configure_usb(void)
+{
+ gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
+ gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
+ gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
+}
+
+static void configure_sdmmc(void)
+{
+ write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
+
+ /* use sdmmc0 io, disable JTAG function */
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
+
+ /* Note: these power rail definitions are copied in romstage.c */
+ rk808_configure_ldo(4, 3300); /* VCCIO_SD */
+ rk808_configure_ldo(5, 3300); /* VCC33_SD */
+
+ gpio_input(GPIO(7, A, 5)); /* SD_DET */
+}
+
+static void configure_emmc(void)
+{
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
+
+ gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
+}
+
+static void configure_codec(void)
+{
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
+ i2c_init(2, 400*KHz); /* CODEC I2C */
+
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
+
+ rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
+
+ /* AUDIO IO domain 1.8V voltage selection */
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
+ rkclk_configure_i2s(12288000);
+}
+
+static void configure_vop(void)
+{
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
+
+ /* lcdc(vop) iodomain select 1.8V */
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
+
+ gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
+ rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
+ gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
+ rk808_configure_switch(1, 1); /* VCC33_LCD */
+
+ /* enable edp HPD */
+ gpio_input_pulldown(GPIO(7, B, 3));
+ write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
+}
+
+static void mainboard_init(device_t dev)
+{
+ gpio_output(GPIO_RESET, 0);
+
+ configure_usb();
+ configure_sdmmc();
+ configure_emmc();
+ configure_codec();
+ configure_vop();
+
+ elog_init();
+ elog_add_watchdog_reset();
+ elog_add_boot_reason();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+ struct lb_range *dma;
+
+ dma = (struct lb_range *)lb_new_record(header);
+ dma->tag = LB_TAB_DMA;
+ dma->size = sizeof(*dma);
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
+}
+
+void mainboard_power_on_backlight(void)
+{
+ gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
+ mdelay(120);
+ gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
+ mdelay(10);
+ gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
+}
diff --git a/src/mainboard/google/veyron/memlayout.ld b/src/mainboard/google/veyron/memlayout.ld
new file mode 100644
index 0000000..ead7f47
--- /dev/null
+++ b/src/mainboard/google/veyron/memlayout.ld
@@ -0,0 +1 @@
+#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c
new file mode 100644
index 0000000..bc26ece
--- /dev/null
+++ b/src/mainboard/google/veyron/reset.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <gpio.h>
+#include <reset.h>
+
+#include "board.h"
+
+void hard_reset(void)
+{
+ gpio_output(GPIO_RESET, 1);
+ while (1);
+}
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
new file mode 100644
index 0000000..5ccbe3e
--- /dev/null
+++ b/src/mainboard/google/veyron/romstage.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <armv7.h>
+#include <assert.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <soc/sdram.h>
+#include <soc/clock.h>
+#include <soc/pwm.h>
+#include <soc/grf.h>
+#include <soc/rk808.h>
+#include <soc/tsadc.h>
+#include <stdlib.h>
+#include <symbols.h>
+#include <timestamp.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "board.h"
+
+static void regulate_vdd_log(unsigned int mv)
+{
+ unsigned int duty_ns;
+ const u32 period_ns = 2000; /* pwm period: 2000ns */
+ const u32 max_regulator_mv = 1350; /* 1.35V */
+ const u32 min_regulator_mv = 870; /* 0.87V */
+
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
+
+ assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
+
+ duty_ns = (max_regulator_mv - mv) * period_ns /
+ (max_regulator_mv - min_regulator_mv);
+
+ pwm_init(1, period_ns, duty_ns);
+}
+
+static void configure_l2ctlr(void)
+{
+ uint32_t l2ctlr;
+
+ l2ctlr = read_l2ctlr();
+ l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+ /*
+ * Data RAM write latency: 2 cycles
+ * Data RAM read latency: 2 cycles
+ * Data RAM setup latency: 1 cycle
+ * Tag RAM write latency: 1 cycle
+ * Tag RAM read latency: 1 cycle
+ * Tag RAM setup latency: 1 cycle
+ */
+ l2ctlr |= (1 << 3 | 1 << 0);
+ write_l2ctlr(l2ctlr);
+}
+
+static void sdmmc_power_off(void)
+{
+ rk808_configure_ldo(4, 0); /* VCCIO_SD */
+ rk808_configure_ldo(5, 0); /* VCC33_SD */
+}
+
+void main(void)
+{
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ console_init();
+ configure_l2ctlr();
+ tsadc_init();
+
+ /* Need to power cycle SD card to ensure it is properly reset. */
+ sdmmc_power_off();
+
+ /* vdd_log 1200mv is enough for ddr run 666Mhz */
+ regulate_vdd_log(1200);
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ sdram_init(get_sdram_config());
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
+ mmu_config_range((uintptr_t)_dram/MiB,
+ sdram_size_mb(), DCACHE_WRITEBACK);
+ mmu_config_range((uintptr_t)_dma_coherent/MiB,
+ _dma_coherent_size/MiB, DCACHE_OFF);
+
+ cbmem_initialize_empty();
+
+ timestamp_add_now(TS_END_ROMSTAGE);
+
+ run_ramstage();
+}
diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
new file mode 100644
index 0000000..023eb37
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_configs.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <arch/io.h>
+#include <boardid.h>
+#include <console/console.h>
+#include <gpio.h>
+#include <soc/sdram.h>
+#include <string.h>
+#include <types.h>
+
+static struct rk3288_sdram_params sdram_configs[] = {
+#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
+#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
+#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
+#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
+#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
+#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
+#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
+#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
+#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
+#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
+};
+
+const struct rk3288_sdram_params *get_sdram_config()
+{
+ u32 ramcode = ram_code();
+
+ if (ramcode >= ARRAY_SIZE(sdram_configs)
+ || sdram_configs[ramcode].dramtype == UNUSED)
+ die("Invalid RAMCODE.");
+ return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
new file mode 100644
index 0000000..5b784cd
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc
new file mode 100644
index 0000000..9f2ca8a
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-4GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Hynix H5TC8G63xxx chips */
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc
new file mode 100644
index 0000000..f5793d1
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* two Samsung K4B4G1646D-BYK0 chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc
new file mode 100644
index 0000000..a32f1a6
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-4GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Samsung K4B8G1646Q chips */
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc
new file mode 100644
index 0000000..ef82b277
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* two ELPIDA F8132A3MA-GD-F chips */
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 2,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 0
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc
new file mode 100644
index 0000000..e071646
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-elpida-4GB.inc
@@ -0,0 +1,78 @@
+{
+ /* two ELPIDA FA232A2MA-GC-F chips */
+ {
+ {
+ .rank = 0x2,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ },
+ {
+ .rank = 0x2,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 6,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 0
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
new file mode 100644
index 0000000..00dc549
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 2 Hynix H9CCNNN8GTMLAR chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 14,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc
new file mode 100644
index 0000000..a48ac42
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-4GB.inc
@@ -0,0 +1,77 @@
+{
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 3,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
new file mode 100644
index 0000000..0f15ba5
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* two Samsung K4E8E304ED-EGCE000 chips */
+ {
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ },
+ {
+ .rank = 0x2,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x2,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 2,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
new file mode 100644
index 0000000..09d260b
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
@@ -0,0 +1,77 @@
+{
+ {
+ {
+ .rank = 0x2,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ },
+ {
+ .rank = 0x2,
+ .col = 0xB,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xE,
+ .cs1_row = 0xE
+ }
+ },
+ {
+ .togcnt1u = 0x215,
+ .tinit = 0xC8,
+ .trsth = 0x0,
+ .togcnt100n = 0x35,
+ .trefi = 0x26,
+ .tmrd = 0x2,
+ .trfc = 0x70,
+ .trp = 0x2000D,
+ .trtw = 0x6,
+ .tal = 0x0,
+ .tcl = 0x8,
+ .tcwl = 0x4,
+ .tras = 0x17,
+ .trc = 0x24,
+ .trcd = 0xD,
+ .trrd = 0x6,
+ .trtp = 0x4,
+ .twr = 0x8,
+ .twtr = 0x4,
+ .texsr = 0x76,
+ .txp = 0x4,
+ .txpdll = 0x0,
+ .tzqcs = 0x30,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x2,
+ .tcksrx = 0x2,
+ .tcke = 0x4,
+ .tmod = 0x0,
+ .trstl = 0x0,
+ .tzqcl = 0xC0,
+ .tmrr = 0x4,
+ .tckesr = 0x8,
+ .tdpd = 0x1F4
+ },
+ {
+ .dtpr0 = 0x48D7DD93,
+ .dtpr1 = 0x187008D8,
+ .dtpr2 = 0x121076,
+ .mr[0] = 0x0,
+ .mr[1] = 0xC3,
+ .mr[2] = 0x6,
+ .mr[3] = 0x1
+ },
+ .noc_timing = 0x20D266A4,
+ .noc_activate = 0x5B6,
+ .ddrconfig = 6,
+ .ddr_freq = 533*MHz,
+ .dramtype = LPDDR3,
+ .num_channels = 2,
+ .stride = 13,
+ .odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
new file mode 100644
index 0000000..06498f7
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
@@ -0,0 +1,3 @@
+{
+ .dramtype= UNUSED
+},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig
deleted file mode 100644
index 1bbcf94..0000000
--- a/src/mainboard/google/veyron_jerry/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_JERRY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_4096
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_jerry
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Jerry"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_JERRY
diff --git a/src/mainboard/google/veyron_jerry/Kconfig.name b/src/mainboard/google/veyron_jerry/Kconfig.name
deleted file mode 100644
index 10c5f4e..0000000
--- a/src/mainboard/google/veyron_jerry/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_JERRY
- bool "Veyron_Jerry"
diff --git a/src/mainboard/google/veyron_jerry/Makefile.inc b/src/mainboard/google/veyron_jerry/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_jerry/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_jerry/board.h b/src/mainboard/google/veyron_jerry/board.h
deleted file mode 100644
index 01be2cd..0000000
--- a/src/mainboard/google/veyron_jerry/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_JERRY_BOARD_H */
diff --git a/src/mainboard/google/veyron_jerry/boardid.c b/src/mainboard/google/veyron_jerry/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_jerry/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_jerry/chromeos.c b/src/mainboard/google/veyron_jerry/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_jerry/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_jerry/devicetree.cb b/src/mainboard/google/veyron_jerry/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_jerry/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
deleted file mode 100644
index 2a945c4..0000000
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 2:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 2:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(120);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_jerry/memlayout.ld b/src/mainboard/google/veyron_jerry/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_jerry/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_jerry/reset.c b/src/mainboard/google/veyron_jerry/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_jerry/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c
deleted file mode 100644
index 5ccbe3e..0000000
--- a/src/mainboard/google/veyron_jerry/romstage.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 5b784cd..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig
deleted file mode 100644
index 4dad49c..0000000
--- a/src/mainboard/google/veyron_mighty/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_MIGHTY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_4096
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_mighty
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Mighty"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_MIGHTY
diff --git a/src/mainboard/google/veyron_mighty/Kconfig.name b/src/mainboard/google/veyron_mighty/Kconfig.name
deleted file mode 100644
index 0eb4536..0000000
--- a/src/mainboard/google/veyron_mighty/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_MIGHTY
- bool "Veyron_Mighty"
diff --git a/src/mainboard/google/veyron_mighty/Makefile.inc b/src/mainboard/google/veyron_mighty/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_mighty/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_mighty/board.h b/src/mainboard/google/veyron_mighty/board.h
deleted file mode 100644
index 909f9a7..0000000
--- a/src/mainboard/google/veyron_mighty/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_MIGHTY_BOARD_H */
diff --git a/src/mainboard/google/veyron_mighty/boardid.c b/src/mainboard/google/veyron_mighty/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_mighty/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_mighty/chromeos.c b/src/mainboard/google/veyron_mighty/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_mighty/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_mighty/devicetree.cb b/src/mainboard/google/veyron_mighty/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_mighty/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
deleted file mode 100644
index d76e2e5..0000000
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_mighty/memlayout.ld b/src/mainboard/google/veyron_mighty/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_mighty/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_mighty/reset.c b/src/mainboard/google/veyron_mighty/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_mighty/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c
deleted file mode 100644
index 5ccbe3e..0000000
--- a/src/mainboard/google/veyron_mighty/romstage.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig
deleted file mode 100644
index f2cd87b..0000000
--- a/src/mainboard/google/veyron_minnie/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_MINNIE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_minnie
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Minnie"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_MINNIE
diff --git a/src/mainboard/google/veyron_minnie/Kconfig.name b/src/mainboard/google/veyron_minnie/Kconfig.name
deleted file mode 100644
index bb7b75e..0000000
--- a/src/mainboard/google/veyron_minnie/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_MINNIE
- bool "Veyron_Minnie"
diff --git a/src/mainboard/google/veyron_minnie/Makefile.inc b/src/mainboard/google/veyron_minnie/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_minnie/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_minnie/board.h b/src/mainboard/google/veyron_minnie/board.h
deleted file mode 100644
index 07b302b..0000000
--- a/src/mainboard/google/veyron_minnie/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_MINNIE_BOARD_H */
diff --git a/src/mainboard/google/veyron_minnie/board_info.txt b/src/mainboard/google/veyron_minnie/board_info.txt
deleted file mode 100644
index 4ce92d3..0000000
--- a/src/mainboard/google/veyron_minnie/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: laptop
diff --git a/src/mainboard/google/veyron_minnie/boardid.c b/src/mainboard/google/veyron_minnie/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_minnie/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_minnie/bootblock.c b/src/mainboard/google/veyron_minnie/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_minnie/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_minnie/chromeos.c b/src/mainboard/google/veyron_minnie/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_minnie/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_minnie/devicetree.cb b/src/mainboard/google/veyron_minnie/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_minnie/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_minnie/mainboard.c b/src/mainboard/google/veyron_minnie/mainboard.c
deleted file mode 100644
index 0de89af..0000000
--- a/src/mainboard/google/veyron_minnie/mainboard.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
-}
diff --git a/src/mainboard/google/veyron_minnie/memlayout.ld b/src/mainboard/google/veyron_minnie/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_minnie/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_minnie/reset.c b/src/mainboard/google/veyron_minnie/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_minnie/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c
deleted file mode 100644
index 9cdacc3..0000000
--- a/src/mainboard/google/veyron_minnie/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig
deleted file mode 100644
index 5c6e7cd..0000000
--- a/src/mainboard/google/veyron_pinky/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_PINKY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select BOARD_ROMSIZE_KB_4096
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_pinky
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Pinky"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_PINKY
diff --git a/src/mainboard/google/veyron_pinky/Kconfig.name b/src/mainboard/google/veyron_pinky/Kconfig.name
deleted file mode 100644
index 37d92f2..0000000
--- a/src/mainboard/google/veyron_pinky/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_PINKY
- bool "Veyron_Pinky"
diff --git a/src/mainboard/google/veyron_pinky/Makefile.inc b/src/mainboard/google/veyron_pinky/Makefile.inc
deleted file mode 100644
index a41b3bf..0000000
--- a/src/mainboard/google/veyron_pinky/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += romstage.c
-romstage-y += chromeos.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_pinky/board.h b/src/mainboard/google/veyron_pinky/board.h
deleted file mode 100644
index 24690df..0000000
--- a/src/mainboard/google/veyron_pinky/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET (board_id() > 0 ? GPIO(0, B, 5) : GPIO(0, B, 2))
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_PINKY_BOARD_H */
diff --git a/src/mainboard/google/veyron_pinky/boardid.c b/src/mainboard/google/veyron_pinky/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_pinky/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c
deleted file mode 100644
index 5e81dad..0000000
--- a/src/mainboard/google/veyron_pinky/chromeos.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID (board_id() > 0 ? GPIO(0, A, 6) : GPIO(7, B, 5))
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = board_id() > 1 ? ACTIVE_LOW :
- ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_pinky/devicetree.cb b/src/mainboard/google/veyron_pinky/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_pinky/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
deleted file mode 100644
index 2caa2be..0000000
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
-
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, B, 3), 1); /* 5V_DRV */
- break;
- case 1:
- break; /* 5V_DRV moved to EC in rev2 */
- default:
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV, again */
- break;
- }
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(8, 3300); /* VCCIO_SD */
- gpio_output(GPIO(7, C, 5), 1); /* SD_EN */
- break;
- default:
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
- break;
- }
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- switch (board_id()) {
- case 0:
- case 1:
- /*
- * Use a pullup instead of a drive since the output is 3.3V and
- * really should be 1.8V (oops). The external pulldown will help
- * bring the voltage down if we only drive with a pullup here.
- */
- gpio_input_pullup(GPIO(7, B, 4)); /* EMMC_RST_L */
- break;
- default:
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
- break;
- }
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(5, 1800); /* VCC18_CODEC */
- break;
- default:
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
- break;
- }
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(4, 1800); /* VCC18_LCD */
- rk808_configure_ldo(6, 1000); /* VCC10_LCD */
- gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */
- break;
- case 1:
- case 2:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 0:
- case 1:
- case 2:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_pinky/memlayout.ld b/src/mainboard/google/veyron_pinky/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_pinky/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_pinky/reset.c b/src/mainboard/google/veyron_pinky/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_pinky/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
deleted file mode 100644
index 3792e62..0000000
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- switch (board_id()) {
- case 0:
- rk808_configure_ldo(8, 0); /* VCCIO_SD */
- gpio_output(GPIO(7, C, 5), 0); /* SD_EN */
- break;
- default:
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
- break;
- }
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig
deleted file mode 100644
index 829fb85..0000000
--- a/src/mainboard/google/veyron_shark/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_SHARK
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_shark
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Shark"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_SHARK
diff --git a/src/mainboard/google/veyron_shark/Kconfig.name b/src/mainboard/google/veyron_shark/Kconfig.name
deleted file mode 100644
index 16c82a9..0000000
--- a/src/mainboard/google/veyron_shark/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_SHARK
- bool "Veyron_Shark"
diff --git a/src/mainboard/google/veyron_shark/Makefile.inc b/src/mainboard/google/veyron_shark/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_shark/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_shark/board.h b/src/mainboard/google/veyron_shark/board.h
deleted file mode 100644
index 47bbbdf..0000000
--- a/src/mainboard/google/veyron_shark/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_SHARK_BOARD_H */
diff --git a/src/mainboard/google/veyron_shark/boardid.c b/src/mainboard/google/veyron_shark/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_shark/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_shark/bootblock.c b/src/mainboard/google/veyron_shark/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_shark/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_shark/chromeos.c b/src/mainboard/google/veyron_shark/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_shark/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_shark/devicetree.cb b/src/mainboard/google/veyron_shark/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_shark/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_shark/mainboard.c b/src/mainboard/google/veyron_shark/mainboard.c
deleted file mode 100644
index c8cb248..0000000
--- a/src/mainboard/google/veyron_shark/mainboard.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
-}
diff --git a/src/mainboard/google/veyron_shark/memlayout.ld b/src/mainboard/google/veyron_shark/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_shark/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_shark/reset.c b/src/mainboard/google/veyron_shark/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_shark/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_shark/romstage.c b/src/mainboard/google/veyron_shark/romstage.c
deleted file mode 100644
index 9cdacc3..0000000
--- a/src/mainboard/google/veyron_shark/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_shark/sdram_configs.c b/src/mainboard/google/veyron_shark/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_shark/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_shark/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig
deleted file mode 100644
index 411ea42..0000000
--- a/src/mainboard/google/veyron_speedy/Kconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-if BOARD_GOOGLE_VEYRON_SPEEDY
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_ID_AUTO
- select BOARD_ROMSIZE_KB_4096
- select COMMON_CBFS_SPI_WRAPPER
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_SPI
- select RAM_CODE_SUPPORT
- select SOC_ROCKCHIP_RK3288
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_DO_NATIVE_VGA_INIT
- select MAINBOARD_HAS_CHROMEOS
- select HAVE_HARD_RESET
- select SPI_FLASH
- select SPI_FLASH_GIGADEVICE
- select SPI_FLASH_WINBOND
-
-config CHROMEOS
- select CHROMEOS_VBNV_EC
- select EC_SOFTWARE_SYNC
- select VIRTUAL_DEV_SWITCH
-
-config MAINBOARD_DIR
- string
- default google/veyron_speedy
-
-config MAINBOARD_PART_NUMBER
- string
- default "Veyron_Speedy"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config EC_GOOGLE_CHROMEEC_SPI_BUS
- hex
- default 0
-
-config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US
- int
- default 100
-
-config BOOT_MEDIA_SPI_BUS
- int
- default 2
-
-config DRIVER_TPM_I2C_BUS
- hex
- default 0x1
-
-config DRIVER_TPM_I2C_ADDR
- hex
- default 0x20
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0xFF690000
-
-config PMIC_BUS
- int
- default 0
-
-endif # BOARD_GOOGLE_VEYRON_SPEEDY
diff --git a/src/mainboard/google/veyron_speedy/Kconfig.name b/src/mainboard/google/veyron_speedy/Kconfig.name
deleted file mode 100644
index a5b2c9d..0000000
--- a/src/mainboard/google/veyron_speedy/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_VEYRON_SPEEDY
- bool "Veyron_Speedy"
diff --git a/src/mainboard/google/veyron_speedy/Makefile.inc b/src/mainboard/google/veyron_speedy/Makefile.inc
deleted file mode 100644
index ea1c606..0000000
--- a/src/mainboard/google/veyron_speedy/Makefile.inc
+++ /dev/null
@@ -1,42 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += romstage.c
-romstage-y += sdram_configs.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/veyron_speedy/board.h b/src/mainboard/google/veyron_speedy/board.h
deleted file mode 100644
index ee705df..0000000
--- a/src/mainboard/google/veyron_speedy/board.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H
-#define __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H
-
-#include <boardid.h>
-#include <gpio.h>
-
-#define GPIO_BACKLIGHT GPIO(7, A, 2)
-#define GPIO_RESET GPIO(0, B, 5)
-
-void setup_chromeos_gpios(void);
-
-#endif /* __MAINBOARD_GOOGLE_VEYRON_SPEEDY_BOARD_H */
diff --git a/src/mainboard/google/veyron_speedy/boardid.c b/src/mainboard/google/veyron_speedy/boardid.c
deleted file mode 100644
index f7cddcc..0000000
--- a/src/mainboard/google/veyron_speedy/boardid.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-
-uint8_t board_id(void)
-{
- static int id = -1;
- static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
- [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
-
- if (id < 0) {
- id = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "Board ID: %d.\n", id);
- }
-
- return id;
-}
-
-uint32_t ram_code(void)
-{
- uint32_t code;
- static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
- [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
-
- code = gpio_base2_value(pins, ARRAY_SIZE(pins));
- printk(BIOS_SPEW, "RAM Config: %u.\n", code);
-
- return code;
-}
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
deleted file mode 100644
index ae74972..0000000
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <delay.h>
-#include <reset.h>
-#include <soc/clock.h>
-#include <soc/i2c.h>
-#include <soc/grf.h>
-#include <soc/pmu.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-void bootblock_mainboard_early_init()
-{
- if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
- assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
- }
-
-}
-
-void bootblock_mainboard_init(void)
-{
- if (rkclk_was_watchdog_reset())
- reboot_from_watchdog();
-
- /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
- setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
- setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
- assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
- i2c_init(CONFIG_PMIC_BUS, 400*KHz);
-
- /* Slowly raise to max CPU voltage to prevent overshoot */
- rk808_configure_buck(1, 1200);
- udelay(175);/* Must wait for voltage to stabilize,2mV/us */
- rk808_configure_buck(1, 1400);
- udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
-
- /* i2c1 for tpm */
- write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
- i2c_init(1, 400*KHz);
-
- /* spi2 for firmware ROM */
- write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
- write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
-
- /* spi0 for chrome ec */
- write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
-
- setup_chromeos_gpios();
-}
diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c
deleted file mode 100644
index 5489639..0000000
--- a/src/mainboard/google/veyron_speedy/chromeos.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#include <gpio.h>
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-#define GPIO_WP GPIO(7, A, 6)
-#define GPIO_LID GPIO(0, A, 6)
-#define GPIO_POWER GPIO(0, A, 5)
-#define GPIO_RECOVERY GPIO(0, B, 1)
-#define GPIO_ECINRW GPIO(0, A, 7)
-#define GPIO_ECIRQ GPIO(7, A, 7)
-
-void setup_chromeos_gpios(void)
-{
- gpio_input(GPIO_WP);
- gpio_input_pullup(GPIO_LID);
- gpio_input(GPIO_POWER);
- gpio_input_pullup(GPIO_RECOVERY);
- gpio_input(GPIO_ECIRQ);
-}
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- int count = 0;
-
- /* Write Protect: active low */
- gpios->gpios[count].port = GPIO_WP.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO_WP);
- strncpy((char *)gpios->gpios[count].name, "write protect",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Recovery: active low */
- gpios->gpios[count].port = GPIO_RECOVERY.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_recovery_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "recovery",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Lid: active high */
- gpios->gpios[count].port = GPIO_LID.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Power:GPIO active high */
- gpios->gpios[count].port = GPIO_POWER.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "power",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Developer: GPIO active high */
- gpios->gpios[count].port = -1;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = get_developer_mode_switch();
- strncpy((char *)gpios->gpios[count].name, "developer",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC in RW: GPIO active high */
- gpios->gpios[count].port = GPIO_ECINRW.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC in RW",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* EC interrupt: GPIO active high */
- gpios->gpios[count].port = GPIO_ECIRQ.raw;
- gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "EC interrupt",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Reset: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_RESET.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "reset",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- /* Backlight: GPIO active high (output) */
- gpios->gpios[count].port = GPIO_BACKLIGHT.raw;
- gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = -1;
- strncpy((char *)gpios->gpios[count].name, "backlight",
- GPIO_MAX_NAME_LENGTH);
- count++;
-
- gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
- gpios->count = count;
-
- printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
-}
-
-int get_developer_mode_switch(void)
-{
- return 0;
-}
-
-int get_recovery_mode_switch(void)
-{
- uint32_t ec_events;
-
- /* The GPIO is active low. */
- if (!gpio_get(GPIO_RECOVERY))
- return 1;
-
- ec_events = google_chromeec_get_events_b();
- return !!(ec_events &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-}
-
-int get_write_protect_state(void)
-{
- return !gpio_get(GPIO_WP);
-}
diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb
deleted file mode 100644
index b958e26..0000000
--- a/src/mainboard/google/veyron_speedy/devicetree.cb
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Rockchip Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/rockchip/rk3288
- device cpu_cluster 0 on end
- register "vop_id" = "1"
- register "vop_mode" = "VOP_MODE_EDP"
- register "framebuffer_bits_per_pixel" = "16"
-end
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
deleted file mode 100644
index d76e2e5..0000000
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/i2c.h>
-#include <edid.h>
-#include <elog.h>
-#include <gpio.h>
-#include <soc/display.h>
-#include <soc/grf.h>
-#include <soc/soc.h>
-#include <soc/pmu.h>
-#include <soc/clock.h>
-#include <soc/rk808.h>
-#include <soc/spi.h>
-#include <soc/i2c.h>
-#include <symbols.h>
-#include <vbe.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void configure_usb(void)
-{
- gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */
- gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
- gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */
-}
-
-static void configure_sdmmc(void)
-{
- write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
-
- /* use sdmmc0 io, disable JTAG function */
- write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
-
- /* Note: these power rail definitions are copied in romstage.c */
- rk808_configure_ldo(4, 3300); /* VCCIO_SD */
- rk808_configure_ldo(5, 3300); /* VCC33_SD */
-
- gpio_input(GPIO(7, A, 5)); /* SD_DET */
-}
-
-static void configure_emmc(void)
-{
- write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
- write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
- write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
-
- gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
-}
-
-static void configure_codec(void)
-{
- write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
- i2c_init(2, 400*KHz); /* CODEC I2C */
-
- write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
- write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
-
- rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
-
- /* AUDIO IO domain 1.8V voltage selection */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
- rkclk_configure_i2s(12288000);
-}
-
-static void configure_vop(void)
-{
- write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
-
- /* lcdc(vop) iodomain select 1.8V */
- write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
-
- switch (board_id()) {
- case 0:
- rk808_configure_switch(2, 1); /* VCC18_LCD */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
- break;
- default:
- gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
- rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
- gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
- rk808_configure_switch(1, 1); /* VCC33_LCD */
-
- /* enable edp HPD */
- gpio_input_pulldown(GPIO(7, B, 3));
- write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
- break;
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- gpio_output(GPIO_RESET, 0);
-
- configure_usb();
- configure_sdmmc();
- configure_emmc();
- configure_codec();
- configure_vop();
-
- elog_init();
- elog_add_watchdog_reset();
- elog_add_boot_reason();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
-
-void mainboard_power_on_backlight(void)
-{
- switch (board_id()) {
- case 0:
- gpio_output(GPIO(7, A, 0), 0); /* BL_EN */
- gpio_output(GPIO(7, A, 2), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO(7, A, 0), 1); /* BL_EN */
- break;
- default:
- gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */
- mdelay(20);
- gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */
- mdelay(10);
- gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */
- break;
- }
-}
diff --git a/src/mainboard/google/veyron_speedy/memlayout.ld b/src/mainboard/google/veyron_speedy/memlayout.ld
deleted file mode 100644
index ead7f47..0000000
--- a/src/mainboard/google/veyron_speedy/memlayout.ld
+++ /dev/null
@@ -1 +0,0 @@
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/veyron_speedy/reset.c b/src/mainboard/google/veyron_speedy/reset.c
deleted file mode 100644
index bc26ece..0000000
--- a/src/mainboard/google/veyron_speedy/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/io.h>
-#include <gpio.h>
-#include <reset.h>
-
-#include "board.h"
-
-void hard_reset(void)
-{
- gpio_output(GPIO_RESET, 1);
- while (1);
-}
diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c
deleted file mode 100644
index 9cdacc3..0000000
--- a/src/mainboard/google/veyron_speedy/romstage.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/io.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
- unsigned int duty_ns;
- const u32 period_ns = 2000; /* pwm period: 2000ns */
- const u32 max_regulator_mv = 1350; /* 1.35V */
- const u32 min_regulator_mv = 870; /* 0.87V */
-
- write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
- assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
- duty_ns = (max_regulator_mv - mv) * period_ns /
- (max_regulator_mv - min_regulator_mv);
-
- pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-static void sdmmc_power_off(void)
-{
- rk808_configure_ldo(4, 0); /* VCCIO_SD */
- rk808_configure_ldo(5, 0); /* VCC33_SD */
-}
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
- configure_l2ctlr();
- tsadc_init();
-
- /* Need to power cycle SD card to ensure it is properly reset. */
- sdmmc_power_off();
-
- /* vdd_log 1200mv is enough for ddr run 666Mhz */
- regulate_vdd_log(1200);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- sdram_init(get_sdram_config());
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
-
- cbmem_initialize_empty();
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
- run_ramstage();
-}
diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c
deleted file mode 100644
index 023eb37..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_configs.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-#include <arch/io.h>
-#include <boardid.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <soc/sdram.h>
-#include <string.h>
-#include <types.h>
-
-static struct rk3288_sdram_params sdram_configs[] = {
-#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
-#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
-#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
-#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
-#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
-#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
-#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
-#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
-#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
-#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
-};
-
-const struct rk3288_sdram_params *get_sdram_config()
-{
- u32 ramcode = ram_code();
-
- if (ramcode >= ARRAY_SIZE(sdram_configs)
- || sdram_configs[ramcode].dramtype == UNUSED)
- die("Invalid RAMCODE.");
- return &sdram_configs[ramcode];
-}
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc
deleted file mode 100644
index 659cfd4..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc
deleted file mode 100644
index 9f2ca8a..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Hynix H5TC8G63xxx chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
deleted file mode 100644
index bd82e7b..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Nanya NT5CC256M16DP chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc
deleted file mode 100644
index f5793d1..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4B4G1646D-BYK0 chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc
deleted file mode 100644
index a32f1a6..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 4 Samsung K4B8G1646Q chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x29A,
- .tinit = 0xC8,
- .trsth = 0x1F4,
- .togcnt100n = 0x42,
- .trefi = 0x4E,
- .tmrd = 0x4,
- .trfc = 0xEA,
- .trp = 0xA,
- .trtw = 0x5,
- .tal = 0x0,
- .tcl = 0xA,
- .tcwl = 0x7,
- .tras = 0x19,
- .trc = 0x24,
- .trcd = 0xA,
- .trrd = 0x7,
- .trtp = 0x5,
- .twr = 0xA,
- .twtr = 0x5,
- .texsr = 0x200,
- .txp = 0x5,
- .txpdll = 0x10,
- .tzqcs = 0x40,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x7,
- .tcksrx = 0x7,
- .tcke = 0x4,
- .tmod = 0xC,
- .trstl = 0x43,
- .tzqcl = 0x100,
- .tmrr = 0x0,
- .tckesr = 0x5,
- .tdpd = 0x0
- },
- {
- .dtpr0 = 0x48F9AAB4,
- .dtpr1 = 0xEA0910,
- .dtpr2 = 0x1002C200,
- .mr[0] = 0xA60,
- .mr[1] = 0x40,
- .mr[2] = 0x10,
- .mr[3] = 0x0
- },
- .noc_timing = 0x30B25564,
- .noc_activate = 0x627,
- .ddrconfig = 3,
- .ddr_freq = 666*MHz,
- .dramtype = DDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 1
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
deleted file mode 100644
index ef82b277..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA F8132A3MA-GD-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
deleted file mode 100644
index e071646..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two ELPIDA FA232A2MA-GC-F chips */
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
deleted file mode 100644
index 00dc549..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* 2 Hynix H9CCNNN8GTMLAR chips */
- {
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x1,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 14,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
deleted file mode 100644
index a48ac42..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-hynix-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xF,
- .cs1_row = 0xF
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 3,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
deleted file mode 100644
index 0f15ba5..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-2GB.inc
+++ /dev/null
@@ -1,78 +0,0 @@
-{
- /* two Samsung K4E8E304ED-EGCE000 chips */
- {
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xA,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x2,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 2,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 9,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
deleted file mode 100644
index 09d260b..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-samsung-4GB.inc
+++ /dev/null
@@ -1,77 +0,0 @@
-{
- {
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- },
- {
- .rank = 0x2,
- .col = 0xB,
- .bk = 0x3,
- .bw = 0x2,
- .dbw = 0x1,
- .row_3_4 = 0x0,
- .cs0_row = 0xE,
- .cs1_row = 0xE
- }
- },
- {
- .togcnt1u = 0x215,
- .tinit = 0xC8,
- .trsth = 0x0,
- .togcnt100n = 0x35,
- .trefi = 0x26,
- .tmrd = 0x2,
- .trfc = 0x70,
- .trp = 0x2000D,
- .trtw = 0x6,
- .tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x4,
- .tras = 0x17,
- .trc = 0x24,
- .trcd = 0xD,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
- .texsr = 0x76,
- .txp = 0x4,
- .txpdll = 0x0,
- .tzqcs = 0x30,
- .tzqcsi = 0x0,
- .tdqs = 0x1,
- .tcksre = 0x2,
- .tcksrx = 0x2,
- .tcke = 0x4,
- .tmod = 0x0,
- .trstl = 0x0,
- .tzqcl = 0xC0,
- .tmrr = 0x4,
- .tckesr = 0x8,
- .tdpd = 0x1F4
- },
- {
- .dtpr0 = 0x48D7DD93,
- .dtpr1 = 0x187008D8,
- .dtpr2 = 0x121076,
- .mr[0] = 0x0,
- .mr[1] = 0xC3,
- .mr[2] = 0x6,
- .mr[3] = 0x1
- },
- .noc_timing = 0x20D266A4,
- .noc_activate = 0x5B6,
- .ddrconfig = 6,
- .ddr_freq = 533*MHz,
- .dramtype = LPDDR3,
- .num_channels = 2,
- .stride = 13,
- .odt = 0,
-},
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc
deleted file mode 100644
index 06498f7..0000000
--- a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-unused.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- .dramtype= UNUSED
-},
\ No newline at end of file
1
0
New patch to review for coreboot: kunimitsu: Fix incorrect comment format in devicetree.cb
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11554
-gerrit
commit ed2211e7ff053cc105151c6643ece24d91a3e074
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Aug 31 10:01:03 2015 -0700
kunimitsu: Fix incorrect comment format in devicetree.cb
The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the kunimitsu
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296302
Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/intel/kunimitsu/devicetree.cb | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 1c3cf67..5cc4f2e 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,17 +15,17 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
- register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */
- register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */
- register "PortUsb20Enable[2]" = "1" /* Bluetooth */
- register "PortUsb20Enable[4]" = "1" /* Type-A Port (card) */
- register "PortUsb20Enable[6]" = "1" /* Camera */
- register "PortUsb20Enable[8]" = "1" /* Type-A Port (board) */
-
- register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */
- register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */
- register "PortUsb30Enable[2]" = "1" /* Type-A Port (card) */
- register "PortUsb30Enable[3]" = "1" /* Type-A Port (board) */
+ register "PortUsb20Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb20Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb20Enable[2]" = "1" # Bluetooth
+ register "PortUsb20Enable[4]" = "1" # Type-A Port (card)
+ register "PortUsb20Enable[6]" = "1" # Camera
+ register "PortUsb20Enable[8]" = "1" # Type-A Port (board)
+
+ register "PortUsb30Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb30Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb30Enable[2]" = "1" # Type-A Port (card)
+ register "PortUsb30Enable[3]" = "1" # Type-A Port (board)
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
1
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New patch to review for coreboot: glados: Fix incorrect comment format in devicetree.cb
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11553
-gerrit
commit d9aceefb964ddef553e5d28ad1155ab575db4c66
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Aug 31 09:49:08 2015 -0700
glados: Fix incorrect comment format in devicetree.cb
The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the glados
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296301
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/glados/devicetree.cb | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2c6d997..40fe2b1 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -20,17 +20,17 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
- register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */
- register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */
- register "PortUsb20Enable[2]" = "1" /* Bluetooth */
- register "PortUsb20Enable[4]" = "1" /* Type-A Port 1 */
- register "PortUsb20Enable[6]" = "1" /* Camera */
- register "PortUsb20Enable[8]" = "1" /* Type-A Port 2 */
+ register "PortUsb20Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb20Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb20Enable[2]" = "1" # Bluetooth
+ register "PortUsb20Enable[4]" = "1" # Type-A Port 1
+ register "PortUsb20Enable[6]" = "1" # Camera
+ register "PortUsb20Enable[8]" = "1" # Type-A Port 2
- register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */
- register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */
- register "PortUsb30Enable[2]" = "1" /* Type-A Port 1 */
- register "PortUsb30Enable[3]" = "1" /* Type-A Port 2 */
+ register "PortUsb30Enable[0]" = "1" # Type-C Port 1
+ register "PortUsb30Enable[1]" = "1" # Type-C Port 2
+ register "PortUsb30Enable[2]" = "1" # Type-A Port 1
+ register "PortUsb30Enable[3]" = "1" # Type-A Port 2
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
1
0
New patch to review for coreboot: Skylake: Print GPIO MMIO base and pad config using gpio_debug token
by Patrick Georgi 07 Sep '15
by Patrick Georgi 07 Sep '15
07 Sep '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11552
-gerrit
commit 3ebac819793a420579cf4035830e7403bf6f8320
Author: Subrata Banik <subrata.banik(a)intel.com>
Date: Mon Aug 31 17:10:35 2015 +0530
Skylake: Print GPIO MMIO base and pad config using gpio_debug token
This will help development activity. Default GPIO print settings is
disable, need to set gpio_debug = 1 to get GPIO MMIO dump.
BUG=None
BRANCH=None
TEST=build coreboot and boot on Kunimitsu.
Change-Id: I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 19102612ea40184307ecb0ce8b165b5b989f6911
Original-Change-Id: I4ea6349866c108382de9787bb9ed09fc78d9c770
Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/296280
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/gpio.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 3610a6c..64b3dda 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -25,6 +25,7 @@
#include <soc/iomap.h>
#include <soc/pm.h>
+static const int gpio_debug = 0;
/* There are 4 communities with 8 GPIO groups (GPP_[A:G] and GPD) */
struct gpio_community {
@@ -323,6 +324,11 @@ static void gpio_configure_pad(const struct pad_config *cfg)
if ((dw0 & PAD_FIELD(GPIROUTSMI, MASK)) == PAD_FIELD(GPIROUTSMI, YES))
gpi_enable_smi(cfg->pad);
+
+ if(gpio_debug)
+ printk(BIOS_DEBUG,
+ "Write Pad: Base(%p) - conf0 = %x conf1= %x pad # = %d\n",
+ &dw_regs[0], dw0, reg, cfg->pad);
}
void gpio_configure_pads(const struct pad_config *cfgs, size_t num)
1
0