coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

1 participants
859 discussions

New patch to review for coreboot: chromeec: Add kconfig entry for EC PD support
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11571 -gerrit commit 5ed2f05a79f54f662076ff759a6105fe216b87d3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Sep 4 10:14:18 2015 -0700 chromeec: Add kconfig entry for EC PD support Add a kconfig entry to indicate that a board has a PD chip and try to put it in RO mode before the EC during early init. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297747 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 6 ++++++ src/ec/google/chromeec/ec.c | 11 ++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 25cc0e4..2a86f33 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -47,6 +47,12 @@ config EC_GOOGLE_CHROMEEC_MEC help Microchip EC variant for LPC register access. +config EC_GOOGLE_CHROMEEC_PD + depends on EC_GOOGLE_CHROMEEC + def_bool n + help + Indicates that Google's Chrome USB PD chip is present. + config EC_GOOGLE_CHROMEEC_SPI depends on EC_GOOGLE_CHROMEEC def_bool n diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index de58d97..e1006dc 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -163,9 +163,14 @@ void google_chromeec_check_ec_image(int expected_type) /* Check for recovery mode and ensure EC is in RO */ void google_chromeec_early_init(void) { - /* If in recovery ensure EC is running RO firmware. */ - if (recovery_mode_enabled()) { - google_chromeec_check_ec_image(EC_IMAGE_RO); + if (IS_ENABLED(CONFIG_CHROMEOS)) { + /* Check USB PD chip state first */ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_PD)) + google_chromeec_early_pd_init(); + + /* If in recovery ensure EC is running RO firmware. */ + if (recovery_mode_enabled()) + google_chromeec_check_ec_image(EC_IMAGE_RO); } }

1 0

New patch to review for coreboot: glados: Add Board ID support
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11570 -gerrit commit 8c16d5c1e3a44e162b2a3f1d972b2ac32dad65b5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Sep 4 10:12:59 2015 -0700 glados: Add Board ID support Add support for reading board id and populating it in the coreboot tables so it is exposed to payloads. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados and look for reported board ID Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004 Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297746 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/Kconfig | 1 + src/mainboard/google/glados/Makefile.inc | 2 ++ src/mainboard/google/glados/boardid.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 1f8a130..a80e16f 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -2,6 +2,7 @@ if BOARD_GOOGLE_GLADOS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 select CACHE_ROM select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index 93fc3d6..39129e8 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -19,6 +19,7 @@ subdirs-y += spd +romstage-y += boardid.c romstage-y += pei_data.c romstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -26,6 +27,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += pei_data.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/glados/boardid.c b/src/mainboard/google/glados/boardid.c new file mode 100644 index 0000000..59c6fff --- /dev/null +++ b/src/mainboard/google/glados/boardid.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +}

1 0

New patch to review for coreboot: glados: Enable DPTF
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11569 -gerrit commit 30bc8ba1e06166c6beb07d513f973b9738b20add Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:22:49 2015 -0700 glados: Enable DPTF - Add ACPI code for DPTF support with placeholder thresholds - Do not have custom PDL for mainboard - Do not have enable charger control for DPTF as there is already a complicated charge profile in the EC. We may still want to enable this but it would need to be tuned to work well with the EC profile. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297745 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/acpi/dptf.asl | 91 +++++++++++++++++++++++++++++++ src/mainboard/google/glados/devicetree.cb | 3 + src/mainboard/google/glados/dsdt.asl | 3 + 3 files changed, 97 insertions(+) diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl new file mode 100644 index 0000000..77578f6 --- /dev/null +++ b/src/mainboard/google/glados/acpi/dptf.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_TSR3_SENSOR_ID 4 +#define DPTF_TSR3_SENSOR_NAME "WiFi" +#define DPTF_TSR3_PASSIVE 55 +#define DPTF_TSR3_CRITICAL 70 + +/* SKL-Y EC already has a custom charge profile based on temperature. */ +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 3 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 1d2f8bf..60966c7 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index 6ac0be4..ba1b263 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -43,6 +43,9 @@ DefinitionBlock( #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" } // Chrome OS specific

1 0

New patch to review for coreboot: glados: Misc code cleanups
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11568 -gerrit commit 78c43fc574106e8458b761a37f30a5b02eeaad5c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:19:42 2015 -0700 glados: Misc code cleanups - romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/ec.c | 13 ++++--------- src/mainboard/google/glados/pei_data.c | 22 ++++++++++------------ src/mainboard/google/glados/romstage.c | 1 + src/mainboard/google/glados/spd/spd.c | 6 ++++-- 4 files changed, 19 insertions(+), 23 deletions(-) diff --git a/src/mainboard/google/glados/ec.c b/src/mainboard/google/glados/ec.c index c491ad5..5473cfc 100644 --- a/src/mainboard/google/glados/ec.c +++ b/src/mainboard/google/glados/ec.c @@ -25,11 +25,9 @@ void mainboard_ec_init(void) { - printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); + printk(BIOS_DEBUG, "mainboard: EC init\n"); - /* Restore SCI event mask on resume. */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S3_WAKE_EVENTS); @@ -39,10 +37,8 @@ void mainboard_ec_init(void) /* Clear pending events */ while (google_chromeec_get_event() != 0) ; - /* - * Set SCI mask.OS may not generate SMI event to set - * this on S3 resume. - */ + + /* Restore SCI event mask */ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); } else { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | @@ -51,5 +47,4 @@ void mainboard_ec_init(void) /* Clear wake event mask */ google_chromeec_set_wake_mask(0); - post_code(0xf1); } diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c index 55d7f08..6d2ae15 100644 --- a/src/mainboard/google/glados/pei_data.c +++ b/src/mainboard/google/glados/pei_data.c @@ -27,22 +27,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { /* DQ byte map */ const u8 dq_map[2][12] = { - {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , - 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00}, - {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC , - 0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} }; + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - {0, 1, 3, 2, 4, 5, 6, 7}, - {1, 0, 4, 5, 2, 3, 6, 7} }; + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; - /* Rcomp resistor*/ - const u16 RcompResistor[3] = {200, 81, 162 }; + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; - /* Rcomp target*/ - const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; - - pei_data->ec_present = 1; + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 36a8453..44a896f 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -24,6 +24,7 @@ #include <memory_info.h> #include <string.h> #include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index fc9cb53..0a17d68 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -22,9 +22,11 @@ #include <cbfs.h> #include <console/console.h> #include <gpio.h> -#include <string.h> +#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/romstage.h> +#include <string.h> + #include "../gpio.h" #include "spd.h" @@ -94,7 +96,7 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - printk(BIOS_ERR, "SPD index %d\n", spd_index); + printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,

1 0

New patch to review for coreboot: glados: Remove thermal.h
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11567 -gerrit commit f45cb906734313eac7a943b325807e870fe7bf67 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:13:36 2015 -0700 glados: Remove thermal.h The constants defined in thermal.h are never used since there is no defined thermal zone. Remove it to result in less code to worry about in board ports. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10 Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297743 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/acpi_tables.c | 21 ------------------- src/mainboard/google/glados/thermal.h | 35 ------------------------------- 2 files changed, 56 deletions(-) diff --git a/src/mainboard/google/glados/acpi_tables.c b/src/mainboard/google/glados/acpi_tables.c index cb0afc4..6da1e1d 100644 --- a/src/mainboard/google/glados/acpi_tables.c +++ b/src/mainboard/google/glados/acpi_tables.c @@ -18,35 +18,14 @@ * Foundation, Inc. */ -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/cpu.h> #include <soc/acpi.h> #include <soc/nvs.h> -#include "thermal.h" - -extern const unsigned char AmlCode[]; void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - - gnvs->tmps = TEMPERATURE_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/glados/thermal.h b/src/mainboard/google/glados/thermal.h deleted file mode 100644 index ef03d717..0000000 --- a/src/mainboard/google/glados/thermal.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _MAINBOARD_THERMAL_H_ -#define _MAINBOARD_THERMAL_H_ - -#define TEMPERATURE_SENSOR_ID 0 /* PECI */ - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 99 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 95 - -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 - -#endif /* _MAINBOARD_THERMAL_H_ */

1 0

New patch to review for coreboot: glados: Change include headers to relative path
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11566 -gerrit commit 8fc54183ae1e7778258407299f85c43542845399 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:10:48 2015 -0700 glados: Change include headers to relative path To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/acpi/chromeos.asl | 2 +- src/mainboard/google/glados/acpi/ec.asl | 4 ++-- src/mainboard/google/glados/acpi/mainboard.asl | 6 +++--- src/mainboard/google/glados/acpi/superio.asl | 2 +- src/mainboard/google/glados/chromeos.c | 2 +- src/mainboard/google/glados/spd/spd.c | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl index b8cef5e..6b16dbc 100644 --- a/src/mainboard/google/glados/acpi/chromeos.asl +++ b/src/mainboard/google/glados/acpi/chromeos.asl @@ -17,7 +17,7 @@ * Foundation, Inc. */ -#include <mainboard/google/glados/gpio.h> +#include "../gpio.h" Name (OIPG, Package () { /* No physical recovery GPIO. */ diff --git a/src/mainboard/google/glados/acpi/ec.asl b/src/mainboard/google/glados/acpi/ec.asl index 33a7471..d69ebe2 100644 --- a/src/mainboard/google/glados/acpi/ec.asl +++ b/src/mainboard/google/glados/acpi/ec.asl @@ -18,8 +18,8 @@ */ /* mainboard configuration */ -#include <mainboard/google/glados/ec.h> -#include <mainboard/google/glados/gpio.h> +#include "../ec.h" +#include "../gpio.h" /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index efa7ddd..0184a6a 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -17,7 +17,7 @@ * Foundation, Inc. */ -#include <mainboard/google/glados/gpio.h> +#include "../gpio.h" #define BOARD_TOUCHPAD_I2C_ADDR 0x15 #define BOARD_TOUCHPAD_IRQ TOUCHPAD_INT_L @@ -67,7 +67,7 @@ Scope (\_SB.PCI0.I2C0) Name (_UID, 1) Name (_S0W, 4) - Name (_CRS, ResourceTemplate() + Name (_CRS, ResourceTemplate () { I2cSerialBus ( BOARD_TOUCHSCREEN_I2C_ADDR, @@ -99,7 +99,7 @@ Scope (\_SB.PCI0.I2C1) Name (_UID, 1) Name (_S0W, 4) - Name (_CRS, ResourceTemplate() + Name (_CRS, ResourceTemplate () { I2cSerialBus ( BOARD_TOUCHPAD_I2C_ADDR, diff --git a/src/mainboard/google/glados/acpi/superio.asl b/src/mainboard/google/glados/acpi/superio.asl index 932fef7..822821e 100644 --- a/src/mainboard/google/glados/acpi/superio.asl +++ b/src/mainboard/google/glados/acpi/superio.asl @@ -18,7 +18,7 @@ */ /* mainboard configuration */ -#include <mainboard/google/glados/ec.h> +#include "../ec.h" #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index dba1cbb..7d42808 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -28,8 +28,8 @@ #include <string.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <mainboard/google/glados/gpio.h> +#include "gpio.h" #include "ec.h" #if ENV_RAMSTAGE diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index ad05b31..fc9cb53 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -25,7 +25,7 @@ #include <string.h> #include <soc/pei_data.h> #include <soc/romstage.h> -#include <mainboard/google/glados/gpio.h> +#include "../gpio.h" #include "spd.h" static void mainboard_print_spd_info(uint8_t spd[])

1 0

New patch to review for coreboot: skylake: Enable DPTF based on devicetree setting
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11565 -gerrit commit a43f4da6503801cdf81a94863e061eddb77ed868 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Sep 4 13:53:14 2015 -0700 skylake: Enable DPTF based on devicetree setting Enable DPTF flag in ACPI NVS based on devicetree setting for the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glaods coreboot Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5 Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297755 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 6 ++++++ src/soc/intel/skylake/chip.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 87d4eb0..1c3ec79 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -169,6 +169,9 @@ static int get_cores_per_package(void) void acpi_init_gnvs(global_nvs_t *gnvs) { + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = dev->chip_info; + /* Set unknown wake source */ gnvs->pm1i = -1; @@ -189,6 +192,9 @@ void acpi_init_gnvs(global_nvs_t *gnvs) #endif gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif + + /* Enable DPTF based on mainboard configuration */ + gnvs->dpte = config->dptf_enable; } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 9b43b7f..94aa3a4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -86,6 +86,9 @@ struct soc_intel_skylake_config { /* Enable S0iX support */ int s0ix_enable; + /* Enable DPTF support */ + int dptf_enable; + /* Deep SX enable for both AC and DC */ int deep_s3_enable; int deep_s5_enable;

1 0

New patch to review for coreboot: skylake: igd: clean up igd.c
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11564 -gerrit commit f940efec62781e5aaa3168193298d5ec46da8f2e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:07:35 2015 -0700 skylake: igd: clean up igd.c Remove unused constants, remove unused headers, and fix the use of acpi_slp_type variable. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I2d041f61605e0fc96483a1e825ab082668a0fa44 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bc57147cb7fa3c38169fcdd62cc9e35d8058414a Original-Change-Id: If411ad50650e6705da7de50f5be8b1d414766a8c Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297741 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/igd.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 25d89c3..5422217 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -26,21 +26,15 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <reg_script.h> #include <drivers/intel/gma/i915_reg.h> #include <soc/cpu.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <stdlib.h> +#include <string.h> #include <vendorcode/google/chromeos/chromeos.h> -#define GT_RETRY 1000 -#define GT_CDCLK_337 0 -#define GT_CDCLK_450 1 -#define GT_CDCLK_540 2 -#define GT_CDCLK_675 3 u32 map_oprom_vendev(u32 vendev) { return SA_IGD_OPROM_VENDEV; @@ -80,16 +74,16 @@ static void igd_init(struct device *dev) return; /* Wait for any configured pre-graphics delay */ - if (acpi_slp_type != SLEEP_STATE_S3) { + if (!acpi_is_wakeup_s3()) { #if IS_ENABLED(CONFIG_CHROMEOS) - if (developer_mode_enabled() || recovery_mode_enabled() || - vboot_wants_oprom()) - mdelay(CONFIG_PRE_GRAPHICS_DELAY); + if (developer_mode_enabled() || recovery_mode_enabled() || + vboot_wants_oprom()) + mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else - mdelay(CONFIG_PRE_GRAPHICS_DELAY); + mdelay(CONFIG_PRE_GRAPHICS_DELAY); #endif - } + /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); @@ -105,7 +99,7 @@ static void igd_init(struct device *dev) gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED); } -#endif /* CONFIG_CHROMEOS */ +#endif } static struct device_operations igd_ops = {

1 0

New patch to review for coreboot: skylake: Clean up chip.h
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11563 -gerrit commit c0cf178cc2f33a952cdb6dd1ef0b2c726a81045a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:05:59 2015 -0700 skylake: Clean up chip.h Remove config options that do not apply and are unused on skylake. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3224b89e310909c2836ef2c669c6b2ee826b1b28 Original-Change-Id: I2b4fe85f78480eac5635e78ce4e848f73967bd27 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297740 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/chip.h | 33 +++++++-------------------------- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index e962b37..9b43b7f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -60,23 +60,6 @@ struct soc_intel_skylake_config { uint32_t gen3_dec; uint32_t gen4_dec; - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -100,15 +83,6 @@ struct soc_intel_skylake_config { u32 gpu_cpu_backlight; u32 gpu_pch_backlight; - /* - * Graphics CD Clock Frequency - * 0 = 337.5MHz - * 1 = 450MHz - * 2 = 540MHz - * 3 = 675MHz - */ - int cdclk; - /* Enable S0iX support */ int s0ix_enable; @@ -167,6 +141,13 @@ struct soc_intel_skylake_config { /* Audio related */ u8 EnableAzalia; u8 DspEnable; + + /* + * I/O Buffer Ownership: + * 0: HD-A Link + * 1 Shared, HD-A Link and I2S Port + * 3: I2S Ports + */ u8 IoBufferOwnership; /* Trace Hub function */

1 0

New patch to review for coreboot: kunimitsu: Clean up devicetree.cb
by Patrick Georgi 07 Sep '15

07 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11562 -gerrit commit ff1bc7d2b9dac92a7be1f5fea9c9fafe9f2a35dd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 3 16:05:00 2015 -0700 kunimitsu: Clean up devicetree.cb Fix the PCI device list comments to be consistent between mainboards and remove unused and incorrect register settings. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8 Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297339 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/devicetree.cb | 182 ++++++++++++---------------- 1 file changed, 79 insertions(+), 103 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 5cc4f2e..f1480f3 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -1,132 +1,104 @@ chip soc/intel/skylake - # SerialIO device modes - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoPci, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoPci, \ - }" - - register "PortUsb20Enable[0]" = "1" # Type-C Port 1 - register "PortUsb20Enable[1]" = "1" # Type-C Port 2 - register "PortUsb20Enable[2]" = "1" # Bluetooth - register "PortUsb20Enable[4]" = "1" # Type-A Port (card) - register "PortUsb20Enable[6]" = "1" # Camera - register "PortUsb20Enable[8]" = "1" # Type-A Port (board) - - register "PortUsb30Enable[0]" = "1" # Type-C Port 1 - register "PortUsb30Enable[1]" = "1" # Type-C Port 2 - register "PortUsb30Enable[2]" = "1" # Type-A Port (card) - register "PortUsb30Enable[3]" = "1" # Type-A Port (board) - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # Pcie RootPort - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" + # Enable deep Sx states + register "deep_s3_enable" = "1" + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration - register "gpe0_en_1" = "0x00000000" - - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command range is in 0x800-0x8ff + register "gen1_dec" = "0x00fc0801" - # Memory related + # FSP Configuration register "ProbelessTrace" = "0" - - # Lan register "EnableLan" = "0" - - # SATA related register "EnableSata" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "SsicPortEnable" = "0" - - # Audio related register "EnableAzalia" = "1" - register "EnableTraceHub" = "0" register "DspEnable" = "1" - - # I/O Buffer Ownership: - # 0: HD-A Link - # 1 Shared, HD-A Link and I2S Port - # 3: I2S Ports register "IoBufferOwnership" = "3" - - # SMBUS + register "EnableTraceHub" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" register "SmbusEnable" = "1" - - # Camera register "Cio2Enable" = "0" - - # eMMC register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" - - # Integrated Sensor register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" - # Enable deep Sx states - register "deep_s3_enable" = "0" - register "deep_s5_enable" = "1" + # Enable Root port 1 and 5. + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "2" - # CPU Thermal participant device - register "Device4Enable" = "1" + register "PortUsb20Enable[0]" = "1" # Type-C Port 1 + register "PortUsb20Enable[1]" = "1" # Type-C Port 2 + register "PortUsb20Enable[2]" = "1" # Bluetooth + register "PortUsb20Enable[4]" = "1" # Type-A Port (card) + register "PortUsb20Enable[6]" = "1" # Camera + register "PortUsb20Enable[8]" = "1" # Type-A Port (board) - # XDCI controller - register "XdciEnable" = "0" + register "PortUsb30Enable[0]" = "1" # Type-C Port 1 + register "PortUsb30Enable[1]" = "1" # Type-C Port 2 + register "PortUsb30Enable[2]" = "1" # Type-A Port (card) + register "PortUsb30Enable[3]" = "1" # Type-A Port (board) - device cpu_cluster 0 on + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ + }" + + device cpu_cluster 0 on device lapic 0 on end end device domain 0 on - # Refered from SKL EDS Vol 1 : Page No: 31-32 device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB 3.0 xHCI Controller - device pci 14.1 off end # USB Device Controller (OTG) + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C Controller #0 - device pci 15.1 on end # I2C Controller #1 - device pci 15.2 on end # I2C Controller #2 - device pci 15.3 on end # I2C Controller #3 + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE Redirection (IDE-R) - device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection - device pci 16.4 off end # Management Engine Intel MEI #3 - device pci 17.0 off end # SATA Controller - device pci 19.0 on end # UART Controller #2 - device pci 19.1 on end # I2C Controller #5 - device pci 19.2 on end # I2C Controller #4 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # I2C #4 device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 @@ -140,20 +112,24 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.2 on end # SPI #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 on end # SDCard device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end chip ec/google/chromeec device pnp 0c09.0 on end end end # LPC Interface device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech) - device pci 1f.4 on end # SMBus Controller - device pci 1f.5 on end # SPI - device pci 1f.6 off end # GbE Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE end end

1 0

← Newer
1
...
57
58
59
60
61
62
63
...
86
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2015