coreboot-gerrit June 2015

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Patch set updated for coreboot: 3b37d67 AMD Merlin Falcon: Add CPU subdirectory files for new AMD processor
by WANG Siyuan 05 Jun '15

05 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10417 -gerrit commit 3b37d67cb6068857d78703ca91af4ce22114d599 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed May 20 14:36:06 2015 +0800 AMD Merlin Falcon: Add CPU subdirectory files for new AMD processor This adds the AMD Family 15h model 60h CPU. S3 suspend/resume currently is not supported. Tested on the amd/bettong platform. Change-Id: I5dea55a5664d29c07a54937ed1e5c2f84715d8ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/cpu/amd/pi/00660F01/Kconfig | 73 ++++++++++++++++ src/cpu/amd/pi/00660F01/Makefile.inc | 31 +++++++ src/cpu/amd/pi/00660F01/acpi/cpu.asl | 82 ++++++++++++++++++ src/cpu/amd/pi/00660F01/chip_name.c | 24 ++++++ src/cpu/amd/pi/00660F01/fixme.c | 98 +++++++++++++++++++++ src/cpu/amd/pi/00660F01/model_15_init.c | 145 ++++++++++++++++++++++++++++++++ src/cpu/amd/pi/Kconfig | 2 + src/cpu/amd/pi/Makefile.inc | 1 + 8 files changed, 456 insertions(+) diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig new file mode 100644 index 0000000..103e978 --- /dev/null +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -0,0 +1,73 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_PI_00660F01 + bool + select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_PI_00660F01 + +config CPU_ADDR_BITS + int + default 48 + +config CPU_SOCKET_TYPE + hex + default 0x10 + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x100000 + +config HAVE_INIT_TIMER + bool + default y + +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0xA1000 + +endif diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc new file mode 100644 index 0000000..d10c94f --- /dev/null +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += fixme.c +ramstage-y += fixme.c +ramstage-y += chip_name.c +ramstage-y += model_15_init.c + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl new file mode 100644 index 0000000..9d1a75b --- /dev/null +++ b/src/cpu/amd/pi/00660F01/acpi/cpu.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Processor Object + * + */ +Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique number for this processor */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } +} /* End _PR scope */ diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c new file mode 100644 index 0000000..bb536e3 --- /dev/null +++ b/src/cpu/amd/pi/00660F01/chip_name.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations cpu_amd_pi_00660F01_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c new file mode 100644 index 0000000..01d9e85 --- /dev/null +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include "amdlib.h" + +void amd_initcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + +void amd_initmmio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); +} diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c new file mode 100644 index 0000000..4d742a7 --- /dev/null +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/amdfam15.h> +#include <arch/acpi.h> +#include <cpu/amd/pi/s3_resume.h> + +#include <amdlib.h> +#include <PspBaseLib.h> + +void PSPProgBar3Msr(void *Buffer); + +void PSPProgBar3Msr(void *Buffer) +{ + u32 Bar3Addr; + u64 Tmp64; + /* Get Bar3 Addr */ + Bar3Addr = PspLibPciReadPspConfig (0x20); + Tmp64 = Bar3Addr; + printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); + LibAmdMsrWrite (0xC00110A2, &Tmp64, NULL); + LibAmdMsrRead (0xC00110A2, &Tmp64, NULL); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + if (acpi_is_wakeup()) + restore_mtrr(); + + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + PSPProgBar3Msr(NULL); + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x660f00 }, + { X86_VENDOR_AMD, 0x660f01 }, + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 50e0f26..6bf3785 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -21,6 +21,7 @@ config CPU_AMD_PI bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 + default y if CPU_AMD_PI_00660F01 default n select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 @@ -76,3 +77,4 @@ endif # CPU_AMD_PI source src/cpu/amd/pi/00630F01/Kconfig source src/cpu/amd/pi/00730F01/Kconfig +source src/cpu/amd/pi/00660F01/Kconfig diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 2ce5a4d..5a407b2 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 romstage-y += s3_resume.c ramstage-y += s3_resume.c

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Patch set updated for coreboot: ff82a5e AMD Merlin Falcon: Add binary PI vendorcode files
by WANG Siyuan 05 Jun '15

05 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10416 -gerrit commit ff82a5e8e0256580c39cbee8b2f7357ffd6cce41 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed May 20 14:28:51 2015 +0800 AMD Merlin Falcon: Add binary PI vendorcode files Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/vendorcode/amd/pi/00660F01/Kconfig | 59 ++ src/vendorcode/amd/pi/00660F01/Lib/amdlib.c | 1417 +++++++++++++++++++++++++++ src/vendorcode/amd/pi/00660F01/Lib/amdlib.h | 396 ++++++++ src/vendorcode/amd/pi/00660F01/Makefile.inc | 127 +++ src/vendorcode/amd/pi/Kconfig | 1 + src/vendorcode/amd/pi/Makefile.inc | 1 + 6 files changed, 2001 insertions(+) diff --git a/src/vendorcode/amd/pi/00660F01/Kconfig b/src/vendorcode/amd/pi/00660F01/Kconfig new file mode 100644 index 0000000..7d64d38 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Kconfig @@ -0,0 +1,59 @@ +# +# Copyright (c) 2013 - 2014, Sage Electronic Engineering, LLC +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +if CPU_AMD_PI_00660F01 + +config AGESA_BINARY_PI_DEFAULTS # dummy + def_bool y + depends on CPU_AMD_PI_00660F01 + select AGESA_BINARY_PI_LOCATION_DEFAULT_SELECTED + select AGESA_BINARY_PI_PATH_DEFAULT_SELECTED + select AGESA_BINARY_PI_FILE_DEFAULT_SELECTED + +config AGESA_BINARY_PI_PATH_DEFAULT + string + depends on CPU_AMD_PI_00660F01 + default "3rdparty/blobs/pi/amd/00660F01" + help + The default binary file name to use for AMD platform initialization. + +config AGESA_BINARY_PI_FILE_DEFAULT + string + depends on CPU_AMD_PI_00660F01 + default "FP4/AGESA.bin" + help + The default binary file name to use for AMD platform initialization. + +config AGESA_BINARY_PI_LOCATION_DEFAULT + hex + depends on CPU_AMD_PI_00660F01 + default 0xFFE00000 + help + The default ROM address at which to store the binary Platform + Initialization code. + +endif diff --git a/src/vendorcode/amd/pi/00660F01/Lib/amdlib.c b/src/vendorcode/amd/pi/00660F01/Lib/amdlib.c new file mode 100644 index 0000000..5e85f6b --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Lib/amdlib.c @@ -0,0 +1,1417 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e \$Revision: 48409 $ @e \$Date: 2011-03-08 11:19:40 -0600 (Tue, 08 Mar 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2011, Advanced Micro Devices, Inc. + * 2013 - 2014, Sage Electronic Engineering, LLC + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ + +#include <AGESA.h> +#include <cpuRegisters.h> +#include <Filecode.h> +#include <Ids.h> +#include <Porting.h> +#include "amdlib.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#if !defined(AMDLIB_OPTIMIZE) + #define AMDLIB_OPTIMIZE +#endif + +#define FILECODE LIB_AMDLIB_FILECODE + +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ); +VOID +IdsOutPort ( + IN UINT32 Addr, + IN UINT32 Value, + IN UINT32 Flag + ); + +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ); + +UINT8 +ReadNumberOfCpuCores( + void + ); + +AMDLIB_OPTIMIZE +UINT8 +ReadIo8 ( + IN UINT16 Address + ) +{ + return __inbyte (Address); +} + +AMDLIB_OPTIMIZE +UINT16 +ReadIo16 ( + IN UINT16 Address + ) +{ + return __inword (Address); +} + +AMDLIB_OPTIMIZE +UINT32 +ReadIo32 ( + IN UINT16 Address + ) +{ + return __indword (Address); +} + +AMDLIB_OPTIMIZE +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ) +{ + __outbyte (Address, Data); +} + +AMDLIB_OPTIMIZE +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ) +{ + __outword (Address, Data); +} + +AMDLIB_OPTIMIZE +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ) +{ + __outdword (Address, Data); +} + +AMDLIB_OPTIMIZE +STATIC +UINT64 SetFsBase ( + UINT64 address + ) +{ + UINT64 hwcr; + hwcr = __readmsr (0xC0010015); + __writemsr (0xC0010015, hwcr | 1 << 17); + __writemsr (0xC0000100, address); + return hwcr; +} + +AMDLIB_OPTIMIZE +STATIC +VOID +RestoreHwcr ( + UINT64 + value + ) +{ + __writemsr (0xC0010015, value); +} + +AMDLIB_OPTIMIZE +UINT8 +Read64Mem8 ( + IN UINT64 Address + ) +{ + UINT8 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT8 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsbyte (0); + RestoreHwcr (hwcrSave); + return dataRead; +} + +AMDLIB_OPTIMIZE +UINT16 +Read64Mem16 ( + IN UINT64 Address + ) +{ + UINT16 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT16 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsword (0); + RestoreHwcr (hwcrSave); + return dataRead; +} + +AMDLIB_OPTIMIZE +UINT32 +Read64Mem32 ( + IN UINT64 Address + ) +{ + UINT32 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT32 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsdword (0); + RestoreHwcr (hwcrSave); + return dataRead; + } + +AMDLIB_OPTIMIZE +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT8 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsbyte (0, Data); + RestoreHwcr (hwcrSave); + } +} + +AMDLIB_OPTIMIZE +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT16 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsword (0, Data); + RestoreHwcr (hwcrSave); + } +} + +AMDLIB_OPTIMIZE +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT32 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsdword (0, Data); + RestoreHwcr (hwcrSave); + } +} + +AMDLIB_OPTIMIZE +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ) +{ + *Value = 0; + switch (RegNum){ + case CR4_REG: + *Value = __readcr4 (); + break; + case DR0_REG: + *Value = __readdr (0); + break; + case DR1_REG: + *Value = __readdr (1); + break; + case DR2_REG: + *Value = __readdr (2); + break; + case DR3_REG: + *Value = __readdr (3); + break; + case DR7_REG: + *Value = __readdr (7); + break; + default: + *Value = -1; + break; + } +} + +AMDLIB_OPTIMIZE +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ) +{ + switch (RegNum){ + case CR4_REG: + __writecr4 (Value); + break; + case DR0_REG: + __writedr (0, Value); + break; + case DR1_REG: + __writedr (1, Value); + break; + case DR2_REG: + __writedr (2, Value); + break; + case DR3_REG: + __writedr (3, Value); + break; + case DR7_REG: + __writedr (7, Value); + break; + default: + break; + } +} + +AMDLIB_OPTIMIZE +VOID +LibAmdWriteBackInvalidateCache ( + void + ) +{ + __wbinvd (); +} + +AMDLIB_OPTIMIZE +VOID +LibAmdHDTBreakPoint ( + void + ) +{ + __writemsr (0xC001100A, __readmsr (0xC001100A) | 1); + __debugbreak (); // do you really need icebp? If so, go back to asm code +} + +AMDLIB_OPTIMIZE +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ) +{ + UINTN Index; + for (Index = 0; Index < 32; Index++){ + if (value & (1 << Index)) break; + } + return (UINT8) Index; +} + +AMDLIB_OPTIMIZE +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value +) +{ + UINTN Index; + for (Index = 31; Index >= 0; Index--){ + if (value & (1 << Index)) break; + } + return (UINT8) Index; +} + +AMDLIB_OPTIMIZE +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + if ((MsrAddress == 0xFFFFFFFF) || (MsrAddress == 0x00000000)) { + IdsErrorStop(MsrAddress); + } + *Value = __readmsr (MsrAddress); +} + +AMDLIB_OPTIMIZE +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __writemsr (MsrAddress, *Value); +} + +AMDLIB_OPTIMIZE +void LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA* Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} + +AMDLIB_OPTIMIZE +UINT64 +ReadTSC ( + void + ) +{ + return __rdtsc (); +} + +AMDLIB_OPTIMIZE +VOID +LibAmdSimNowEnterDebugger ( + void + ) +{ + STATIC CONST UINT8 opcode [] = {0x60, // pushad + 0xBB, 0x02, 0x00, 0x00, 0x00, // mov ebx, 2 + 0xB8, 0x0B, 0xD0, 0xCC, 0xBA, // mov eax, 0xBACCD00B + 0x0F, 0xA2, // cpuid + 0x61, // popad + 0xC3 // ret + }; + ((VOID (*)(VOID)) (size_t) opcode) (); // call the function +} + +AMDLIB_OPTIMIZE +VOID +IdsOutPort ( + IN UINT32 Addr, + IN UINT32 Value, + IN UINT32 Flag + ) +{ + __outdword ((UINT16) Addr, Value); +} + +AMDLIB_OPTIMIZE +VOID +StopHere ( + void + ) +{ + VOLATILE UINTN x = 1; + while (x); +} + +AMDLIB_OPTIMIZE +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ) +{ + UINT64 hwcrSave; + UINT8 *address32; + UINTN Index; + address32 = 0; + hwcrSave = SetFsBase (Address); + for (Index = 0; Index < Count; Index++){ + _mm_mfence (); + _mm_clflush_fs (&address32 [Index * 64]); + } + RestoreHwcr (hwcrSave); +} + + +AMDLIB_OPTIMIZE +VOID +LibAmdFinit( + void + ) +{ + /* TODO: finit */ + __asm__ volatile ("finit"); +} +/*---------------------------------------------------------------------------------------*/ +/** + * Read IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to save data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = ReadIo8 (IoAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = ReadIo16 (IoAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = ReadIo32 (IoAddress); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + WriteIo8 (IoAddress, *(UINT8 *) Value); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + WriteIo16 (IoAddress, *(UINT16 *) Value); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + WriteIo32 (IoAddress, *(UINT32 *) Value); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * IO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData; + UINT32 TempMask; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll IO register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data Data to compare + * @param[in] DataMask And mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData; + UINT32 TempMask; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = Read64Mem8 (MemAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = Read64Mem16 (MemAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = Read64Mem32 (MemAddress); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Write64Mem8 (MemAddress, *((UINT8 *) Value)); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Write64Mem16 (MemAddress, *((UINT16 *) Value)); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Write64Mem32 (MemAddress, *((UINT32 *) Value)); + break; + default: + ASSERT (FALSE); + break; + } +} +/*---------------------------------------------------------------------------------------*/ +/** + * Memory/MMIO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData; + UINT32 TempMask; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll Mmio + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + //IDS_HDT_CONSOLE (LIB_PCI_RD, "~PCI RD %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader); + //IDS_HDT_CONSOLE (LIB_PCI_RD, "~MMIO RD %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader); + //IDS_HDT_CONSOLE (LIB_PCI_WR, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "LibAmdPciWrite mmio\n"); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * PCI read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data OR Data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll PCI config space register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get MMIO base address for PCI accesses + * + * @param[out] MmioAddress PCI MMIO base address + * @param[out] MmioSize Size of region in bytes + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE MmioAddress/MmioSize are valid + */ +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN MmioIsEnabled; + UINT32 EncodedSize; + UINT64 LocalMsrRegister; + + ASSERT (StdHeader != NULL); + + MmioIsEnabled = FALSE; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + if ((LocalMsrRegister & BIT0) != 0) { + *MmioAddress = LocalMsrRegister & 0xFFFFFFFFFFF00000; + EncodedSize = (UINT32) ((LocalMsrRegister & 0x3C) >> 2); + *MmioSize = ((1 << EncodedSize) * 0x100000); + MmioIsEnabled = TRUE; + } + return MmioIsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[out] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + LibAmdPciRead (AccessWidth32, Address, Value, StdHeader); + *Value >>= Lowbit; // Shift + + // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN CONST UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 Mask; + + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32) 0xFFFFFFFF; + } + + LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader); + Temp &= ~(Mask << Lowbit); + Temp |= (*Value & Mask) << Lowbit; + LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locate next capability pointer + * + * Given a SBDFO this routine will find the next PCI capabilities list entry. + * if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is + * returned. + * To start a new search from the head of the list, specify a SBDFO with an offset of zero. + * + * @param[in,out] Address Pci address + * @param[in] StdHeader Standard configuration header + */ + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Base; + UINT32 Offset; + UINT32 Temp; + PCI_ADDR TempAddress; + + ASSERT (Address != NULL); + ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO); + + Base.AddressValue = Address->AddressValue; + Offset = Base.Address.Register; + Base.Address.Register = 0; + + Address->AddressValue = (UINT32) ILLEGAL_SBDFO; + + // Verify that the SBDFO points to a valid PCI device SANITY CHECK + LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader); + if (Temp == 0xFFFFFFFF) { + ASSERT (FALSE); + return; // There is no device at this address + } + + // Verify that the device supports a capability list + TempAddress.AddressValue = Base.AddressValue + 0x04; + LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader); + if (Temp == 0) { + return; // This PCI device does not support capability lists + } + + if (Offset != 0) { + // If we are continuing on an existing list + TempAddress.AddressValue = Base.AddressValue + Offset; + LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader); + } else { + // We are starting on a new list + TempAddress.AddressValue = Base.AddressValue + 0x34; + LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader); + } + + if (Temp == 0) { + return; // We have reached the end of the capabilities list + } + + // Error detection and recovery- The statement below protects against + // PCI devices with broken PCI capabilities lists. Detect a pointer + // that is not uint32 aligned, points into the first 64 reserved DWORDs + // or points back to itself. + if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) { + ASSERT (FALSE); + return; + } + + Address->AddressValue = Base.AddressValue + Temp; + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set memory with value + * + * + * @param[in,out] Destination Pointer to memory range + * @param[in] Value Value to set memory with + * @param[in] FillLength Size of the memory range + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + ASSERT (StdHeader != NULL); + Dest = Destination; + while ((FillLength--) != 0) { + *Dest++ = Value; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Copy memory + * + * + * @param[in,out] Destination Pointer to destination buffer + * @param[in] Source Pointer to source buffer + * @param[in] CopyLength buffer length + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN CONST VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + CONST UINT8 *SourcePtr; + ASSERT (StdHeader != NULL); + Dest = Destination; + SourcePtr = Source; + while ((CopyLength--) != 0) { + *Dest++ = *SourcePtr++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Verify checksum of binary image (B1/B2/B3) + * + * + * @param[in] ImagePtr Pointer to image start + * @retval TRUE Checksum valid + * @retval FALSE Checksum invalid + */ +BOOLEAN +LibAmdVerifyImageChecksum ( + IN CONST VOID *ImagePtr + ) +{ + // Assume ImagePtr points to the binary start ($AMD) + // Checksum is on an even boundary in AMD_IMAGE_HEADER + + UINT16 Sum; + UINT32 i; + + Sum = 0; + + i = ((AMD_IMAGE_HEADER*) ImagePtr)->ImageSize; + + while (i > 1) { + Sum = Sum + *((UINT16 *)ImagePtr); + ImagePtr = (VOID *) ((UINT8 *)ImagePtr + 2); + i = i - 2; + } + if (i > 0) { + Sum = Sum + *((UINT8 *) ImagePtr); + } + + return (Sum == 0)?TRUE:FALSE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locate AMD binary image that contain specific module + * + * + * @param[in] StartAddress Pointer to start range + * @param[in] EndAddress Pointer to end range + * @param[in] Alignment Image address alignment + * @param[in] ModuleSignature Module signature. + * @retval NULL if image not found + * @retval pointer to image header + */ +CONST VOID * +LibAmdLocateImage ( + IN CONST VOID *StartAddress, + IN CONST VOID *EndAddress, + IN UINT32 Alignment, + IN CONST CHAR8 ModuleSignature[8] + ) + +{ + CONST UINT8 *CurrentPtr = StartAddress; + AMD_MODULE_HEADER *ModuleHeaderPtr; + CONST UINT64 SearchStr = *((UINT64*)ModuleSignature); + + // Search from start to end incrementing by alignment + while ((CurrentPtr >= (UINT8 *) StartAddress) && (CurrentPtr < (UINT8 *) EndAddress)) { + // First find a binary image + if (IMAGE_SIGNATURE == *((UINT32 *) CurrentPtr)) { + // TODO Figure out a way to fix the AGESA binary checksum +// if (LibAmdVerifyImageChecksum (CurrentPtr)) { + // If we have a valid image, search module linked list for a match + ModuleHeaderPtr = (AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset); + while ((ModuleHeaderPtr != NULL) && + (MODULE_SIGNATURE == *((UINT32*)&(ModuleHeaderPtr->ModuleHeaderSignature)))) { + if (SearchStr == *((UINT64*)&(ModuleHeaderPtr->ModuleIdentifier))) { + return CurrentPtr; + } + ModuleHeaderPtr = (AMD_MODULE_HEADER *)ModuleHeaderPtr->NextBlock; + } +// } + } + CurrentPtr += Alignment; + } + return NULL; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] StdHeader Standard configuration header (Optional) + */ + +// Returns the package type mask for the processor +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProcessorPackageType; + CPUID_DATA CpuId; + + LibAmdCpuidRead (0x80000001, &CpuId, StdHeader); + ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + return (UINT32) (1 << ProcessorPackageType); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @param[in] Data data + * @param[in] DataMask data + * @param[out] TemData typecast data + * @param[out] TempDataMask typecast data + */ + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *TemData = (UINT32)*(UINT8 *) Data; + *TempDataMask = (UINT32)*(UINT8 *) DataMask; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *TemData = (UINT32)*(UINT16 *) Data; + *TempDataMask = (UINT32)*(UINT16 *) DataMask; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *TemData = *(UINT32 *) Data; + *TempDataMask = *(UINT32 *) DataMask; + break; + default: + IDS_ERROR_TRAP; + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @retval Width in number of bytes + */ + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ) +{ + UINT8 Width; + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Width = 1; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Width = 2; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Width = 4; + break; + case AccessWidth64: + case AccessS3SaveWidth64: + Width = 8; + break; + default: + Width = 0; + IDS_ERROR_TRAP; + break; + } + return Width; +} + +AMDLIB_OPTIMIZE +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} + +AMDLIB_OPTIMIZE +UINT8 +ReadNumberOfCpuCores( + void + ) +{ + CPUID_DATA Value; + CpuidRead (0x80000008, &Value); + return Value.ECX_Reg & 0xff; +} + +BOOLEAN +IdsErrorStop ( + IN UINT32 FileCode + ) +{ + struct POST { + UINT16 deadlo; + UINT32 messagelo; + UINT16 deadhi; + UINT32 messagehi; + } post = {0xDEAD, FileCode, 0xDEAD, FileCode}; + UINT16 offset = 0; + UINT16 j; + + while(1) { + offset %= sizeof(struct POST) / 2; + WriteIo32(80, *((UINT32*)(&post+offset))); + ++offset; + for (j=0; j<250; ++j) { + ReadIo8(80); + } + } +} diff --git a/src/vendorcode/amd/pi/00660F01/Lib/amdlib.h b/src/vendorcode/amd/pi/00660F01/Lib/amdlib.h new file mode 100644 index 0000000..f5eab0a --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Lib/amdlib.h @@ -0,0 +1,396 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e \$Revision: 85030 $ @e \$Date: 2012-12-26 00:20:10 -0600 (Wed, 26 Dec 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * 2013 - 2014, Sage Electronic Engineering, LLC + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + **/ + +#ifndef _AMD_LIB_H_ +#define _AMD_LIB_H_ + +#include "Porting.h" +#include "AMD.h" + +#define IOCF8 0xCF8 +#define IOCFC 0xCFC + +// Reg Values for ReadCpuReg and WriteCpuReg +#define CR4_REG 0x04 +#define DR0_REG 0x10 +#define DR1_REG 0x11 +#define DR2_REG 0x12 +#define DR3_REG 0x13 +#define DR7_REG 0x17 + +// PROTOTYPES FOR amdlib32.asm +UINT8 +ReadIo8 ( + IN UINT16 Address + ); + +UINT16 +ReadIo16 ( + IN UINT16 Address + ); + +UINT32 +ReadIo32 ( + IN UINT16 Address + ); + +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ); + +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ); + +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ); + +UINT8 +Read64Mem8 ( + IN UINT64 Address + ); + +UINT16 +Read64Mem16 ( + IN UINT64 Address + ); + +UINT32 +Read64Mem32 ( + IN UINT64 Address + ); + +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ); + +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ); + +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ); + +UINT64 +ReadTSC ( + void + ); + +// MSR +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// IO +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Memory or MMIO +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// PCI +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN CONST UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// CPUID +VOID +LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Utility Functions +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN CONST VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +CONST VOID * +LibAmdLocateImage ( + IN CONST VOID *StartAddress, + IN CONST VOID *EndAddress, + IN UINT32 Alignment, + IN CONST CHAR8 ModuleSignature[8] + ); + +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +LibAmdVerifyImageChecksum ( + IN CONST VOID *ImagePtr + ); + +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value + ); +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ); + +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ); +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ); + +VOID +LibAmdWriteBackInvalidateCache ( + void + ); + +VOID +LibAmdSimNowEnterDebugger ( + void + ); + +VOID +LibAmdHDTBreakPoint ( + void + ); + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ); + +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ); + +VOID +StopHere ( + void + ); + +VOID +LibAmdFinit ( + void + ); + +VOID +LibAmdFnclex ( + void + ); + +VOID +LibAmdReadMxcsr ( + OUT UINT32 *Value + ); + +VOID +LibAmdWriteMxcsr ( + IN UINT32 *Value + ); + +#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Makefile.inc b/src/vendorcode/amd/pi/00660F01/Makefile.inc new file mode 100644 index 0000000..50ebe97 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Makefile.inc @@ -0,0 +1,127 @@ +#***************************************************************************** +# +# Copyright (c) 2012, Advanced Micro Devices, Inc. +# 2013 - 2014, Sage Electronic Engineering, LLC +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +# AGESA V5 Files +AGESA_ROOT = $(call strip_quotes,$(src)/../$(CONFIG_AGESA_BINARY_PI_PATH)) + +AGESA_INC = -I$(obj) + +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(AGESA_ROOT)/binaryPI +AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)/Include +AGESA_INC += -I$(src)/vendorcode/amd/pi/00660F01 +AGESA_INC += -I$(src)/vendorcode/amd/pi/00660F01/Lib +AGESA_INC += -I$(AGESA_ROOT)/Proc +AGESA_INC += -I$(AGESA_ROOT)/Proc/Common +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature +AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch +AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Kern +AGESA_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib + +AGESA_INC += -I$(src)/northbridge/amd/pi +AGESA_INC += -I$(src)/southbridge/amd/pi/hudson + +AGESA_INC += -I$(src)/arch/x86/include +AGESA_INC += -I$(src)/include + +AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_32 += $(AGESA_CFLAGS) + +export AGESA_ROOT := $(AGESA_ROOT) +export AGESA_INC := $(AGESA_INC) +export AGESA_CFLAGS := $(AGESA_CFLAGS) + +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) + +####################################################################### + +define create_agesa_cp_template + +# $1 AGESA source file +# $2 AGESA copy-to location +$(agesa_src_path)/$(notdir $2): $2 $(agesa_src_path) + @printf " AGESA Copying $$(notdir $2) => $$(@D)\n" + if [ ! -r $(agesa_src_path)/$(notdir $2) ]; then \ + cp -uf $2 $$(@D); \ + fi + +$(agesa_obj_path)/$1.libagesa.o: $(agesa_src_path)/$(notdir $2) $(obj)/config.h $(src)/include/kconfig.h $(agesa_obj_path) + @printf " CC $(subst $(agesa_obj_path)/,,$$(@))\n" + $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ + $(AGESA_INC) \ + -include $(obj)/config.h -include $(src)/include/kconfig.h \ + -o $$@ \ + $(agesa_src_path)/$(notdir $2) + +endef + +agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/00660F01/Lib/*.[cS]) +agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) +agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS]) +agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) +agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) + +classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa +$(eval $(call create_class_compiler,libagesa,x86_32)) + +agesa_src_files := $(strip $(sort $(foreach file,$(strip $(agesa_raw_files)),$(call strip_quotes,$(file))))) +agesa_obj_path := $(strip $(obj)/vendorcode/amd) +agesa_src_path := $(strip $(obj)/agesa) +agesa_src_copies := $(strip $(foreach file,$(agesa_src_files),$(agesa_obj_path)/$(notdir $(file)))) +agesa_obj_copies := $(strip $(agesa_src_copies:.c=.libagesa.o)) + +$(agesa_src_path): + mkdir -p $@ + +$(agesa_obj_path): + mkdir -p $@ + +$(foreach file,$(strip $(agesa_src_files)),$(eval $(call create_agesa_cp_template,$(basename $(notdir $(file))),$(file)))) + +$(obj)/agesa/libagesa.00660F01.a: $(agesa_obj_copies) + @printf " AGESA $(subst $(agesa_obj_path)/,,$(@))\n" + ar rcs $@ $+ + +romstage-libs += $(obj)/agesa/libagesa.00660F01.a +ramstage-libs += $(obj)/agesa/libagesa.00660F01.a + +####################################################################### + +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += AGESA +AGESA-file := $(CONFIG_AGESA_BINARY_PI_PATH)/$(CONFIG_AGESA_BINARY_PI_FILE) +AGESA-type := raw +AGESA-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index b881fd0..7d847f2 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -1,2 +1,3 @@ source src/vendorcode/amd/pi/00630F01/Kconfig source src/vendorcode/amd/pi/00730F01/Kconfig +source src/vendorcode/amd/pi/00660F01/Kconfig diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4f2a9d0..dc0a1bd 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -1,2 +1,3 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 +subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01

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Patch set updated for coreboot: f31ec69 southbridge/ibexpeak: use new ssdt sata port generator
by Alexander Couzens 05 Jun '15

05 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710 -gerrit commit f31ec6948e3ab5c7e89a60cf48fc9d1c1986dae3 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:23:00 2015 +0200 southbridge/ibexpeak: use new ssdt sata port generator Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/sata.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ccd16bf..f31f83c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 29d9240..be2b961 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -26,6 +26,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -249,6 +250,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -259,6 +265,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, + .acpi_fill_ssdt_generator = sata_fill_ssdt, .scan_bus = 0, .ops_pci = &sata_pci_ops, };

1 0

Patch set updated for coreboot: 716a05f southbridge/bd82x6x: use new ssdt sata port generator
by Alexander Couzens 05 Jun '15

05 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709 -gerrit commit 716a05f3518842f5c7f12fb230d0ae39eea304c8 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 ----------------------------- src/southbridge/intel/bd82x6x/sata.c | 8 +++++ 3 files changed, 9 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 6190879..3a68fec 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index fb685a3..00d3010 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -26,56 +26,4 @@ Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1cdc5e2..18e5a08 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -255,6 +261,8 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator + = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0,

1 0

Patch set updated for coreboot: 3aacee8 acpi/sata: add generic sata ssdt port generator
by Alexander Couzens 05 Jun '15

05 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9708 -gerrit commit 3aacee8cf205d06d07f6c663e3e87075d2d3b6bf Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:03:26 2015 +0200 acpi/sata: add generic sata ssdt port generator generate_sata_ssdt_ports() generates ports based on sata enable map Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- Makefile.inc | 2 +- src/Kconfig | 2 ++ src/acpi/Kconfig | 6 +++++ src/acpi/Makefile.inc | 1 + src/acpi/sata.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/acpi/sata.h | 3 +++ 6 files changed, 74 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index d5ef301..f1475e6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,7 +52,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device +subdirs-y := src/lib src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode diff --git a/src/Kconfig b/src/Kconfig index 5aa76fb..f685cc3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -330,6 +330,8 @@ config RAM_CODE_SUPPORT endmenu +source "src/acpi/Kconfig" + source "src/mainboard/Kconfig" source "src/arch/*/Kconfig" diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig new file mode 100644 index 0000000..e025f99 --- /dev/null +++ b/src/acpi/Kconfig @@ -0,0 +1,6 @@ + +config ACPI_SATA_GENERATOR + bool + default n + help + Use acpi sata port generator. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc new file mode 100644 index 0000000..53ac679 --- /dev/null +++ b/src/acpi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c diff --git a/src/acpi/sata.c b/src/acpi/sata.c new file mode 100644 index 0000000..b488574 --- /dev/null +++ b/src/acpi/sata.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "sata.h" + +#include <arch/acpi.h> +#include <arch/acpigen.h> + +/* e.g. + * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); + * generates: + * Scope (\_SB.PCI0.SATA) + * { + * Device (PRT0) + * { + * Name (_ADR, 0x0000FFFF) // _ADR: Address + * } + * + * Device (PRT1) + * { + * Name (_ADR, 0x0001FFFF) // _ADR: Address + * } + * } + */ +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map) +{ + int i; + int bit; + char port_name[4] = "PRT0"; + + acpigen_write_scope(scope); + + /* generate a device for every enabled port */ + for (i = 0; i < 8; i++) { + bit = 1 << i; + if (!(bit & enable_map)) + continue; + + port_name[3] = '0' + i; + acpigen_write_device(port_name); + + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); + acpigen_pop_len(); /* close PRT%d */ + } + + acpigen_pop_len(); /* close scope */ +} diff --git a/src/acpi/sata.h b/src/acpi/sata.h new file mode 100644 index 0000000..b7f17b2 --- /dev/null +++ b/src/acpi/sata.h @@ -0,0 +1,3 @@ +#include <stdint.h> + +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map);

1 0

Patch set updated for coreboot: dd1cc75 device_ops: add device_t argument to write_acpi_tables
by Alexander Couzens 05 Jun '15

05 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9599 -gerrit commit dd1cc755a8913f64c8bbe7a0cd7f5e79d1e50636 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 22:28:37 2015 +0200 device_ops: add device_t argument to write_acpi_tables `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 4 ++-- src/arch/x86/include/arch/acpi.h | 2 +- src/include/device/device.h | 2 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 2 +- src/mainboard/amd/serengeti_cheetah/mainboard.h | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c | 3 ++- src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h | 2 +- src/mainboard/emulation/qemu-i440fx/acpi.h | 2 +- src/mainboard/getac/p470/acpi_tables.c | 4 +++- src/mainboard/getac/p470/mainboard.h | 3 ++- src/mainboard/iwill/dk8_htx/acpi_tables.c | 4 +++- src/mainboard/iwill/dk8_htx/mainboard.h | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 3 ++- src/northbridge/amd/agesa/family14/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15rl/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 ++- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 ++- src/northbridge/amd/amdfam10/acpi.c | 5 +++-- src/northbridge/amd/amdfam10/amdfam10.h | 3 ++- src/northbridge/amd/amdk8/acpi.c | 5 ++++- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 3 ++- src/northbridge/amd/pi/00730F01/northbridge.c | 3 ++- src/northbridge/intel/gm45/acpi.c | 4 +++- src/northbridge/intel/gm45/gm45.h | 8 +++++++- src/soc/intel/fsp_baytrail/acpi.c | 5 +++-- src/soc/intel/fsp_baytrail/baytrail/acpi.h | 3 ++- src/southbridge/intel/lynxpoint/lpc.c | 4 +++- 29 files changed, 63 insertions(+), 32 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index dd01e0c..4090a1d 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -508,7 +508,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } -unsigned long acpi_write_hpet(unsigned long current, acpi_rsdp_t *rsdp) +unsigned long acpi_write_hpet(device_t device, unsigned long current, acpi_rsdp_t *rsdp) { acpi_hpet_t *hpet; @@ -898,7 +898,7 @@ unsigned long write_acpi_tables(unsigned long start) for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { - current = dev->ops->write_acpi_tables(current, rsdp); + current = dev->ops->write_acpi_tables(dev, current, rsdp); ALIGN_CURRENT; } } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index be97db5..28f650c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -537,7 +537,7 @@ void acpi_create_slit(acpi_slit_t *slit, #if ENV_RAMSTAGE void acpi_create_hpet(acpi_hpet_t *hpet); -unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(device_t device); diff --git a/src/include/device/device.h b/src/include/device/device.h index b806859..076db13 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -56,7 +56,7 @@ struct device_operations { void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); + unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); #endif diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 225f897..b25f7e7 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -119,7 +119,7 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ssdtx; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.h b/src/mainboard/amd/serengeti_cheetah/mainboard.h index 80d8f2a..fc2dcaf 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.h @@ -1 +1 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index ac021d0..7b5be84 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -127,7 +127,8 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long current, +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_header_t *ssdtx; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h index 8f17804..b152b04 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h @@ -1,2 +1,2 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/emulation/qemu-i440fx/acpi.h b/src/mainboard/emulation/qemu-i440fx/acpi.h index c0d4e6e..f2ffdeb 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi.h +++ b/src/mainboard/emulation/qemu-i440fx/acpi.h @@ -1 +1 @@ -unsigned long northbridge_write_acpi_tables(unsigned long start); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start); diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index b6cd654..18b7151 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -110,7 +110,9 @@ unsigned long acpi_fill_madt(unsigned long current) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ecdt; diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index 45d961b..56f5455 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -1,4 +1,5 @@ struct acpi_rsdp; -unsigned long mainboard_write_acpi_tables(unsigned long start, +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 5767878..7c8835a 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -125,7 +125,9 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ssdtx; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.h b/src/mainboard/iwill/dk8_htx/mainboard.h index 80d8f2a..fc2dcaf 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.h +++ b/src/mainboard/iwill/dk8_htx/mainboard.h @@ -1 +1 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index ee291a5..ec1f493 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -832,7 +832,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 2cf4736..6d3a173 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -832,7 +832,8 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d42926f..5ad7ae3 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -527,7 +527,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 6c2e953..199843e 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index aef0d83..85b9799 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 192c3df..25f40b8 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 734ebb6..4b86e96 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -330,8 +330,9 @@ void northbridge_acpi_write_vars(device_t device) acpigen_pop_len(); } -unsigned long northbridge_write_acpi_tables(unsigned long current, - struct acpi_rsdp *rsdp) +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) { acpi_srat_t *srat; acpi_slit_t *slit; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 9213ed1..9461385 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1074,7 +1074,8 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(device_t device); diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 1bb1d83..10228cf 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -204,7 +204,10 @@ static unsigned long acpi_fill_slit(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long northbridge_write_acpi_tables( + device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_srat_t *srat; diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index 4d822e4..b874dd4 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -22,6 +22,6 @@ #include <arch/acpigen.h> void k8acpi_write_vars(device_t device); -unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index d21becf..acecb28 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -492,7 +492,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 2e46b16..3e5b2b2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -486,7 +486,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index a1cfdb5..daa5aed 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -109,7 +109,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) { unsigned long current; #if CONFIG_IOMMU diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index db3db00..cb946fc 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -25,6 +25,7 @@ #ifndef __ACPI__ +#include <rules.h> #include <stdint.h> typedef enum { @@ -435,8 +436,13 @@ u32 decode_igd_gtt_size(u32 gsm); void init_iommu(void); +#if ENV_RAMSTAGE +#include <device/device.h> + struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif + +#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 9b0d148..ed607b3 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -569,12 +569,13 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long southcluster_write_acpi_tables(unsigned long current, +unsigned long southcluster_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; - current = acpi_write_hpet(current, rsdp); + current = acpi_write_hpet(device, current, rsdp); ALIGN_CURRENT; ssdt2 = (acpi_header_t *)current; diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h index 1e60508..0cd978d 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/acpi.h +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -30,7 +30,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long southcluster_write_acpi_tables(unsigned long current, +unsigned long southcluster_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(device_t device); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 50f48cb..8308f41 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -786,7 +786,9 @@ static void southbridge_inject_dsdt(device_t dev) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +static unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) { unsigned long current; acpi_hpet_t *hpet;

1 0

Patch set updated for coreboot: afbdacb device_ops: add device_t argument to acpi_fill_ssdt_generator
by Alexander Couzens 05 Jun '15

05 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9598 -gerrit commit afbdacb86ec091e4edf7883b61f5626f945bf5ee Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 22:18:55 2015 +0200 device_ops: add device_t argument to acpi_fill_ssdt_generator `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 3 ++- src/cpu/intel/fsp_model_206ax/acpi.c | 2 +- src/cpu/intel/fsp_model_406dx/acpi.c | 2 +- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/include/device/device.h | 2 +- src/mainboard/lenovo/x200/mainboard.c | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdk8/acpi.c | 2 +- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/fsp_rangeley/acpi.c | 4 ++-- src/northbridge/intel/fsp_rangeley/northbridge.h | 8 +++++++- src/northbridge/intel/fsp_sandybridge/gma.c | 2 +- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/gma.c | 2 +- src/northbridge/intel/i945/gma.c | 2 +- src/northbridge/intel/nehalem/gma.c | 2 +- src/northbridge/intel/sandybridge/gma.c | 2 +- src/northbridge/intel/sch/gma.c | 2 +- src/soc/intel/baytrail/acpi.c | 2 +- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/fsp_baytrail/acpi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- src/southbridge/via/k8t890/traf_ctrl.c | 2 +- 51 files changed, 60 insertions(+), 53 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index ca52fb4..dd01e0c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -325,7 +325,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { - dev->ops->acpi_fill_ssdt_generator(); + dev->ops->acpi_fill_ssdt_generator(dev); } current = (unsigned long) acpigen_get_current(); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 10db820..be97db5 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -29,6 +29,7 @@ #include <stdint.h> #include <rules.h> +#include <device/device.h> #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ @@ -539,7 +540,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void); +void generate_cpu_entries(device_t device); #endif void acpi_create_mcfg(acpi_mcfg_t *mcfg); diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index 95c90fb..272f486 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index ba778b6..abc35ad 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -263,7 +263,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index b8aad14..c072075 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -307,7 +307,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1e4bb03..da8ba4e 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -299,7 +299,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 47c958a..94cc6de 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 6c7178e..1c3cb9d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -117,7 +117,7 @@ static void gen_pstate_entries(const sst_table_t *const pstates, /** * @brief Generate ACPI entries for Speedstep for each cpu */ -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); diff --git a/src/include/device/device.h b/src/include/device/device.h index beac42a..b806859 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -57,7 +57,7 @@ struct device_operations { #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); - void (*acpi_fill_ssdt_generator)(void); + void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); #endif const struct pci_operations *ops_pci; diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 3ec615f..4fb2baf 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -32,7 +32,7 @@ #include <ec/lenovo/h8/h8.h> #include "drivers/lenovo/lenovo.h" -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index a4da528..62e4fc9 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -87,7 +87,7 @@ static void mainboard_init(device_t dev) printk(BIOS_SPEW, "SPI configured\n"); } -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index fbab0f1..b137aaa 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -99,7 +99,7 @@ static void mainboard_init(device_t dev) } } -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..e62b95e 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -8,7 +8,7 @@ extern u16 pm_base; -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 935e137..ee291a5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -811,7 +811,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 32b74f6..2cf4736 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -793,7 +793,7 @@ static void cpu_bus_init(device_t dev) /* North Bridge Structures */ -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 94e16ac..d42926f 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -506,7 +506,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 0a1e7d3..6c2e953 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 37b6a8e..aef0d83 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 9bbc279..192c3df 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index dee2087..734ebb6 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -196,7 +196,7 @@ void update_ssdtx(void *ssdtx, int i) } -void northbridge_acpi_write_vars(void) +void northbridge_acpi_write_vars(device_t device) { /* * If more than one physical CPU is installed, northbridge_acpi_write_vars() diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 0bbdbd3..9213ed1 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1076,6 +1076,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); -void northbridge_acpi_write_vars(void); +void northbridge_acpi_write_vars(device_t device); #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index d407d7e..1bb1d83 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -277,7 +277,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { acpigen_pop_len(); } -void k8acpi_write_vars(void) +void k8acpi_write_vars(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index a9c2ded..4d822e4 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -21,7 +21,7 @@ #define AMDK8_ACPI_H #include <arch/acpigen.h> -void k8acpi_write_vars(void); +void k8acpi_write_vars(device_t device); unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 60a1d49..d21becf 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -471,7 +471,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8e340ce..2e46b16 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -465,7 +465,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 6b6a703..c726155 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -65,7 +65,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -void northbridge_acpi_fill_ssdt_generator(void) +void northbridge_acpi_fill_ssdt_generator(device_t device) { u32 bmbound; char pscope[] = "\\_SB.PCI0"; @@ -74,5 +74,5 @@ void northbridge_acpi_fill_ssdt_generator(void) acpigen_write_scope(pscope); acpigen_write_name_dword("BMBD", bmbound); acpigen_pop_len(); - generate_cpu_entries(); + generate_cpu_entries(device); } diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index d7f4ebd..dc4676b 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -27,6 +27,9 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ +#include <rules.h> +#include <device/device.h> + /* Device 0:0.0 PCI configuration space (Host Bridge) */ /* SideBand B-UNIT */ @@ -72,7 +75,10 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); -void northbridge_acpi_fill_ssdt_generator(void); + +#if ENV_RAMSTAGE +void northbridge_acpi_fill_ssdt_generator(device_t device); +#endif #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index 26f1ae6..132a1b8 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -74,7 +74,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 7cc59c8..f29b9b1 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -502,7 +502,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f120670..21a285c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -498,7 +498,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 28f611f..a2e5163 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -499,7 +499,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index d4217de..609701d 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -1082,7 +1082,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index d7ad8fe..979d65a 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -624,7 +624,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/sch/gma.c b/src/northbridge/intel/sch/gma.c index 5540eb1..5786f1e 100644 --- a/src/northbridge/intel/sch/gma.c +++ b/src/northbridge/intel/sch/gma.c @@ -57,7 +57,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(void) +static void gma_ssdt(device_t device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index dd8833d..e3444b6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -447,7 +447,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 67220c5..34a576d 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -537,7 +537,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 2825773..9b0d148 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -513,7 +513,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 47b9ae7..df3eff4 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -128,7 +128,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { #if CONFIG_SET_FIDVID amd_generate_powernow(pm_base + 0x10, 6, 1); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 2fb9e22..78fe1fb 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -223,7 +223,7 @@ static void sb600_lpc_enable_resources(device_t dev) extern u16 pm_base; -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(pm_base + 8, 6, 1); } diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 94d8dcb..a39ec18 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -267,7 +267,7 @@ static void sb700_lpc_enable_resources(device_t dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0c24a0a..6bf43de 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -797,7 +797,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index c919205..fa3029c 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -45,7 +45,7 @@ static int determine_total_number_of_cores(void) return count; } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; int numcpus = determine_total_number_of_cores(); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 024604b..61006e6 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -129,10 +129,10 @@ static void sb_read_resources(struct device *dev) } #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - generate_cpu_entries(); + generate_cpu_entries(device); } #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 7c11310..ac1d49f 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -562,7 +562,7 @@ static void southbridge_inject_dsdt(device_t dev) } } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 58a00d5..6565293 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -784,7 +784,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 406b4f2..d0f687f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -313,7 +313,7 @@ static void ck804_lpc_enable_resources(device_t dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d3399f3..8d1a83a 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -283,7 +283,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index b4620da..75dc353 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -127,7 +127,7 @@ static void traf_ctrl_enable_k8t890(struct device *dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t dev) { amd_generate_powernow(0, 0, 0); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); }

1 0

Patch set updated for coreboot: 3d45ab9 mainboard/lenovo/t400: Increase backlight frequency to reduce flicker
by Timothy Pearson 05 Jun '15

05 Jun '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9331 -gerrit commit 3d45ab9b2a6007640473dc191b974aa5500a12d7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Apr 6 22:02:18 2015 -0500 mainboard/lenovo/t400: Increase backlight frequency to reduce flicker TEST: Booted Lenovo T400 with LED backlight and verified the absence of any visible flicker along with proper operation of the brightness control. Change-Id: Ifb485f4aad385aac794978527fd7d246f444ea08 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index c3fffe8..81944c0 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -8,6 +8,8 @@ chip northbridge/intel/gm45 register "gfx.link_frequency_270_mhz" = "1" register "gfx.lvds_num_lanes" = "4" + register "gfx.backlight" = "0x620062" + device cpu_cluster 0 on chip cpu/intel/socket_BGA956 device lapic 0 on end

1 0

Patch set updated for coreboot: 95bb521 mainboard/lenovo/t400: Add initial hybrid graphics support
by Timothy Pearson 05 Jun '15

05 Jun '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9319 -gerrit commit 95bb521bc782f5c5247161995dee7afa7c12a963 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 18:10:09 2015 -0500 mainboard/lenovo/t400: Add initial hybrid graphics support TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux. Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 8 +- src/mainboard/lenovo/t400/romstage.c | 143 +++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 67b8920..06eec57 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -14,3 +14,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 2dc91bf..44f5d04 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -85,7 +85,10 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size -#944 2 r 0 unused +# coreboot config options: graphics +944 2 e 12 hybrid_graphics_mode + +#946 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -137,6 +140,9 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index a739d18..c62df60 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -37,6 +38,118 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 +#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 + +#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 + +#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 +#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 + +static void hybrid_graphics_configure_switchable_graphics(bool enable) +{ + uint32_t tmp; + + if (enable) { + /* Disable integrated graphics legacy VGA cycles */ + tmp = pci_read_config16(MCH_DEV, D0F0_GGC); + pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Enable secondary VGA controller */ + tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); + pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); + } + else { + /* Enable integrated graphics legacy VGA cycles */ + tmp = pci_read_config16(MCH_DEV, D0F0_GGC); + pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); + + /* Disable secondary VGA controller */ + tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); + pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); + } +} + +static void hybrid_graphics_set_up_gpio(void) +{ + uint32_t tmp; + + /* Enable hybrid graphics GPIO lines */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + + /* Set hybrid graphics control GPIO lines to output */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); + + /* Set hybrid graphics detect GPIO lines to input */ + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); +} + +static bool hybrid_graphics_installed(void) +{ + if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) + return false; + else + return true; +} + +static void hybrid_graphics_switch_to_integrated_graphics(void) +{ + uint32_t tmp; + + /* Disable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(false); + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_discrete_graphics(void) +{ + uint32_t tmp; + + /* Disable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(false); + + /* Configure muxes */ + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_dual_graphics(void) +{ + /* Enable switchable graphics */ + hybrid_graphics_configure_switchable_graphics(true); +} + static void default_southbridge_gpio_setup(void) { outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); @@ -98,6 +211,31 @@ void main(unsigned long bist) default_southbridge_gpio_setup(); + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + + /* Set up hybrid graphics */ + hybrid_graphics_set_up_gpio(); + if (hybrid_graphics_installed()) { + /* Select appropriate hybrid graphics device */ + printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); + if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) + hybrid_graphics_switch_to_integrated_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) + hybrid_graphics_switch_to_discrete_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_switch_to_integrated_graphics(); + /* Switchable graphics are fully enabled after raminit */ + /* FIXME + * Enabling switchable graphics prevents bootup! + * Debug and fix appropriately... + */ + } + else { + printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); + hybrid_graphics_switch_to_integrated_graphics(); + } + /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); @@ -177,6 +315,11 @@ void main(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); + + if (hybrid_graphics_installed()) + if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_switch_to_dual_graphics(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc.

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Patch set updated for coreboot: bf35981 mainboard/lenovo/x200: Add power_on_after_fail NVRAM option
by Timothy Pearson 05 Jun '15

05 Jun '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9332 -gerrit commit bf359813b9cb5a25ec271d9538446e338e02645d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Apr 6 22:12:47 2015 -0500 mainboard/lenovo/x200: Add power_on_after_fail NVRAM option Change-Id: I8e78cbae132566b6ca27e0a68af2656364c82b8f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/lenovo/x200/cmos.default | 1 + src/mainboard/lenovo/x200/cmos.layout | 29 +++++++++++++++-------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default index 1da4c7c..67b8920 100644 --- a/src/mainboard/lenovo/x200/cmos.default +++ b/src/mainboard/lenovo/x200/cmos.default @@ -2,6 +2,7 @@ boot_option=Fallback last_boot=Fallback baud_rate=115200 debug_level=Spew +power_on_after_fail=Disable volume=0x3 first_battery=Primary bluetooth=Enable diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 9565915..2dc91bf 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -63,28 +63,29 @@ entries # coreboot config options: southbridge 408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail # coreboot config options: EC -409 1 e 9 first_battery -410 1 e 1 bluetooth -411 1 e 1 wwan -412 1 e 1 wlan -413 1 e 1 trackpoint -414 1 e 1 fn_ctrl_swap -415 1 e 1 sticky_fn +411 1 e 9 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 wlan +415 1 e 1 trackpoint +416 1 e 1 fn_ctrl_swap +417 1 e 1 sticky_fn # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default +418 512 s 0 boot_devices +930 8 h 0 boot_default -936 1 e 1 power_management_beeps -937 1 e 1 low_battery_beep -938 1 e 1 uwb +938 1 e 1 power_management_beeps +939 1 e 1 low_battery_beep +940 1 e 1 uwb # coreboot config options: northbridge -939 3 e 11 gfx_uma_size +941 3 e 11 gfx_uma_size -#942 2 r 0 unused +#944 2 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum

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coreboot-gerrit June 2015