coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch merged into coreboot/master: a9f4327 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit a9f4327d0f40f53fba5ca690f52b98e12236e236 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:24:59 2015 +0200 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0 Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8352 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8352 for details. -gerrit

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Patch merged into coreboot/master: 6326255 AMD K8 fam10: Eliminate local variables busn and max_bus
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 6326255caa2488d90762470bd0c83b8015c198a9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:22:55 2015 +0200 AMD K8 fam10: Eliminate local variables busn and max_bus Change-Id: I297de09dcf93511acece4441593ef958a390fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8362 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8362 for details. -gerrit

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Patch merged into coreboot/master: 20968c9 AMD K8 fam10: Add ht_route_link()
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 20968c9220b6de6a403c807edb19babc8c3a2eac Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 12:05:33 2015 +0200 AMD K8 fam10: Add ht_route_link() Change-Id: I41aeb80121f120641b65759c8502150ce89caa30 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8556 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8556 for details. -gerrit

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Patch merged into coreboot/master: 59d6092 AMD fam10: Fix add_more_links
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 59d609217b0d8abccc7038d7f7a13020fd1ee246 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 23:56:07 2015 +0200 AMD fam10: Fix add_more_links One PCI function may contain upto 4 links, further links must be added to PCI function 4 on the same device. There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: If7ebdd1ad52653d3757b5930bd0a83e2cf2fcac6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8555 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8555 for details. -gerrit

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Patch set updated for coreboot: 7acda43 crossgcc: Add clang support
by Stefan Reinauer 05 Jun '15

05 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10415 -gerrit commit 7acda43ebe6e4f26a27c754623691cab9c2fefe4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 3 17:13:23 2015 -0700 crossgcc: Add clang support Add a new option -C|--clang to buildgcc to build a clang based toolchain as opposed to a gcc based toolchain. This toolchain comes with the required patches needed to successfully build coreboot, and also with clang's famous scan-build script. Change-Id: I1aea7cd6002edc4f3bb2b46dc1f69a212ad18f77 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 229 ++++++++++++++------- util/crossgcc/patches/cfe-3.6.1.src_frontend.patch | 75 +++++++ util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum | 1 + .../sum/clang-tools-extra-3.6.1.src.tar.xz.cksum | 1 + .../sum/compiler-rt-3.6.1.src.tar.xz.cksum | 1 + util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum | 1 + 6 files changed, 233 insertions(+), 75 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a1b596e..d42fc2c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -22,15 +22,15 @@ cd `dirname $0` -CROSSGCC_DATE="June 3th, 2015" -CROSSGCC_VERSION="1.28" +CROSSGCC_DATE="June 4th, 2015" +CROSSGCC_VERSION="1.29" # default settings TARGETDIR=`pwd`/xgcc TARGETARCH=i386-elf DESTDIR= -# version numbers +# GCC toolchain version numbers GMP_VERSION=6.0.0 MPFR_VERSION=3.1.2 MPC_VERSION=1.0.3 @@ -42,8 +42,10 @@ GDB_VERSION=7.9 IASL_VERSION=20150204 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 +# CLANG version number +CLANG_VERSION=3.6.1 -# archive locations +# GCC toolchain archive locations GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}a.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" @@ -54,7 +56,13 @@ GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz" IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix-${IASL_VERSION}.tar.gz" PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}…" EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.t…" +# CLANG toolchain archive locations +LLVM_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" +CFE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" +CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.…" +CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" +# GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" MPC_DIR="mpc-${MPC_VERSION}" @@ -65,10 +73,16 @@ GDB_DIR="gdb-${GDB_VERSION}" IASL_DIR="acpica-unix-${IASL_VERSION}" PYTHON_DIR="Python-${PYTHON_VERSION}" EXPAT_DIR="expat-${EXPAT_VERSION}" +# CLANG toolchain directories +LLVM_DIR="llvm-${CLANG_VERSION}.src" +CFE_DIR="cfe-${CLANG_VERSION}.src" +CRT_DIR="compiler-rt-${CLANG_VERSION}.src" +CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" unset MAKELEVEL MAKEFLAGS SAVETEMPS=0 +BUILDCLANG=0 SKIPGDB=1 SKIPPYTHON=1 @@ -153,15 +167,64 @@ searchtool() TAR=`searchtool tar` || exit $? PATCH=`searchtool patch` || exit $? MAKE=`searchtool make` || exit $? +CMAKE=`searchtool cmake "cmake"` || exit $? searchtool m4 > /dev/null searchtool bison > /dev/null searchtool flex flex > /dev/null searchtool g++ "Free Software Foundation" nofail > /dev/null || \ -searchtool clang "clang version" > /dev/null searchtool wget > /dev/null searchtool bzip2 "bzip2," > /dev/null +download() { + ARCHIVE=$1 + FILE=`basename $ARCHIVE` + printf " * $FILE " + + test -f tarballs/$FILE && \ + (test -z "$CHECKSUM" || \ + test "`cat sum/$FILE.cksum 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" = "`$CHECKSUM tarballs/$FILE 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" ) && \ + printf "(cached)" || ( + printf "(downloading)" + rm -f tarballs/$FILE + cd tarballs + wget --no-check-certificate -q $ARCHIVE + cd .. + test ! -f sum/$FILE.cksum && test -f tarballs/$FILE && \ + (test -z "$CHECKSUM" || $CHECKSUM tarballs/$FILE > sum/$FILE.cksum ) && \ + printf "(checksum created. ${RED}Note. Please upload sum/$FILE.cksum if the corresponding archive is upgraded.${NC})" + ) + test -f tarballs/$FILE || \ + printf "\n${RED}Failed to download $FILE.${NC}\n" + test -f tarballs/$FILE || exit 1 + printf "\n" +} + +unpack_and_patch() { + PACKAGE=$1 + archive=$PACKAGE"_ARCHIVE" + archive="`eval echo '$'$archive`" + dir=$PACKAGE"_DIR" + dir="`eval echo '$'${dir}`" + test -d ${dir} && test -f ${dir}/.unpack_success || ( + printf " * `basename $archive`\n" + FLAGS=zxf + suffix=`echo $archive | sed 's,.*\.,,'` + test "$suffix" = "gz" && FLAGS=zxf + test "$suffix" = "bz2" && FLAGS=jxf + test "$suffix" = "xz" && FLAGS="--xz -xf" + test "$suffix" = "lzma" && FLAGS="--lzma -xf" + $TAR $FLAGS tarballs/`basename $archive` + for patch in patches/${dir}_*.patch; do + test -r $patch || continue + printf " o `basename $patch`\n" + $PATCH -s -N -p0 < `echo $patch` || \ + printf "\n${RED}Failed $patch.${NC}\n" + done + touch ${dir}/.unpack_success + ) +} + wait_for_build() { # $1: directory in which log file and failure marker are stored cat > "$1/crossgcc-build.log" @@ -178,14 +241,30 @@ CHECKSUM=$SHA1SUM cleanup() { printf "Cleaning up temporary files... " - rm -rf ${BUILDDIRPREFIX}-* combined gcc-* gmp-* mpfr-* mpc-* libelf-* binutils-* - rm -rf gdb-* acpica-* python-* expat-* - printf "${green}ok${NC}\n" + if [ "$BUILDCLANG" -eq 0 ]; then + # GCC toolchain + rm -rf ${GMP_DIR} ${BUILDDIRPREFIX}-gmp + rm -rf ${MPFR_DIR} ${BUILDDIRPREFIX}-mpfr + rm -rf ${MPC_DIR} ${BUILDDIRPREFIX}-mpc + rm -rf ${LIBELF_DIR} ${BUILDDIRPREFIX}-libelf + rm -rf ${BINUTILS_DIR} ${BUILDDIRPREFIX}-binutils + rm -rf ${GCC_DIR} ${BUILDDIRPREFIX}-gcc + + # Other tools + rm -rf ${GDB_DIR} ${BUILDDIRPREFIX}-gdb + rm -rf ${EXPAT_DIR} ${BUILDDIRPREFIX}-expat + rm -rf ${PYTHON_DIR} ${BUILDDIRPREFIX}-python + rm -rf ${IASL_DIR} + else + # CLANG + rm -rf ${LLVM_DIR} ${CFE_DIR} ${CRT_DIR} ${CTE_DIR} ${BUILDDIR} + printf "${green}ok${NC}\n" + fi } myhelp() { - printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-G] [-S]\n" + printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n" printf " $0 [-V|--version]\n" printf " $0 [-h|--help]\n\n" @@ -196,14 +275,16 @@ myhelp() printf " [-t|--savetemps] don't remove temporary files after build\n" printf " [-y|--ccache] Use ccache when building cross compiler\n" printf " [-j|--jobs <num>] run <num> jobs in parallel in make\n" + printf " [-C|--clang] build CLANG toolchain" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" - printf " (defaults to $TARGETARCH)\n" + printf " (defaults to $TARGETARCH)\*\n" printf " [-d|--directory <target dir>] target directory to install cross compiler to\n" printf " (defaults to $TARGETDIR)\n\n" printf " [-D|--destdir <dest dir>] destination directory to install cross compiler to\n" printf " (for RPM builds, default unset)\n" - printf " [-G|--gdb] build GNU debugger\n" - printf " [-S|--scripting] build scripting support for GDB\n\n" + printf " [-G|--gdb] build GNU debugger\*\n" + printf " [-S|--scripting] build scripting support for GDB\*\n\n" + printf " \* option only available when building GCC toolchain (not with CLANG)\n\n" } myversion() @@ -236,11 +317,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="`getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,'`" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache Vhcd:p:j:D:tGy -- "$@"` + args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache,clang Vhcd:p:j:D:tGyC -- "$@"` eval set "$args" else # Detected non-GNU getopt - args=`getopt Vhcd:p:j:D:tGy $*` + args=`getopt Vhcd:p:j:D:tGyC $*` set -- $args fi @@ -259,6 +340,7 @@ while true ; do -p|--platform) shift; TARGETARCH="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;; -j|--jobs) shift; JOBS="-j $1"; shift;; + -C|--clang) shift; BUILDCLANG=1;; -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; @@ -268,6 +350,8 @@ while true ; do esac done +if [ "$BUILDCLANG" -eq 0 ]; then + case "$TARGETARCH" in x86_64-elf) ;; x86_64*) TARGETARCH=x86_64-elf;; @@ -283,11 +367,16 @@ esac echo "Target arch is now $TARGETARCH" BUILDDIRPREFIX=build-${TARGETARCH} +else +BUILDDIR=$PWD/build-clang +fi if [ "$clean" = "1" ]; then cleanup fi +if [ "$BUILDCLANG" -eq 0 ]; then + GDB_PACKAGE="GDB" PYTHON_PACKAGE="PYTHON" EXPAT_PACKAGE="EXPAT" @@ -312,69 +401,40 @@ fi USE_GOLD="" GCC_OPTIONS="--enable-lto" +fi # $BUILDCLANG -eq 0 + printf "Downloading tar balls ... \n" mkdir -p tarballs + +if [ "$BUILDCLANG" -eq 0 ]; then for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE \ $IASL_ARCHIVE $PYTHON_ARCHIVE $EXPAT_ARCHIVE; do - FILE=`basename $ARCHIVE` - printf " * $FILE " - - ##create the sum - #test -f sum/$FILE.cksum || ( - # $CHECKSUM tarballs/$FILE > sum/$FILE.cksum - # continue - #) - - test -f tarballs/$FILE && \ - (test -z "$CHECKSUM" || \ - test "`cat sum/$FILE.cksum 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" = "`$CHECKSUM tarballs/$FILE 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" ) && \ - printf "(cached)" || ( - printf "(downloading)" - rm -f tarballs/$FILE - cd tarballs - wget --no-check-certificate -q $ARCHIVE - cd .. - test ! -f sum/$FILE.cksum && test -f tarballs/$FILE && \ - (test -z "$CHECKSUM" || $CHECKSUM tarballs/$FILE > sum/$FILE.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$FILE.cksum if the corresponding archive is upgraded.${NC})" - ) - test -f tarballs/$FILE || \ - printf "\n${RED}Failed to download $FILE.${NC}\n" - test -f tarballs/$FILE || exit 1 - printf "\n" + download $ARCHIVE done +else +for ARCHIVE in $LLVM_ARCHIVE $CFE_ARCHIVE $CRT_ARCHIVE $CTE_ARCHIVE; do + download $ARCHIVE +done +fi printf "Downloaded tar balls ... " printf "${green}ok${NC}\n" printf "Unpacking and patching ... \n" +if [ "$BUILDCLANG" -eq 0 ]; then for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $PYTHON_PACKAGE \ $EXPAT_PACKAGE $GDB_PACKAGE IASL; do - archive=$PACKAGE"_ARCHIVE" - archive="`eval echo '$'$archive`" - dir=$PACKAGE"_DIR" - dir="`eval echo '$'${dir}`" - test -d ${dir} && test -f ${dir}/.unpack_success || ( - printf " * `basename $archive`\n" - FLAGS=zxf - suffix=`echo $archive | sed 's,.*\.,,'` - test "$suffix" = "gz" && FLAGS=zxf - test "$suffix" = "bz2" && FLAGS=jxf - test "$suffix" = "xz" && FLAGS="--xz -xf" - test "$suffix" = "lzma" && FLAGS="--lzma -xf" - $TAR $FLAGS tarballs/`basename $archive` - for patch in patches/${dir}_*.patch; do - test -r $patch || continue - printf " o `basename $patch`\n" - $PATCH -s -N -p0 < `echo $patch` || \ - printf "\n${RED}Failed $patch.${NC}\n" - done - touch ${dir}/.unpack_success - ) + unpack_and_patch $PACKAGE +done +else +for PACKAGE in LLVM CFE CRT CTE; do + unpack_and_patch $PACKAGE done +fi printf "Unpacked and patched ... " printf "${green}ok${NC}\n" +if [ "$BUILDCLANG" -eq 0 ]; then CC=cc if [ $UNAME = "Darwin" ]; then #GCC_OPTIONS="$GCC_OPTIONS --enable-threads=posix" @@ -397,11 +457,13 @@ if [ $UNAME = "Darwin" ]; then CC=llvm-gcc fi fi +fi # "$BUILDCLANG" -eq 0 if [ "$USECCACHE" = 1 ]; then CC="ccache $CC" fi +if [ "$BUILDCLANG" -eq 0 ]; then mkdir -p ${BUILDDIRPREFIX}-gmp ${BUILDDIRPREFIX}-mpfr ${BUILDDIRPREFIX}-mpc ${BUILDDIRPREFIX}-libelf ${BUILDDIRPREFIX}-binutils \ ${BUILDDIRPREFIX}-gcc ${BUILDDIRPREFIX}-python ${BUILDDIRPREFIX}-expat @@ -656,27 +718,44 @@ printf "Building IASL ${IASL_VERSION} ... " ) 2>&1 | wait_for_build "$IASL_DIR/source/compiler" || exit 1 fi +else + +printf "Building CLANG ${CLANG_VERSION} ... " +mkdir -p ${BUILDDIR} +( + ln -sf $PWD/$CFE_DIR $LLVM_DIR/tools/clang + ln -sf $PWD/$CTE_DIR $LLVM_DIR/tools/clang/tools/extra + ln -sf $PWD/$CRT_DIR $LLVM_DIR/projects/compiler-rt + + cd ${BUILDDIR} + + $CMAKE -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX=$DESTDIR$TARGETDIR \ + -DCMAKE_BUILD_TYPE=Release ../$LLVM_DIR || touch .failed + $MAKE $JOBS || touch .failed + $MAKE install || touch .failed + + cd - + + cp -a $CFE_DIR/tools/scan-build/* $DESTDIR$TARGETDIR/bin + cp -a $CFE_DIR/tools/scan-view/* $DESTDIR$TARGETDIR/bin + + if [ ! -f .failed ]; then touch .success; fi +) 2>&1 | wait_for_build "${BUILDDIR}" || exit 1 + +fi # "$BUILDCLANG" -eq 0 + PROGNAME=`basename "$0"` rm -f "$DESTDIR$TARGETDIR/$PROGNAME".commit.* cp "$PROGNAME" $DESTDIR$TARGETDIR/"$PROGNAME.commit.`git describe`" if [ $SAVETEMPS -eq 0 ]; then - printf "Cleaning up... " - rm -rf ${GMP_DIR} ${BUILDDIRPREFIX}-gmp - rm -rf ${MPFR_DIR} ${BUILDDIRPREFIX}-mpfr - rm -rf ${MPC_DIR} ${BUILDDIRPREFIX}-mpc - rm -rf ${LIBELF_DIR} ${BUILDDIRPREFIX}-libelf - rm -rf ${BINUTILS_DIR} ${BUILDDIRPREFIX}-binutils - rm -rf ${GCC_DIR} ${BUILDDIRPREFIX}-gcc - rm -rf ${GDB_DIR} ${BUILDDIRPREFIX}-gdb - rm -rf ${EXPAT_DIR} ${BUILDDIRPREFIX}-expat - rm -rf ${PYTHON_DIR} ${BUILDDIRPREFIX}-python - rm -rf ${IASL_DIR} - printf "${green}ok${NC}\n" + cleanup else printf "Leaving temporary files around... ${green}ok${NC}\n" fi +if [ "$BUILDCLANG" -eq 0 ]; then printf "\n${green}You can now run your $TARGETARCH cross toolchain from $TARGETDIR.${NC}\n" - - +else +printf "\n${green}You can now run your CLANG toolchain from $TARGETDIR.${NC}\n" +fi diff --git a/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch b/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch new file mode 100644 index 0000000..594e08a --- /dev/null +++ b/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch @@ -0,0 +1,75 @@ +Index: include/clang/Driver/Driver.h +=================================================================== +--- cfe-3.6.1.src/include/clang/Driver/Driver.h (revision 211898) ++++ cfe-3.6.1.src/include/clang/Driver/Driver.h (working copy) +@@ -325,6 +325,14 @@ + // FIXME: This should be in CompilationInfo. + std::string GetFilePath(const char *Name, const ToolChain &TC) const; + ++ /// GetCompilerRTPath - Find Compiler-RT library path ++ /// ++ /// \param TC - The provided tool chain for additional information on ++ /// directories to search. ++ // ++ // FIXME: This should be in CompilationInfo. ++ std::string GetCompilerRTPath(const ToolChain &TC) const; ++ + /// GetProgramPath - Lookup \p Name in the list of program search paths. + /// + /// \param TC - The provided tool chain for additional information on +Index: include/clang/Driver/Options.td +=================================================================== +--- cfe-3.6.1.src/include/clang/Driver/Options.td (revision 211898) ++++ cfe-3.6.1.src/include/clang/Driver/Options.td (working copy) +@@ -1269,6 +1269,8 @@ + HelpText<"Enable Objective-C Ivar layout bitmap print trace">; + def print_libgcc_file_name : Flag<["-", "--"], "print-libgcc-file-name">, + HelpText<"Print the library path for \"libgcc.a\"">; ++def print_librt_file_name : Flag<["-", "--"], "print-librt-file-name">, ++ HelpText<"Print the library path for \"libclang_rt.builtins-ARCH.a\"">; + def print_multi_directory : Flag<["-", "--"], "print-multi-directory">; + def print_multi_lib : Flag<["-", "--"], "print-multi-lib">; + def print_multi_os_directory : Flag<["-", "--"], "print-multi-os-directory">; +Index: lib/Driver/Driver.cpp +=================================================================== +--- cfe-3.6.1.src/lib/Driver/Driver.cpp (revision 211898) ++++ cfe-3.6.1.src/lib/Driver/Driver.cpp (working copy) +@@ -756,6 +756,11 @@ + return false; + } + ++ if (C.getArgs().hasArg(options::OPT_print_librt_file_name)) { ++ llvm::outs() << GetCompilerRTPath(TC) << "\n"; ++ return false; ++ } ++ + if (C.getArgs().hasArg(options::OPT_print_multi_lib)) { + const MultilibSet &Multilibs = TC.getMultilibs(); + +@@ -1820,6 +1825,26 @@ + return Name; + } + ++std::string Driver::GetCompilerRTPath(const ToolChain &TC) const { ++ // The runtimes are located in the OS-specific resource directory. ++ SmallString<128> Res(TC.getDriver().ResourceDir); ++ const llvm::Triple &Triple = TC.getTriple(); ++ ++ // TC.getOS() yield "freebsd10.0" whereas "freebsd" is expected. ++ StringRef OSLibName = (Triple.getOS() == llvm::Triple::FreeBSD) ? ++ "freebsd" : TC.getOS(); ++ llvm::sys::path::append(Res, "lib", OSLibName); ++ ++ StringRef archName = TC.getArchName(); ++ // Until ARM libraries are build separately, we have them all in one library ++ if (TC.getArch() == llvm::Triple::arm || ++ TC.getArch() == llvm::Triple::armeb) ++ archName = "arm"; ++ ++ llvm::sys::path::append(Res, Twine("libclang_rt.builtins-") + archName + ".a"); ++ return Res.str(); ++} ++ + std::string Driver::GetProgramPath(const char *Name, + const ToolChain &TC) const { + // FIXME: Needs a better variable than DefaultTargetTriple diff --git a/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..661bf9c --- /dev/null +++ b/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +b7221d8fdd27e3ed519d0281646e82e17b51122c tarballs/cfe-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..17d55cb --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +d93136f56999d8ae1ffebb9cd0cd7f3c27ba77c4 tarballs/clang-tools-extra-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..51e426b --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +85dccdc6ccd9675e871dfd2786b45fbf53518485 tarballs/compiler-rt-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..5ca7065 --- /dev/null +++ b/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +01ecab99adc9030ee34e9a2e19e65dfe64e1affe tarballs/llvm-3.6.1.src.tar.xz

1 0

Patch set updated for coreboot: 944b11c crossgcc: Add clang support
by Stefan Reinauer 05 Jun '15

05 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10415 -gerrit commit 944b11c2e466a408352ed21db1ecdcead458fe75 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 3 17:13:23 2015 -0700 crossgcc: Add clang support Add a new script, buildclang, which builds and installs a clang based toolchain, similarly to our buildgcc script. This toolchain will carry the required patches needed to successfully build coreboot, and also install clang's famous scan-build script. Change-Id: I1aea7cd6002edc4f3bb2b46dc1f69a212ad18f77 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 229 ++++++++++++++------- util/crossgcc/patches/cfe-3.6.1.src_frontend.patch | 75 +++++++ util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum | 1 + .../sum/clang-tools-extra-3.6.1.src.tar.xz.cksum | 1 + .../sum/compiler-rt-3.6.1.src.tar.xz.cksum | 1 + util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum | 1 + 6 files changed, 233 insertions(+), 75 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index a1b596e..d42fc2c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -22,15 +22,15 @@ cd `dirname $0` -CROSSGCC_DATE="June 3th, 2015" -CROSSGCC_VERSION="1.28" +CROSSGCC_DATE="June 4th, 2015" +CROSSGCC_VERSION="1.29" # default settings TARGETDIR=`pwd`/xgcc TARGETARCH=i386-elf DESTDIR= -# version numbers +# GCC toolchain version numbers GMP_VERSION=6.0.0 MPFR_VERSION=3.1.2 MPC_VERSION=1.0.3 @@ -42,8 +42,10 @@ GDB_VERSION=7.9 IASL_VERSION=20150204 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 +# CLANG version number +CLANG_VERSION=3.6.1 -# archive locations +# GCC toolchain archive locations GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}a.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" @@ -54,7 +56,13 @@ GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz" IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix-${IASL_VERSION}.tar.gz" PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}…" EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.t…" +# CLANG toolchain archive locations +LLVM_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" +CFE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" +CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.…" +CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" +# GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" MPC_DIR="mpc-${MPC_VERSION}" @@ -65,10 +73,16 @@ GDB_DIR="gdb-${GDB_VERSION}" IASL_DIR="acpica-unix-${IASL_VERSION}" PYTHON_DIR="Python-${PYTHON_VERSION}" EXPAT_DIR="expat-${EXPAT_VERSION}" +# CLANG toolchain directories +LLVM_DIR="llvm-${CLANG_VERSION}.src" +CFE_DIR="cfe-${CLANG_VERSION}.src" +CRT_DIR="compiler-rt-${CLANG_VERSION}.src" +CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" unset MAKELEVEL MAKEFLAGS SAVETEMPS=0 +BUILDCLANG=0 SKIPGDB=1 SKIPPYTHON=1 @@ -153,15 +167,64 @@ searchtool() TAR=`searchtool tar` || exit $? PATCH=`searchtool patch` || exit $? MAKE=`searchtool make` || exit $? +CMAKE=`searchtool cmake "cmake"` || exit $? searchtool m4 > /dev/null searchtool bison > /dev/null searchtool flex flex > /dev/null searchtool g++ "Free Software Foundation" nofail > /dev/null || \ -searchtool clang "clang version" > /dev/null searchtool wget > /dev/null searchtool bzip2 "bzip2," > /dev/null +download() { + ARCHIVE=$1 + FILE=`basename $ARCHIVE` + printf " * $FILE " + + test -f tarballs/$FILE && \ + (test -z "$CHECKSUM" || \ + test "`cat sum/$FILE.cksum 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" = "`$CHECKSUM tarballs/$FILE 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" ) && \ + printf "(cached)" || ( + printf "(downloading)" + rm -f tarballs/$FILE + cd tarballs + wget --no-check-certificate -q $ARCHIVE + cd .. + test ! -f sum/$FILE.cksum && test -f tarballs/$FILE && \ + (test -z "$CHECKSUM" || $CHECKSUM tarballs/$FILE > sum/$FILE.cksum ) && \ + printf "(checksum created. ${RED}Note. Please upload sum/$FILE.cksum if the corresponding archive is upgraded.${NC})" + ) + test -f tarballs/$FILE || \ + printf "\n${RED}Failed to download $FILE.${NC}\n" + test -f tarballs/$FILE || exit 1 + printf "\n" +} + +unpack_and_patch() { + PACKAGE=$1 + archive=$PACKAGE"_ARCHIVE" + archive="`eval echo '$'$archive`" + dir=$PACKAGE"_DIR" + dir="`eval echo '$'${dir}`" + test -d ${dir} && test -f ${dir}/.unpack_success || ( + printf " * `basename $archive`\n" + FLAGS=zxf + suffix=`echo $archive | sed 's,.*\.,,'` + test "$suffix" = "gz" && FLAGS=zxf + test "$suffix" = "bz2" && FLAGS=jxf + test "$suffix" = "xz" && FLAGS="--xz -xf" + test "$suffix" = "lzma" && FLAGS="--lzma -xf" + $TAR $FLAGS tarballs/`basename $archive` + for patch in patches/${dir}_*.patch; do + test -r $patch || continue + printf " o `basename $patch`\n" + $PATCH -s -N -p0 < `echo $patch` || \ + printf "\n${RED}Failed $patch.${NC}\n" + done + touch ${dir}/.unpack_success + ) +} + wait_for_build() { # $1: directory in which log file and failure marker are stored cat > "$1/crossgcc-build.log" @@ -178,14 +241,30 @@ CHECKSUM=$SHA1SUM cleanup() { printf "Cleaning up temporary files... " - rm -rf ${BUILDDIRPREFIX}-* combined gcc-* gmp-* mpfr-* mpc-* libelf-* binutils-* - rm -rf gdb-* acpica-* python-* expat-* - printf "${green}ok${NC}\n" + if [ "$BUILDCLANG" -eq 0 ]; then + # GCC toolchain + rm -rf ${GMP_DIR} ${BUILDDIRPREFIX}-gmp + rm -rf ${MPFR_DIR} ${BUILDDIRPREFIX}-mpfr + rm -rf ${MPC_DIR} ${BUILDDIRPREFIX}-mpc + rm -rf ${LIBELF_DIR} ${BUILDDIRPREFIX}-libelf + rm -rf ${BINUTILS_DIR} ${BUILDDIRPREFIX}-binutils + rm -rf ${GCC_DIR} ${BUILDDIRPREFIX}-gcc + + # Other tools + rm -rf ${GDB_DIR} ${BUILDDIRPREFIX}-gdb + rm -rf ${EXPAT_DIR} ${BUILDDIRPREFIX}-expat + rm -rf ${PYTHON_DIR} ${BUILDDIRPREFIX}-python + rm -rf ${IASL_DIR} + else + # CLANG + rm -rf ${LLVM_DIR} ${CFE_DIR} ${CRT_DIR} ${CTE_DIR} ${BUILDDIR} + printf "${green}ok${NC}\n" + fi } myhelp() { - printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-G] [-S]\n" + printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n" printf " $0 [-V|--version]\n" printf " $0 [-h|--help]\n\n" @@ -196,14 +275,16 @@ myhelp() printf " [-t|--savetemps] don't remove temporary files after build\n" printf " [-y|--ccache] Use ccache when building cross compiler\n" printf " [-j|--jobs <num>] run <num> jobs in parallel in make\n" + printf " [-C|--clang] build CLANG toolchain" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" - printf " (defaults to $TARGETARCH)\n" + printf " (defaults to $TARGETARCH)\*\n" printf " [-d|--directory <target dir>] target directory to install cross compiler to\n" printf " (defaults to $TARGETDIR)\n\n" printf " [-D|--destdir <dest dir>] destination directory to install cross compiler to\n" printf " (for RPM builds, default unset)\n" - printf " [-G|--gdb] build GNU debugger\n" - printf " [-S|--scripting] build scripting support for GDB\n\n" + printf " [-G|--gdb] build GNU debugger\*\n" + printf " [-S|--scripting] build scripting support for GDB\*\n\n" + printf " \* option only available when building GCC toolchain (not with CLANG)\n\n" } myversion() @@ -236,11 +317,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="`getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,'`" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache Vhcd:p:j:D:tGy -- "$@"` + args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps,skip-gdb,ccache,clang Vhcd:p:j:D:tGyC -- "$@"` eval set "$args" else # Detected non-GNU getopt - args=`getopt Vhcd:p:j:D:tGy $*` + args=`getopt Vhcd:p:j:D:tGyC $*` set -- $args fi @@ -259,6 +340,7 @@ while true ; do -p|--platform) shift; TARGETARCH="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;; -j|--jobs) shift; JOBS="-j $1"; shift;; + -C|--clang) shift; BUILDCLANG=1;; -G|--gdb) shift; SKIPGDB=0;; -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; @@ -268,6 +350,8 @@ while true ; do esac done +if [ "$BUILDCLANG" -eq 0 ]; then + case "$TARGETARCH" in x86_64-elf) ;; x86_64*) TARGETARCH=x86_64-elf;; @@ -283,11 +367,16 @@ esac echo "Target arch is now $TARGETARCH" BUILDDIRPREFIX=build-${TARGETARCH} +else +BUILDDIR=$PWD/build-clang +fi if [ "$clean" = "1" ]; then cleanup fi +if [ "$BUILDCLANG" -eq 0 ]; then + GDB_PACKAGE="GDB" PYTHON_PACKAGE="PYTHON" EXPAT_PACKAGE="EXPAT" @@ -312,69 +401,40 @@ fi USE_GOLD="" GCC_OPTIONS="--enable-lto" +fi # $BUILDCLANG -eq 0 + printf "Downloading tar balls ... \n" mkdir -p tarballs + +if [ "$BUILDCLANG" -eq 0 ]; then for ARCHIVE in $GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE \ $IASL_ARCHIVE $PYTHON_ARCHIVE $EXPAT_ARCHIVE; do - FILE=`basename $ARCHIVE` - printf " * $FILE " - - ##create the sum - #test -f sum/$FILE.cksum || ( - # $CHECKSUM tarballs/$FILE > sum/$FILE.cksum - # continue - #) - - test -f tarballs/$FILE && \ - (test -z "$CHECKSUM" || \ - test "`cat sum/$FILE.cksum 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" = "`$CHECKSUM tarballs/$FILE 2>/dev/null | sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,'`" ) && \ - printf "(cached)" || ( - printf "(downloading)" - rm -f tarballs/$FILE - cd tarballs - wget --no-check-certificate -q $ARCHIVE - cd .. - test ! -f sum/$FILE.cksum && test -f tarballs/$FILE && \ - (test -z "$CHECKSUM" || $CHECKSUM tarballs/$FILE > sum/$FILE.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$FILE.cksum if the corresponding archive is upgraded.${NC})" - ) - test -f tarballs/$FILE || \ - printf "\n${RED}Failed to download $FILE.${NC}\n" - test -f tarballs/$FILE || exit 1 - printf "\n" + download $ARCHIVE done +else +for ARCHIVE in $LLVM_ARCHIVE $CFE_ARCHIVE $CRT_ARCHIVE $CTE_ARCHIVE; do + download $ARCHIVE +done +fi printf "Downloaded tar balls ... " printf "${green}ok${NC}\n" printf "Unpacking and patching ... \n" +if [ "$BUILDCLANG" -eq 0 ]; then for PACKAGE in GMP MPFR MPC LIBELF GCC BINUTILS $PYTHON_PACKAGE \ $EXPAT_PACKAGE $GDB_PACKAGE IASL; do - archive=$PACKAGE"_ARCHIVE" - archive="`eval echo '$'$archive`" - dir=$PACKAGE"_DIR" - dir="`eval echo '$'${dir}`" - test -d ${dir} && test -f ${dir}/.unpack_success || ( - printf " * `basename $archive`\n" - FLAGS=zxf - suffix=`echo $archive | sed 's,.*\.,,'` - test "$suffix" = "gz" && FLAGS=zxf - test "$suffix" = "bz2" && FLAGS=jxf - test "$suffix" = "xz" && FLAGS="--xz -xf" - test "$suffix" = "lzma" && FLAGS="--lzma -xf" - $TAR $FLAGS tarballs/`basename $archive` - for patch in patches/${dir}_*.patch; do - test -r $patch || continue - printf " o `basename $patch`\n" - $PATCH -s -N -p0 < `echo $patch` || \ - printf "\n${RED}Failed $patch.${NC}\n" - done - touch ${dir}/.unpack_success - ) + unpack_and_patch $PACKAGE +done +else +for PACKAGE in LLVM CFE CRT CTE; do + unpack_and_patch $PACKAGE done +fi printf "Unpacked and patched ... " printf "${green}ok${NC}\n" +if [ "$BUILDCLANG" -eq 0 ]; then CC=cc if [ $UNAME = "Darwin" ]; then #GCC_OPTIONS="$GCC_OPTIONS --enable-threads=posix" @@ -397,11 +457,13 @@ if [ $UNAME = "Darwin" ]; then CC=llvm-gcc fi fi +fi # "$BUILDCLANG" -eq 0 if [ "$USECCACHE" = 1 ]; then CC="ccache $CC" fi +if [ "$BUILDCLANG" -eq 0 ]; then mkdir -p ${BUILDDIRPREFIX}-gmp ${BUILDDIRPREFIX}-mpfr ${BUILDDIRPREFIX}-mpc ${BUILDDIRPREFIX}-libelf ${BUILDDIRPREFIX}-binutils \ ${BUILDDIRPREFIX}-gcc ${BUILDDIRPREFIX}-python ${BUILDDIRPREFIX}-expat @@ -656,27 +718,44 @@ printf "Building IASL ${IASL_VERSION} ... " ) 2>&1 | wait_for_build "$IASL_DIR/source/compiler" || exit 1 fi +else + +printf "Building CLANG ${CLANG_VERSION} ... " +mkdir -p ${BUILDDIR} +( + ln -sf $PWD/$CFE_DIR $LLVM_DIR/tools/clang + ln -sf $PWD/$CTE_DIR $LLVM_DIR/tools/clang/tools/extra + ln -sf $PWD/$CRT_DIR $LLVM_DIR/projects/compiler-rt + + cd ${BUILDDIR} + + $CMAKE -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX=$DESTDIR$TARGETDIR \ + -DCMAKE_BUILD_TYPE=Release ../$LLVM_DIR || touch .failed + $MAKE $JOBS || touch .failed + $MAKE install || touch .failed + + cd - + + cp -a $CFE_DIR/tools/scan-build/* $DESTDIR$TARGETDIR/bin + cp -a $CFE_DIR/tools/scan-view/* $DESTDIR$TARGETDIR/bin + + if [ ! -f .failed ]; then touch .success; fi +) 2>&1 | wait_for_build "${BUILDDIR}" || exit 1 + +fi # "$BUILDCLANG" -eq 0 + PROGNAME=`basename "$0"` rm -f "$DESTDIR$TARGETDIR/$PROGNAME".commit.* cp "$PROGNAME" $DESTDIR$TARGETDIR/"$PROGNAME.commit.`git describe`" if [ $SAVETEMPS -eq 0 ]; then - printf "Cleaning up... " - rm -rf ${GMP_DIR} ${BUILDDIRPREFIX}-gmp - rm -rf ${MPFR_DIR} ${BUILDDIRPREFIX}-mpfr - rm -rf ${MPC_DIR} ${BUILDDIRPREFIX}-mpc - rm -rf ${LIBELF_DIR} ${BUILDDIRPREFIX}-libelf - rm -rf ${BINUTILS_DIR} ${BUILDDIRPREFIX}-binutils - rm -rf ${GCC_DIR} ${BUILDDIRPREFIX}-gcc - rm -rf ${GDB_DIR} ${BUILDDIRPREFIX}-gdb - rm -rf ${EXPAT_DIR} ${BUILDDIRPREFIX}-expat - rm -rf ${PYTHON_DIR} ${BUILDDIRPREFIX}-python - rm -rf ${IASL_DIR} - printf "${green}ok${NC}\n" + cleanup else printf "Leaving temporary files around... ${green}ok${NC}\n" fi +if [ "$BUILDCLANG" -eq 0 ]; then printf "\n${green}You can now run your $TARGETARCH cross toolchain from $TARGETDIR.${NC}\n" - - +else +printf "\n${green}You can now run your CLANG toolchain from $TARGETDIR.${NC}\n" +fi diff --git a/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch b/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch new file mode 100644 index 0000000..594e08a --- /dev/null +++ b/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch @@ -0,0 +1,75 @@ +Index: include/clang/Driver/Driver.h +=================================================================== +--- cfe-3.6.1.src/include/clang/Driver/Driver.h (revision 211898) ++++ cfe-3.6.1.src/include/clang/Driver/Driver.h (working copy) +@@ -325,6 +325,14 @@ + // FIXME: This should be in CompilationInfo. + std::string GetFilePath(const char *Name, const ToolChain &TC) const; + ++ /// GetCompilerRTPath - Find Compiler-RT library path ++ /// ++ /// \param TC - The provided tool chain for additional information on ++ /// directories to search. ++ // ++ // FIXME: This should be in CompilationInfo. ++ std::string GetCompilerRTPath(const ToolChain &TC) const; ++ + /// GetProgramPath - Lookup \p Name in the list of program search paths. + /// + /// \param TC - The provided tool chain for additional information on +Index: include/clang/Driver/Options.td +=================================================================== +--- cfe-3.6.1.src/include/clang/Driver/Options.td (revision 211898) ++++ cfe-3.6.1.src/include/clang/Driver/Options.td (working copy) +@@ -1269,6 +1269,8 @@ + HelpText<"Enable Objective-C Ivar layout bitmap print trace">; + def print_libgcc_file_name : Flag<["-", "--"], "print-libgcc-file-name">, + HelpText<"Print the library path for \"libgcc.a\"">; ++def print_librt_file_name : Flag<["-", "--"], "print-librt-file-name">, ++ HelpText<"Print the library path for \"libclang_rt.builtins-ARCH.a\"">; + def print_multi_directory : Flag<["-", "--"], "print-multi-directory">; + def print_multi_lib : Flag<["-", "--"], "print-multi-lib">; + def print_multi_os_directory : Flag<["-", "--"], "print-multi-os-directory">; +Index: lib/Driver/Driver.cpp +=================================================================== +--- cfe-3.6.1.src/lib/Driver/Driver.cpp (revision 211898) ++++ cfe-3.6.1.src/lib/Driver/Driver.cpp (working copy) +@@ -756,6 +756,11 @@ + return false; + } + ++ if (C.getArgs().hasArg(options::OPT_print_librt_file_name)) { ++ llvm::outs() << GetCompilerRTPath(TC) << "\n"; ++ return false; ++ } ++ + if (C.getArgs().hasArg(options::OPT_print_multi_lib)) { + const MultilibSet &Multilibs = TC.getMultilibs(); + +@@ -1820,6 +1825,26 @@ + return Name; + } + ++std::string Driver::GetCompilerRTPath(const ToolChain &TC) const { ++ // The runtimes are located in the OS-specific resource directory. ++ SmallString<128> Res(TC.getDriver().ResourceDir); ++ const llvm::Triple &Triple = TC.getTriple(); ++ ++ // TC.getOS() yield "freebsd10.0" whereas "freebsd" is expected. ++ StringRef OSLibName = (Triple.getOS() == llvm::Triple::FreeBSD) ? ++ "freebsd" : TC.getOS(); ++ llvm::sys::path::append(Res, "lib", OSLibName); ++ ++ StringRef archName = TC.getArchName(); ++ // Until ARM libraries are build separately, we have them all in one library ++ if (TC.getArch() == llvm::Triple::arm || ++ TC.getArch() == llvm::Triple::armeb) ++ archName = "arm"; ++ ++ llvm::sys::path::append(Res, Twine("libclang_rt.builtins-") + archName + ".a"); ++ return Res.str(); ++} ++ + std::string Driver::GetProgramPath(const char *Name, + const ToolChain &TC) const { + // FIXME: Needs a better variable than DefaultTargetTriple diff --git a/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..661bf9c --- /dev/null +++ b/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +b7221d8fdd27e3ed519d0281646e82e17b51122c tarballs/cfe-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..17d55cb --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +d93136f56999d8ae1ffebb9cd0cd7f3c27ba77c4 tarballs/clang-tools-extra-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..51e426b --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +85dccdc6ccd9675e871dfd2786b45fbf53518485 tarballs/compiler-rt-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum new file mode 100644 index 0000000..5ca7065 --- /dev/null +++ b/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum @@ -0,0 +1 @@ +01ecab99adc9030ee34e9a2e19e65dfe64e1affe tarballs/llvm-3.6.1.src.tar.xz

1 0

Patch set updated for coreboot: 6665881 Move same Kconfigs to northbridge/amd/pi/Kconfig
by WANG Siyuan 05 Jun '15

05 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10421 -gerrit commit 6665881725ff918c3d1831bf659246d8ad030a1f Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 2 16:25:58 2015 +0800 Move same Kconfigs to northbridge/amd/pi/Kconfig Bettong, Lamar and Olivehill Plus have many same Kconfigs. Move them to northbridge/amd/pi/Kconfig. Change-Id: I758d5a09f27eee7a7bd60268a2aaed6f16fd0294 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/mainboard/amd/bettong/Kconfig | 32 -------------------------------- src/mainboard/amd/lamar/Kconfig | 32 -------------------------------- src/mainboard/amd/olivehillplus/Kconfig | 20 -------------------- src/northbridge/amd/pi/Kconfig | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 32 insertions(+), 84 deletions(-) diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 17862c3..9f95ef1 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -40,42 +40,10 @@ config MAINBOARD_PART_NUMBER string default "FP4" -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n - -config IRQ_SLOT_COUNT - int - default 11 - -config RAMTOP - hex - default 0x1000000 - -config HEAP_SIZE - hex - default 0xc0000 - config ACPI_SSDTX_NUM int default 0 -config RAMBASE - hex - default 0x200000 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config HUDSON_LEGACY_FREE bool default y diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 4d67a43..408d430 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -44,38 +44,6 @@ config MAINBOARD_SERIAL_NUMBER string default "52198A" -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n - -config IRQ_SLOT_COUNT - int - default 11 - -config RAMTOP - hex - default 0x1000000 - -config HEAP_SIZE - hex - default 0xc0000 - -config RAMBASE - hex - default 0x200000 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config HUDSON_XHCI_FWM_FILE string default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index e99d17d..38e029b 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -39,26 +39,6 @@ config MAINBOARD_PART_NUMBER string default "DB-FT3b" -config HW_MEM_HOLE_SIZEK - hex - default 0x200000 - -config MAX_CPUS - int - default 4 - -config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n - -config IRQ_SLOT_COUNT - int - default 11 - -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config HUDSON_LEGACY_FREE bool default y diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 950126b..5954a68 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -36,4 +36,36 @@ source src/northbridge/amd/pi/00630F01/Kconfig source src/northbridge/amd/pi/00730F01/Kconfig source src/northbridge/amd/pi/00660F01/Kconfig +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + endif # NORTHBRIDGE_AMD_PI

1 0

Patch set updated for coreboot: d931c31 AMD Bettong: Add a new AMD FP4 socket mainboard
by WANG Siyuan 05 Jun '15

05 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10420 -gerrit commit d931c315b210427dae63b22286077346e3960d43 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed May 20 14:47:58 2015 +0800 AMD Bettong: Add a new AMD FP4 socket mainboard Add a new mainboard based on AMD's Family 15h Model 60h processor. TEST: Bettong can boot Ubuntu 14.10, Windows 7 and Windows 8. Change-Id: Id807369ff0f04ba303383c65ddd1bd512f184e6a Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 93 ++++++++++++ src/mainboard/amd/bettong/BiosCallOuts.h | 50 +++++++ src/mainboard/amd/bettong/Kconfig | 87 +++++++++++ src/mainboard/amd/bettong/Kconfig.name | 2 + src/mainboard/amd/bettong/Makefile.inc | 24 +++ src/mainboard/amd/bettong/PlatformGnbPcie.c | 127 ++++++++++++++++ src/mainboard/amd/bettong/acpi/AmdImc.asl | 114 ++++++++++++++ src/mainboard/amd/bettong/acpi/gpe.asl | 78 ++++++++++ src/mainboard/amd/bettong/acpi/mainboard.asl | 34 +++++ src/mainboard/amd/bettong/acpi/routing.asl | 212 +++++++++++++++++++++++++++ src/mainboard/amd/bettong/acpi/sleep.asl | 90 ++++++++++++ src/mainboard/amd/bettong/acpi/usb_oc.asl | 132 +++++++++++++++++ src/mainboard/amd/bettong/acpi_tables.c | 62 ++++++++ src/mainboard/amd/bettong/board_info.txt | 1 + src/mainboard/amd/bettong/cmos.layout | 114 ++++++++++++++ src/mainboard/amd/bettong/devicetree.cb | 77 ++++++++++ src/mainboard/amd/bettong/dsdt.asl | 84 +++++++++++ src/mainboard/amd/bettong/irq_tables.c | 107 ++++++++++++++ src/mainboard/amd/bettong/mainboard.c | 45 ++++++ src/mainboard/amd/bettong/mptable.c | 195 ++++++++++++++++++++++++ src/mainboard/amd/bettong/romstage.c | 102 +++++++++++++ src/mainboard/amd/olivehillplus/romstage.c | 3 - 22 files changed, 1830 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c new file mode 100644 index 0000000..218bb86 --- /dev/null +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include "hudson.h" +#include <stdlib.h> +#include "BiosCallOuts.h" + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such as Azalia, SATA, IMC etc. + */ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + GPIO_CONTROL oem_bettong_gpio[] = { + {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, + {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, + {-1} + }; + + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; + FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio; + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* XHCI configuration */ +#if CONFIG_HUDSON_XHCI_ENABLE + FchParams_env->Usb.Xhci0Enable = TRUE; +#else + FchParams_env->Usb.Xhci0Enable = FALSE; +#endif + FchParams_env->Usb.Xhci1Enable = FALSE; + + /* sata configuration */ + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/bettong/BiosCallOuts.h b/src/mainboard/amd/bettong/BiosCallOuts.h new file mode 100644 index 0000000..42ad188 --- /dev/null +++ b/src/mainboard/amd/bettong/BiosCallOuts.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig new file mode 100644 index 0000000..17862c3 --- /dev/null +++ b/src/mainboard/amd/bettong/Kconfig @@ -0,0 +1,87 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_BETTONG + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_PI_00660F01 + select NORTHBRIDGE_AMD_PI_00660F01 + select SOUTHBRIDGE_AMD_PI_KERN + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE +# select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + string + default amd/bettong + +config MAINBOARD_PART_NUMBER + string + default "FP4" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + +endif # BOARD_AMD_BETTONG diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name new file mode 100644 index 0000000..09201b5 --- /dev/null +++ b/src/mainboard/amd/bettong/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_BETTONG + bool "Bettong" diff --git a/src/mainboard/amd/bettong/Makefile.inc b/src/mainboard/amd/bettong/Makefile.inc new file mode 100644 index 0000000..89dc0ee --- /dev/null +++ b/src/mainboard/amd/bettong/Makefile.inc @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/bettong/PlatformGnbPcie.c b/src/mainboard/amd/bettong/PlatformGnbPcie.c new file mode 100644 index 0000000..e73288d --- /dev/null +++ b/src/mainboard/amd/bettong/PlatformGnbPcie.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 3, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, // Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x06, 0) + }, +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, //DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} diff --git a/src/mainboard/amd/bettong/acpi/AmdImc.asl b/src/mainboard/amd/bettong/acpi/AmdImc.asl new file mode 100644 index 0000000..2f39d0d --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/AmdImc.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl new file mode 100644 index 0000000..8d4f8a2 --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/bettong/acpi/mainboard.asl b/src/mainboard/amd/bettong/acpi/mainboard.asl new file mode 100644 index 0000000..baa27eb --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/mainboard.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl new file mode 100644 index 0000000..d348727 --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/routing.asl @@ -0,0 +1,212 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 43 }, + Package(){0x0001FFFF, 1, 0, 40 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 44 }, + Package(){0x0002FFFF, 1, 0, 45 }, + Package(){0x0002FFFF, 2, 0, 46 }, + Package(){0x0002FFFF, 3, 0, 47 }, + + Package(){0x0003FFFF, 0, 0, 49 }, + Package(){0x0003FFFF, 1, 0, 50 }, + Package(){0x0003FFFF, 2, 0, 51 }, + Package(){0x0003FFFF, 3, 0, 52 }, + + Package(){0x0008FFFF, 0, 0, 35 }, + Package(){0x0008FFFF, 1, 0, 32 }, + Package(){0x0008FFFF, 2, 0, 33 }, + Package(){0x0008FFFF, 3, 0, 34 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, 0, 39 }, + Package(){0x0009FFFF, 1, 0, 36 }, + Package(){0x0009FFFF, 2, 0, 37 }, + Package(){0x0009FFFF, 3, 0, 38 }, +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + diff --git a/src/mainboard/amd/bettong/acpi/sleep.asl b/src/mainboard/amd/bettong/acpi/sleep.asl new file mode 100644 index 0000000..fa10cab --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/sleep.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/bettong/acpi/usb_oc.asl b/src/mainboard/amd/bettong/acpi/usb_oc.asl new file mode 100644 index 0000000..30dd041 --- /dev/null +++ b/src/mainboard/amd/bettong/acpi/usb_oc.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ + +#if 0 /* TODO: Update for Olivehill */ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} +#endif diff --git a/src/mainboard/amd/bettong/acpi_tables.c b/src/mainboard/amd/bettong/acpi_tables.c new file mode 100644 index 0000000..82489de --- /dev/null +++ b/src/mainboard/amd/bettong/acpi_tables.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +#define IO_APIC2_ADDR 0xFEC20000 + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Kern IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + IO_APIC2_ADDR, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/amd/bettong/board_info.txt b/src/mainboard/amd/bettong/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/bettong/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/bettong/cmos.layout b/src/mainboard/amd/bettong/cmos.layout new file mode 100644 index 0000000..4244417 --- /dev/null +++ b/src/mainboard/amd/bettong/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb new file mode 100644 index 0000000..2d55a66 --- /dev/null +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/pi/00660F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00660F01 + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00660F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00660F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + end #chip northbridge/amd/pi/00660F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 11.0 on end # SATA + device pci 12.0 on end # USB +# device pci 12.2 on end # USB + device pci 13.0 on end # USB +# device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + #device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/pi/00660F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00660F01/root_complex diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl new file mode 100644 index 0000000..07f86b9 --- /dev/null +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/pi/00660F01/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/pi/00660F01/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/bettong/irq_tables.c b/src/mainboard/amd/bettong/irq_tables.c new file mode 100644 index 0000000..4ab068b --- /dev/null +++ b/src/mainboard/amd/bettong/irq_tables.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c new file mode 100644 index 0000000..087881b --- /dev/null +++ b/src/mainboard/amd/bettong/mainboard.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include <cpu/amd/pi/s3_resume.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +/************************************************* + * enable the dedicated function in bettong board. + *************************************************/ +static void bettong_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = bettong_enable, +}; diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c new file mode 100644 index 0000000..6359b6b --- /dev/null +++ b/src/mainboard/amd/bettong/mptable.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include "southbridge/amd/pi/hudson/hudson.h" /* pm_ioread() */ + +u8 picr_data[0x54] = { + 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03,0x04,0x05,0x07 +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c new file mode 100644 index 0000000..1fe2e85 --- /dev/null +++ b/src/mainboard/amd/bettong/romstage.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/s3_resume.h> + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; +#if CONFIG_HAVE_ACPI_RESUME + void *resume_backup_memory; +#endif + + amd_initmmio(); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + post_code(0x38); + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } + + /* enable USB */ + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +} diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 0d0fcc0..999510b 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -114,9 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - post_code(0x50); copy_and_run();

1 0

Patch set updated for coreboot: c79607f AMD Merlin Falcon: Add northbridge files for new AMD processor
by WANG Siyuan 05 Jun '15

05 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10419 -gerrit commit c79607f4e71397c524b9cc147f27a2ad762342af Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed May 20 14:44:32 2015 +0800 AMD Merlin Falcon: Add northbridge files for new AMD processor Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/include/device/pci_ids.h | 1 + src/northbridge/amd/agesa/agesawrapper.h | 2 + src/northbridge/amd/pi/00660F01/Kconfig | 53 + src/northbridge/amd/pi/00660F01/Makefile.inc | 22 + .../amd/pi/00660F01/acpi/northbridge.asl | 100 ++ src/northbridge/amd/pi/00660F01/chip.h | 28 + src/northbridge/amd/pi/00660F01/dimmSpd.c | 54 + src/northbridge/amd/pi/00660F01/northbridge.c | 1232 ++++++++++++++++++++ src/northbridge/amd/pi/00660F01/northbridge.h | 26 + src/northbridge/amd/pi/BiosCallOuts.h | 2 +- src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/amd/pi/Makefile.inc | 1 + src/northbridge/amd/pi/agesawrapper.c | 2 + 13 files changed, 1523 insertions(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 13e66db..5ba183b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -289,6 +289,7 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 #define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566 +#define PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT 0x1570 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index eb1a59c..a548374 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -74,6 +74,8 @@ extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); +#ifndef CONFIG_CPU_AMD_PI_00660F01 AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); +#endif #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig new file mode 100644 index 0000000..53982e7 --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_PI_00660F01 + bool + select MMCONF_SUPPORT + select PER_DEVICE_ACPI_TABLES + +if NORTHBRIDGE_AMD_PI_00660F01 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 + +config MMCONF_BUS_NUMBER + int + default 64 + +config VGA_BIOS_ID + string + default "1002,9870" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" + +endif diff --git a/src/northbridge/amd/pi/00660F01/Makefile.inc b/src/northbridge/amd/pi/00660F01/Makefile.inc new file mode 100644 index 0000000..82024b8 --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += dimmSpd.c + +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl new file mode 100644 index 0000000..37aba9a --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PMOD) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h new file mode 100644 index 0000000..5e6ddd1 --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PI_FAM15CZ_CHIP_H_ +#define _PI_FAM15CZ_CHIP_H_ + +struct northbridge_amd_pi_00660F01_config +{ + u8 spdAddrLookup[2][2][4]; +}; + +#endif diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c new file mode 100644 index 0000000..8afa7a6 --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_def.h> +#include <device/device.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "chip.h" +#include "northbridge/amd/pi/dimmSpd.h" + +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + int spdAddress; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; + + if ((dev == 0) || (config == 0)) + return AGESA_ERROR; + if (info->SocketId >= DIMENSION(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + spdAddress = config->spdAddrLookup + [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) + return AGESA_ERROR; + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + if (err) + return AGESA_ERROR; + return AGESA_SUCCESS; +} diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c new file mode 100644 index 0000000..4c6e527 --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -0,0 +1,1232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <lib.h> +#include <cpu/cpu.h> +#include <cbmem.h> + +#include <Porting.h> +#include <AGESA.h> +#include <FieldAccessors.h> +#include <Options.h> +#include <Topology.h> +#include <cpu/amd/amdfam15.h> +#include <cpuRegisters.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include "northbridge.h" + +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp << 21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] + d.base |= temp << 21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit + for (i = 0; i < node_nums; i++) + pci_write_config32(__f1_dev[i], reg + 4, tempreg); + tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? + for (i = 0; i < node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid << 4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure does not exist, usable + * @retval 0 resource exists, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + + if (!res) + result = 2; + else if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + else + result = 0; + + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result >= 1) { + free_reg = reg; + } + if (result == 1) { + /* resource allocated */ + break; + } + } + resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result >= 1) { + free_reg = reg; + } + if (result == 1) { + /* I have been allocated this one */ + break; + } + } + resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); + return resource; +} + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_IO_HOST_ALIGN); + resource->gran = log2(HT_IO_HOST_ALIGN); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } +} + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) + return; + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) + return; + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) + return; + + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + snprintf(buf, sizeof(buf), " <node %x link %x>", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + /* do we need this? */ + create_vga_resource(dev, nodeid); + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +static void northbridge_fill_ssdt_generator(void) +{ + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static unsigned long agesa_write_acpi_tables(unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current, acpi_fill_hest); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT, +}; + +static void fam15_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + +struct chip_operations northbridge_amd_pi_00660F01_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, + .final = fam15_finalize, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg < 0xc0) { // mmio + nodeid = (limit & 0xf) + (base & 0x30); + } else { // io + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if !CONFIG_PCI_64BIT_PREF_MEM + pci_domain_read_resources(dev); + +#else + struct bus *link; + struct resource *resource; + for (link = dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0 | (link->link_num << 2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1 | (link->link_num << 2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2 | (link->link_num << 2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void domain_enable_resources(device_t dev) +{ + if (acpi_is_wakeup_s3()) + AGESAWRAPPER(fchs3laterestore); + + /* Must be called after PCI enumeration and resource allocation */ + if (!acpi_is_wakeup_s3()) + AGESAWRAPPER(amdinitmid); + + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 2) { + /* we find the hole */ + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + /* We need to double check if there is special set on base reg and limit reg + * are not continuous instead of hole, it will find out its hole_startk. + */ + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(i); + if (!(d.base & 1)) + continue; + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (base_k > 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +#define ONE_MB_SHIFT 20 +#define ONE_GB_SHIFT 30 + +static void setup_uma_memory(void) +{ +#if CONFIG_GFXUMA + uint64_t topmem = bsp_topmem(); + uint64_t topmem2 = bsp_topmem2(); + uint32_t sysmem_mb, sysmem_gb; + + /* refer to UMA_AUTO size computation in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeML() */ + /* + * Total system memory UMASize + * >= 6G 1024M + * >= 4G 512M + * >= 2G 256M + * < 2G 128M + */ + + sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocated for C6 when finding UMA size + sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; + sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); + printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", + __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); + if (sysmem_gb >= 6) { + uma_memory_size = 1024 << ONE_MB_SHIFT; + } else if (sysmem_gb >= 4) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else if (sysmem_gb >= 2) { + uma_memory_size = 256 << ONE_MB_SHIFT; + } else { + uma_memory_size = 128 << ONE_MB_SHIFT; + } + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#endif +} + + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + u64 ramtop = 0; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + * MMIO hole. If you fix this here, please fix amdk8, too. + */ + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) + continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + /* split the region to accommodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + if (!ramtop) + ramtop = mmio_basek * 1024; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + uint64_t topmem2 = bsp_topmem2(); + basek = 4*1024*1024; + sizek = topmem2/1024 - basek; + } + } + + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (!ramtop) + ramtop = limitk * 1024; + } + +#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + u32 modules = 0; + VOID* modules_ptr = &modules; + BUILD_OPT_CFG* options = NULL; + int ioapic_count = 0; + + AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); + AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); + modules = (*(u32*)modules_ptr) && ((1ull << (sizeof(modules) * 8)) - 1); + ASSERT(modules > 0); + ASSERT(options); + ioapic_count = (int)options->CfgPlatNumIoApics; + ASSERT(ioapic_count > 0); + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums > 32) { + /* need to put node 32 to node 63 to bus 0xfe */ + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + add_more_links(cdb_dev, 4); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 6 || family == 7) { + /* f15 and f16 */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + /* default one core */ + siblings = 0; + } + int enable_node = cdb_dev && cdb_dev->enabled; + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + u32 lapicid_start = 0; + + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ + if ((node_nums * core_max) + ioapic_count >= 0x10) { + lapicid_start = (ioapic_count - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + static int done = 0; + + /* Do not delay UMA setup, as a device on the PCI bus may evaluate + the global uma_memory variables already in its enable function. */ + if (!done) { + setup_bsp_ramtop(); + setup_uma_memory(); + done = 1; + } + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = { + CHIP_NAME("AMD FAM16 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + +/********************************************************************* + * Change the vendor / device IDs to match the generic VBIOS header. * + *********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev; + new_vendev = + ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev; + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + + return new_vendev; +} diff --git a/src/northbridge/amd/pi/00660F01/northbridge.h b/src/northbridge/amd/pi/00660F01/northbridge.h new file mode 100644 index 0000000..0748c1d --- /dev/null +++ b/src/northbridge/amd/pi/00660F01/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H +#define NORTHBRIDGE_AMD_AGESA_FAM16H_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */ diff --git a/src/northbridge/amd/pi/BiosCallOuts.h b/src/northbridge/amd/pi/BiosCallOuts.h index d5fe66f..002efbf 100644 --- a/src/northbridge/amd/pi/BiosCallOuts.h +++ b/src/northbridge/amd/pi/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "Porting.h" #include "AGESA.h" -#if CONFIG_NORTHBRIDGE_AMD_PI_00630F01 || CONFIG_NORTHBRIDGE_AMD_PI_00730F01 +#if CONFIG_NORTHBRIDGE_AMD_PI_00630F01 || CONFIG_NORTHBRIDGE_AMD_PI_00730F01 || CONFIG_NORTHBRIDGE_AMD_PI_00660F01 #define BIOS_HEAP_START_ADDRESS 0x010000000 #define BIOS_HEAP_SIZE 0x30000 diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 03bdd6b..950126b 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -34,5 +34,6 @@ config S3_VGA_ROM_RUN source src/northbridge/amd/pi/00630F01/Kconfig source src/northbridge/amd/pi/00730F01/Kconfig +source src/northbridge/amd/pi/00660F01/Kconfig endif # NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index de83c51..ea92035 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -21,6 +21,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 romstage-y += agesawrapper.c romstage-y += def_callouts.c diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 1236932..6730c56 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -305,8 +305,10 @@ AGESA_STATUS agesawrapper_amdinitlate(void) DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) AcpiSrat = AmdLateParams->AcpiSrat; AcpiSlit = AmdLateParams->AcpiSlit; +#endif AcpiWheaMce = AmdLateParams->AcpiWheaMce; AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;

1 0

Patch set updated for coreboot: d3f6b12 southbridge/amd/pi: Add support for new AMD southbridge kern
by WANG Siyuan 05 Jun '15

05 Jun '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10418 -gerrit commit d3f6b122fe472aceaf215250f611314f485c10a7 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed May 20 14:41:01 2015 +0800 southbridge/amd/pi: Add support for new AMD southbridge kern Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/include/device/pci_ids.h | 7 ++ src/southbridge/amd/common/Makefile.inc | 1 + src/southbridge/amd/pi/Makefile.inc | 1 + src/southbridge/amd/pi/hudson/Kconfig | 13 ++- src/southbridge/amd/pi/hudson/Makefile.inc | 112 +++++++++++++++++++++- src/southbridge/amd/pi/hudson/acpi/fch.asl | 2 + src/southbridge/amd/pi/hudson/acpi/lpc.asl | 2 + src/southbridge/amd/pi/hudson/acpi/pcie.asl | 8 ++ src/southbridge/amd/pi/hudson/acpi/usb.asl | 4 +- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 5 + src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 4 + src/southbridge/amd/pi/hudson/hda.c | 7 +- src/southbridge/amd/pi/hudson/lpc.c | 8 +- src/southbridge/amd/pi/hudson/sata.c | 16 ++-- src/southbridge/amd/pi/hudson/usb.c | 34 ++----- 15 files changed, 185 insertions(+), 39 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a02a27c..13e66db 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -427,6 +427,13 @@ #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 +#define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A +#define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E +#define PCI_DEVICE_ID_AMD_CZ_SATA 0x7900 +#define PCI_DEVICE_ID_AMD_CZ_SATA_AHCI 0x7901 +#define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 +#define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 + #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 #define PCI_DEVICE_ID_VLSI_82C593 0x0006 diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 1f847cd..50adf7b 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -5,3 +5,4 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += amd_pci_util.c diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc index f1e81ea..b7a2656 100644 --- a/src/southbridge/amd/pi/Makefile.inc +++ b/src/southbridge/amd/pi/Makefile.inc @@ -18,3 +18,4 @@ # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += hudson +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += hudson diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 7825b4d..36716fa 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -29,7 +29,13 @@ config SOUTHBRIDGE_AMD_PI_AVALON select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET -if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON +config SOUTHBRIDGE_AMD_PI_KERN + bool + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_HARD_RESET + +if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -79,16 +85,18 @@ config HUDSON_GEC_FWM config HUDSON_PSP bool - default y if CPU_AMD_PI_00730F01 + default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON + default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON + default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE @@ -127,6 +135,7 @@ config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 + default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01 config HUDSON_SATA_MODE int "SATA Mode" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c5978f1..5e8dbc2 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -99,6 +99,13 @@ HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ 65536) HUDSON_PSP_DIRECTORY_SIZE=256 +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +HUDSON_PSP_DIRECTORY_POSITION=$(call int-align,\ + $(call int-add,\ + $(HUDSON_FWM_POSITION) $(ROMSIG_SIZE) $(CBFS_HEADER_SIZE) $(XHCI_FWM_SIZE)\ + $(CBFS_HEADER_SIZE) $(GEC_FWM_SIZE) $(CBFS_HEADER_SIZE) $(IMC_FWM_SIZE) $(CBFS_HEADER_SIZE)),\ + 65536) +HUDSON_PSP_DIRECTORY_SIZE=256 else HUDSON_PSP_DIRECTORY_POSITION=0 HUDSON_PSP_DIRECTORY_SIZE=0 @@ -172,48 +179,110 @@ FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE= endif +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_TYPE=CZ +endif + +#5 CONFIG_PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key PUBSIGNEDKEY_POS=$(call int-align, \ $(call int-add,$(AMDPUBKEY_POS) $(AMDPUBKEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PUBSIGNEDKEY_SIZE=$(call file-size,$(CONFIG_PUBSIGNEDKEY_FILE)) +#1 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader$(FIRMWARE_TYPE).Bypass.sbin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +endif PSPBTLDR_POS=$(call int-align, \ $(call int-add,$(PUBSIGNEDKEY_POS) $(PUBSIGNEDKEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPBTLDR_SIZE=$(call file-size,$(CONFIG_PSPBTLDR_FILE)) +#3 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery$(FIRMWARE_TYPE).sbin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +endif PSPRCVR_POS=$(call int-align, \ $(call int-add,$(PSPBTLDR_POS) $(PSPBTLDR_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPRCVR_SIZE=$(call file-size,$(CONFIG_PSPRCVR_FILE)) +#2 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs$(FIRMWARE_TYPE).sbin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).sbin +endif PSPSECUREOS_POS=$(call int-align, \ $(call int-add,$(PSPRCVR_POS) $(PSPRCVR_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPSECUREOS_SIZE=$(call file-size,$(CONFIG_PSPSCUREOS_FILE)) +#4 CONFIG_PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin PSPNVRAM_POS=$(call int-align, \ $(call int-add,$(PSPSECUREOS_POS) $(PSPSECUREOS_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) PSPNVRAM_SIZE=$(call file-size,$(CONFIG_PSPNVRAM_FILE)) +#8 CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_POS=$(call int-align, \ $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) +#95 CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin SMUSCS_POS=$(call int-align, \ $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) +#9 +CONFIG_PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +PSPSECUREDEBUG_POS=$(call int-align, \ + $(call int-add,$(SMUSCS_POS) $(SMUSCS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +PSPSECUREDEBUG_SIZE=$(call file-size,$(CONFIG_PSPSECUREDEBUG_FILE)) + +#12 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) +CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_$(FIRMWARE_TYPE).cbin +endif +PSPTRUSTLETS_POS=$(call int-align, \ + $(call int-add,$(PSPSECUREDEBUG_POS) $(PSPSECUREDEBUG_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +PSPTRUSTLETS_SIZE=$(call file-size,$(CONFIG_PSPTRUSTLETS_FILE)) + +#13 +ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) +CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +endif +TRUSTLETKEY_POS=$(call int-align, \ + $(call int-add,$(PSPTRUSTLETS_POS) $(PSPTRUSTLETS_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLETKEY_SIZE=$(call file-size,$(CONFIG_TRUSTLETKEY_FILE)) + +#18 +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +SMUFIRMWARE2_POS=$(call int-align, \ + $(call int-add,$(TRUSTLETKEY_POS) $(TRUSTLETKEY_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +SMUFIRMWARE2_SIZE=$(call file-size,$(CONFIG_SMUFIRMWARE2_FILE)) +endif + define output_hex echo $(1) | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}' endef @@ -241,10 +310,24 @@ $(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp + for fwm in 9 $(PSPSECUREDEBUG_SIZE) $(PSPSECUREDEBUG_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp + for fwm in 12 $(PSPTRUSTLETS_SIZE) $(PSPTRUSTLETS_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp + for fwm in 13 $(TRUSTLETKEY_SIZE) $(TRUSTLETKEY_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) + for fwm in 18 $(SMUFIRMWARE2_SIZE) $(SMUFIRMWARE2_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp +endif for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp - for fwm in 11 4294967295 0 0; do \ + for fwm in 11 4294967295 1 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp for fwm in 1347637284 0 `ls -l $(a)_tail.tmp | awk '{printf("%d", $$5/16);}'` 0; do \ @@ -300,9 +383,36 @@ apu/smufwm-file := $(CONFIG_SMUFWM_FILE) apu/smufwm-position := $(SMUFWM_POS) apu/smufwm-type := raw +#95 cbfs-files-y += apu/smuscs apu/smuscs-file := $(CONFIG_SMUSCS_FILE) apu/smuscs-position := $(SMUSCS_POS) apu/smuscs-type := raw +#9 +cbfs-files-y += apu/pspsecuredebug +apu/pspsecuredebug-file := $(CONFIG_PSPSECUREDEBUG_FILE) +apu/pspsecuredebug-position := $(PSPSECUREDEBUG_POS) +apu/pspsecuredebug-type := raw + +#12 +cbfs-files-y += apu/psptrustlets +apu/psptrustlets-file := $(CONFIG_PSPTRUSTLETS_FILE) +apu/psptrustlets-position := $(PSPTRUSTLETS_POS) +apu/psptrustlets-type := raw + +#13 +cbfs-files-y += apu/trustletkey +apu/trustletkey-file := $(CONFIG_TRUSTLETKEY_FILE) +apu/trustletkey-position := $(TRUSTLETKEY_POS) +apu/trustletkey-type := raw + +#18 +ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) +cbfs-files-y += apu/smufirmware2 +apu/smufirmware2-file := $(CONFIG_SMUFIRMWARE2_FILE) +apu/smufirmware2-position := $(SMUFIRMWARE2_POS) +apu/smufirmware2-type := raw +endif + endif diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index d638942..0f1651f 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -45,7 +45,9 @@ Method(_OSC,4) /* 0:11.0 - SATA */ Device(STCR) { Name(_ADR, 0x00110000) +#ifndef CONFIG_CPU_AMD_PI_00660F01 #include "acpi/sata.asl" +#endif } /* end STCR */ /* 0:14.0 - SMBUS */ diff --git a/src/southbridge/amd/pi/hudson/acpi/lpc.asl b/src/southbridge/amd/pi/hudson/acpi/lpc.asl index 35b4d9d..120f02c 100644 --- a/src/southbridge/amd/pi/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/pi/hudson/acpi/lpc.asl @@ -104,5 +104,7 @@ Device(LIBR) { IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#ifndef CONFIG_CPU_AMD_PI_00660F01 #include "acpi/superio.asl" +#endif } /* end LIBR */ diff --git a/src/southbridge/amd/pi/hudson/acpi/pcie.asl b/src/southbridge/amd/pi/hudson/acpi/pcie.asl index dbf4ccb..0626cab 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pcie.asl @@ -90,6 +90,14 @@ } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x60), /* AcpiPm1EvgBlk */ + P1EB, 16, Offset(0xEE), UPWS, 3, } + OperationRegion (P1E0, SystemIO, P1EB, 0x04) + Field (P1E0, ByteAcc, Nolock, Preserve) { + Offset(0x02), + , 14, + PEWD, 1, + } diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl index 453d792..9b56985 100644 --- a/src/southbridge/amd/pi/hudson/acpi/usb.asl +++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl @@ -54,7 +54,7 @@ Device(UOH6) { Name(_PRW, Package() {0x0B, 3}) } /* end UOH5 */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON +#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:14.5 - OHCI */ Device(UEH1) { Name(_ADR, 0x00140005) @@ -68,7 +68,7 @@ Device(XHC0) { Name(_PRW, Package() {0x0B, 4}) } /* end XHC0 */ -#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON +#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN /* 0:10.1 - XHCI 1*/ Device(XHC1) { Name(_ADR, 0x00100001) diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 2ca9147..a1e5e07 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -80,4 +80,9 @@ #define PIRQ_GPP3 0x53 /* GPP INT 3 */ #endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) +#define FCH_INT_TABLE_SIZE 0x75 +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif + #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index ad26d63..b48f87e 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -33,6 +33,10 @@ const char * intr_types[] = { #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) [0x40] = "IDE\t", "SATA\t", [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", + [0x75] = NULL #endif }; diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 3002dc5..1eb7759 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -26,6 +26,11 @@ #include <delay.h> #include "hudson.h" +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_HDA, + PCI_DEVICE_ID_AMD_CZ_HDA, + 0 +}; static void hda_init(struct device *dev) { @@ -47,5 +52,5 @@ static struct device_operations hda_audio_ops = { static const struct pci_driver hdaaudio_driver __pci_driver = { .ops = &hda_audio_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_HDA, + .devices = pci_device_ids, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 840ff7a..2f843f3 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -343,8 +343,14 @@ static struct device_operations lpc_ops = { .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_LPC, + PCI_DEVICE_ID_AMD_CZ_LPC, + 0 +}; static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_LPC, + .devices = pci_device_ids, }; diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 8b8a79a..1d2cd93 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -29,7 +29,7 @@ static void sata_init(struct device *dev) { -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) /************************************** * Configure the SATA port multiplier * **************************************/ @@ -72,14 +72,16 @@ static struct device_operations sata_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_SATA, +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_SATA, + PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, + PCI_DEVICE_ID_AMD_CZ_SATA, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + 0 }; -static const struct pci_driver sata0_driver_ahci __pci_driver = { +static const struct pci_driver sata0_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, + .devices = pci_device_ids, }; diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index 6438be1..f686521 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -43,35 +43,19 @@ static struct device_operations usb_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_ATI_SB900_USB_18_0, + PCI_DEVICE_ID_ATI_SB900_USB_18_2, + PCI_DEVICE_ID_ATI_SB900_USB_20_5, + PCI_DEVICE_ID_AMD_CZ_USB_0, + PCI_DEVICE_ID_AMD_CZ_USB_1, + 0 }; -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, -}; - -/* the pci id of usb ctrl 0 and 1 are the same. */ -/* - * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_AMD, - * .device = PCI_DEVICE_ID_ATI_HUDSON_USB_19_0, - * }; - * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_AMD, - * .device = PCI_DEVICE_ID_ATI_HUDSON_USB_19_1, - * }; - */ -static const struct pci_driver usb_4_driver __pci_driver = { +static const struct pci_driver usb_0_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, + .devices = pci_device_ids, }; /*

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coreboot-gerrit June 2015