coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 3a7e55c mainboard/lenovo/t400: Use HDA verbs from Lenovo BIOS
by Michał Masłowski 05 Jun '15

05 Jun '15

Michał Masłowski (mtjm(a)mtjm.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10431 -gerrit commit 3a7e55cd273f3c01fa1f8f44e0f31d18070208af Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Fri Jun 5 15:40:48 2015 +0200 mainboard/lenovo/t400: Use HDA verbs from Lenovo BIOS The same values are used on my Lenovo R400 as reported by Francis Rowe from his T400 and T500. TEST: Read /proc/asound/card0/codec#0, see that the jack locations correspond to the board layout, e.g. headphone and microphone connectors are on front of the laptop, not right. Read /sys/class/sound/hwC0D0/init_pin_configs, see that it has the same content with coreboot and Lenovo BIOS. Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> --- src/mainboard/lenovo/t400/hda_verb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t400/hda_verb.c b/src/mainboard/lenovo/t400/hda_verb.c index beb637f..423d10c 100644 --- a/src/mainboard/lenovo/t400/hda_verb.c +++ b/src/mainboard/lenovo/t400/hda_verb.c @@ -23,15 +23,15 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14f15051, // Conexant CX20561 (Hermosa) - 0x17aa20ff, // Subsystem ID + 0x17aa211c, // Subsystem ID 0x00000008, // Number of entries /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0, 0x16, 0x042140f0), + AZALIA_PIN_CFG(0, 0x16, 0x022140f0), AZALIA_PIN_CFG(0, 0x17, 0x61a190f0), - AZALIA_PIN_CFG(0, 0x18, 0x04a190f0), - AZALIA_PIN_CFG(0, 0x19, 0x612140f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a190f0), + AZALIA_PIN_CFG(0, 0x19, 0x40f000f0), AZALIA_PIN_CFG(0, 0x1a, 0x901701f0), AZALIA_PIN_CFG(0, 0x1b, 0x40f001f0), AZALIA_PIN_CFG(0, 0x1c, 0x40f001f0),

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Patch set updated for coreboot: 83feda2 lenovo/r400: Add clone of Lenovo T400
by Michał Masłowski 05 Jun '15

05 Jun '15

Michał Masłowski (mtjm(a)mtjm.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8393 -gerrit commit 83feda25918544d0e4b003f80460e0f7741930a0 Author: Michał Masłowski <mtjm(a)mtjm.eu> Date: Tue Feb 3 23:26:05 2015 +0100 lenovo/r400: Add clone of Lenovo T400 The existing code for the Lenovo T400 works without changes on the Lenovo R400. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9 Signed-off-by: Michał Masłowski <mtjm(a)mtjm.eu> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/mainboard/lenovo/r400/Kconfig | 7 +++++++ src/mainboard/lenovo/r400/Kconfig.name | 2 ++ src/mainboard/lenovo/r400/board_info.txt | 6 ++++++ src/mainboard/lenovo/t400/Kconfig | 6 +++++- 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/r400/Kconfig b/src/mainboard/lenovo/r400/Kconfig new file mode 100644 index 0000000..0966bf1 --- /dev/null +++ b/src/mainboard/lenovo/r400/Kconfig @@ -0,0 +1,7 @@ +if BOARD_LENOVO_R400 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad R400" + +endif diff --git a/src/mainboard/lenovo/r400/Kconfig.name b/src/mainboard/lenovo/r400/Kconfig.name new file mode 100644 index 0000000..15a99b1 --- /dev/null +++ b/src/mainboard/lenovo/r400/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_R400 + bool "ThinkPad R400" diff --git a/src/mainboard/lenovo/r400/board_info.txt b/src/mainboard/lenovo/r400/board_info.txt new file mode 100644 index 0000000..007ec6c --- /dev/null +++ b/src/mainboard/lenovo/r400/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-16 or SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Clone of: lenovo/t400 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a1d0652..2ea592f 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T400 +if BOARD_LENOVO_T400 || BOARD_LENOVO_R400 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -26,10 +26,14 @@ config MAINBOARD_DIR string default lenovo/t400 +if BOARD_LENOVO_T400 + config MAINBOARD_PART_NUMBER string default "ThinkPad T400" +endif + config MMCONF_BASE_ADDRESS hex default 0xf0000000

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Patch merged into coreboot/master: 7a8a4ab lib: Unify log2() and related functions
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 7a8a4ab1d88a411ee0dad23318f98b4f29fd2f60 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 22 16:26:40 2015 -0700 lib: Unify log2() and related functions This patch adds a few bit counting functions that are commonly needed for certain register calculations. We previously had a log2() implementation already, but it was awkwardly split between some C code that's only available in ramstage and an optimized x86-specific implementation in pre-RAM that prevented other archs from pulling it into earlier stages. Using __builtin_clz() as the baseline allows GCC to inline optimized assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and to perform constant-folding if possible. What was previously named log2f on pre-RAM x86 is now ffs, since that's the standard name for that operation and I honestly don't have the slightest idea how it could've ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm with Float result, whereas the Find First Set operation has no direct correlation to logarithms that I know of). Make ffs result 0-based instead of the POSIX standard's 1-based since that is consistent with clz, log2 and the former log2f, and generally closer to what you want for most applications (a value that can directly be used as a shift to reach the found bit). Call it __ffs() instead of ffs() to avoid problems when importing code, since that's what Linux uses for the 0-based operation. CQ-DEPEND=CL:273023 BRANCH=None BUG=None TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new log2() and __ffs() results on Falco for a bunch of test values. Change-Id: I599209b342059e17b3130621edb6b6bbeae26876 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273008 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10394 for details. -gerrit

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Patch merged into coreboot/master: 3d02b9c mainboard/lenovo/{t430s, t420s, t520, t530, x220}: Add TPM 1.2 mainboard support
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 3d02b9c79e8dbe661c9e784519c486b8897b6af5 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Jun 3 23:09:36 2015 +0200 mainboard/lenovo/{t430s,t420s,t520,t530,x220}: Add TPM 1.2 mainboard support Every Lenovo Thinkpad includes a Trusted Platform Module, so we can enable it for the sandy-/ivybridge platforms. Change-Id: Icda443ba88c2a49a0033014ce7710dd607fa15dc Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: http://review.coreboot.org/10411 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10411 for details. -gerrit

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New patch to review for coreboot: 37fe58c cbmem: Break out CBMEM_ID to a separate header file
by Marc Jones 05 Jun '15

05 Jun '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10430 -gerrit commit 37fe58cf023b83c52310a7d26d51ad44effd2e1f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Jun 4 23:36:01 2015 -0600 cbmem: Break out CBMEM_ID to a separate header file The cbmem util needs the CBMEM_IDs and the strings for reporting and shares the cbmem.h file with coreboot. Split out the IDs so for a simpler sharing and no wories about overlap of standard libraries and other things in the header that coreboot requires, but the tool does not. Change-Id: Iba760c5f99c5e9838ba9426e284b59f02bcc507a Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/include/cbmem.h | 91 +-------------------------------------- src/include/cbmem_id.h | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ util/cbmem/cbmem.c | 2 +- 3 files changed, 117 insertions(+), 90 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index afee873..6e8e5f9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -21,6 +21,8 @@ #ifndef _CBMEM_H_ #define _CBMEM_H_ +#include <cbmem_id.h> + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) @@ -35,99 +37,10 @@ #define CBMEM_RESUME_BACKUP 0x614 #define CBMEM_FSP_HOB_PTR 0x614 -#define CBMEM_ID_ACPI 0x41435049 -#define CBMEM_ID_ACPI_GNVS 0x474e5653 -#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650 -#define CBMEM_ID_AGESA_RUNTIME 0x41474553 -#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E -#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 -#define CBMEM_ID_CBTABLE 0x43425442 -#define CBMEM_ID_CONSOLE 0x434f4e53 -#define CBMEM_ID_COVERAGE 0x47434f56 -#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 -#define CBMEM_ID_ELOG 0x454c4f47 -#define CBMEM_ID_FREESPACE 0x46524545 -#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052 -#define CBMEM_ID_FSP_RUNTIME 0x52505346 -#define CBMEM_ID_GDT 0x4c474454 -#define CBMEM_ID_HOB_POINTER 0x484f4221 -#define CBMEM_ID_IGD_OPREGION 0x4f444749 -#define CBMEM_ID_IMD_ROOT 0xff4017ff -#define CBMEM_ID_IMD_SMALL 0x53a11439 -#define CBMEM_ID_MEMINFO 0x494D454D -#define CBMEM_ID_MPTABLE 0x534d5054 -#define CBMEM_ID_MRCDATA 0x4d524344 -#define CBMEM_ID_NONE 0x00000000 -#define CBMEM_ID_PIRQ 0x49525154 -#define CBMEM_ID_POWER_STATE 0x50535454 -#define CBMEM_ID_RAM_OOPS 0x05430095 -#define CBMEM_ID_RAMSTAGE 0x9a357a9e -#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e -#define CBMEM_ID_REFCODE 0x04efc0de -#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5 -#define CBMEM_ID_RESUME 0x5245534d -#define CBMEM_ID_RESUME_SCRATCH 0x52455343 -#define CBMEM_ID_ROMSTAGE_INFO 0x47545352 -#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 -#define CBMEM_ID_ROOT 0xff4007ff -#define CBMEM_ID_SMBIOS 0x534d4254 -#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee -#define CBMEM_ID_SPINTABLE 0x59175917 -#define CBMEM_ID_STAGEx_META 0x57a9e000 -#define CBMEM_ID_STAGEx_CACHE 0x57a9e100 -#define CBMEM_ID_TIMESTAMP 0x54494d45 -#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 -#define CBMEM_ID_VBOOT_WORKBUF 0x78007343 -#define CBMEM_ID_WIFI_CALIBRATION 0x57494649 -#define CBMEM_ID_TCPA_LOG 0x54435041 - #ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> -#define CBMEM_ID_TO_NAME_TABLE \ - { CBMEM_ID_ACPI, "ACPI " }, \ - { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ - { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \ - { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ - { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ - { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ - { CBMEM_ID_CBTABLE, "COREBOOT " }, \ - { CBMEM_ID_CONSOLE, "CONSOLE " }, \ - { CBMEM_ID_COVERAGE, "COVERAGE " }, \ - { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ - { CBMEM_ID_ELOG, "ELOG " }, \ - { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ - { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \ - { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ - { CBMEM_ID_GDT, "GDT " }, \ - { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \ - { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ - { CBMEM_ID_MEMINFO, "MEM INFO " }, \ - { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ - { CBMEM_ID_MRCDATA, "MRC DATA " }, \ - { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ - { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ - { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ - { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \ - { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \ - { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \ - { CBMEM_ID_REFCODE, "REFCODE " }, \ - { CBMEM_ID_RESUME, "ACPI RESUME" }, \ - { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \ - { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \ - { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \ - { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ - { CBMEM_ID_SMBIOS, "SMBIOS " }, \ - { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ - { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \ - { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ - { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ - { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ - { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, - -struct cbmem_entry; - /* * The dynamic cbmem infrastructure allows for growing cbmem dynamically as * things are added. It requires an external function, cbmem_top(), to be diff --git a/src/include/cbmem_id.h b/src/include/cbmem_id.h new file mode 100644 index 0000000..abea030 --- /dev/null +++ b/src/include/cbmem_id.h @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _CBMEM_ID_H_ +#define _CBMEM_ID_H_ + +#define CBMEM_ID_ACPI 0x41435049 +#define CBMEM_ID_ACPI_GNVS 0x474e5653 +#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650 +#define CBMEM_ID_AGESA_RUNTIME 0x41474553 +#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E +#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 +#define CBMEM_ID_CBTABLE 0x43425442 +#define CBMEM_ID_CONSOLE 0x434f4e53 +#define CBMEM_ID_COVERAGE 0x47434f56 +#define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 +#define CBMEM_ID_ELOG 0x454c4f47 +#define CBMEM_ID_FREESPACE 0x46524545 +#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052 +#define CBMEM_ID_FSP_RUNTIME 0x52505346 +#define CBMEM_ID_GDT 0x4c474454 +#define CBMEM_ID_HOB_POINTER 0x484f4221 +#define CBMEM_ID_IGD_OPREGION 0x4f444749 +#define CBMEM_ID_IMD_ROOT 0xff4017ff +#define CBMEM_ID_IMD_SMALL 0x53a11439 +#define CBMEM_ID_MEMINFO 0x494D454D +#define CBMEM_ID_MPTABLE 0x534d5054 +#define CBMEM_ID_MRCDATA 0x4d524344 +#define CBMEM_ID_NONE 0x00000000 +#define CBMEM_ID_PIRQ 0x49525154 +#define CBMEM_ID_POWER_STATE 0x50535454 +#define CBMEM_ID_RAM_OOPS 0x05430095 +#define CBMEM_ID_RAMSTAGE 0x9a357a9e +#define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e +#define CBMEM_ID_REFCODE 0x04efc0de +#define CBMEM_ID_REFCODE_CACHE 0x4efc0de5 +#define CBMEM_ID_RESUME 0x5245534d +#define CBMEM_ID_RESUME_SCRATCH 0x52455343 +#define CBMEM_ID_ROMSTAGE_INFO 0x47545352 +#define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 +#define CBMEM_ID_ROOT 0xff4007ff +#define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee +#define CBMEM_ID_SPINTABLE 0x59175917 +#define CBMEM_ID_STAGEx_META 0x57a9e000 +#define CBMEM_ID_STAGEx_CACHE 0x57a9e100 +#define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 +#define CBMEM_ID_VBOOT_WORKBUF 0x78007343 +#define CBMEM_ID_WIFI_CALIBRATION 0x57494649 +#define CBMEM_ID_TCPA_LOG 0x54435041 + +#ifndef __ASSEMBLER__ +#define CBMEM_ID_TO_NAME_TABLE \ + { CBMEM_ID_ACPI, "ACPI " }, \ + { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ + { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \ + { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ + { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ + { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ + { CBMEM_ID_CBTABLE, "COREBOOT " }, \ + { CBMEM_ID_CONSOLE, "CONSOLE " }, \ + { CBMEM_ID_COVERAGE, "COVERAGE " }, \ + { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ + { CBMEM_ID_ELOG, "ELOG " }, \ + { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ + { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \ + { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ + { CBMEM_ID_GDT, "GDT " }, \ + { CBMEM_ID_IMD_ROOT, "IMD ROOT " }, \ + { CBMEM_ID_IMD_SMALL, "IMD SMALL " }, \ + { CBMEM_ID_MEMINFO, "MEM INFO " }, \ + { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ + { CBMEM_ID_MRCDATA, "MRC DATA " }, \ + { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ + { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ + { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, \ + { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, \ + { CBMEM_ID_RAMSTAGE, "RAMSTAGE " }, \ + { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, \ + { CBMEM_ID_REFCODE, "REFCODE " }, \ + { CBMEM_ID_RESUME, "ACPI RESUME" }, \ + { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, \ + { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, \ + { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \ + { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ + { CBMEM_ID_SMBIOS, "SMBIOS " }, \ + { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ + { CBMEM_ID_SPINTABLE, "SPIN TABLE " }, \ + { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ + { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ + { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ + { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, + +struct cbmem_entry; +#endif /* __ASSEMBLER__ */ +#endif /* _CBMEM_ID_H_ */ diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index e294c20..3bc0fcd 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -46,7 +46,7 @@ typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; -#include "cbmem.h" +#include "cbmem_id.h" #include "timestamp.h" #define CBMEM_VERSION "1.1"

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Patch set updated for coreboot: ff30ba7 cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() API
by Marc Jones 05 Jun '15

05 Jun '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7878 -gerrit commit ff30ba7beaa8b4dc2a0ad799bceaaa04d39c8c17 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 7 04:48:43 2015 +0200 cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() API Squashed and adjusted two changes from chromium.git. Covers CBMEM init for ROMTAGE and RAMSTAGE. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 1 - src/arch/x86/boot/cbmem.c | 22 ---------------------- src/arch/x86/boot/gdt.c | 3 ++- src/arch/x86/include/arch/early_variables.h | 12 ------------ src/arch/x86/init/romstage.ld | 9 ++++----- src/cpu/x86/car.c | 18 +++--------------- src/drivers/usb/ehci_debug.c | 2 +- src/include/cbmem.h | 22 ++++++++++++++++++++++ src/include/console/cbmem_console.h | 6 ------ src/include/cpu/x86/gdt.h | 3 --- src/include/symbols.h | 4 ++++ src/include/timestamp.h | 2 -- src/lib/cbmem_common.c | 22 ++++++++++------------ src/lib/cbmem_console.c | 7 +++---- src/lib/ramstage.ld | 3 +++ src/lib/rmodule.ld | 3 +++ src/lib/romstage.ld | 4 ++++ src/lib/timestamp.c | 7 ++++--- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/power_state.c | 2 +- src/soc/nvidia/tegra132/romstage.c | 2 -- 22 files changed, 65 insertions(+), 92 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 725650a..5e09448 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 725650a..5e09448 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index a9127d7..e279db9 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,12 +20,6 @@ #include <cbmem.h> #include <arch/acpi.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <arch/early_variables.h> -#include <cpu/x86/gdt.h> -#include <console/cbmem_console.h> -#include <timestamp.h> - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -71,22 +65,6 @@ void *cbmem_top(void) #endif /* LATE_CBMEM_INIT */ -void cbmem_run_init_hooks(void) -{ - /* Migrate car.global_data. */ - car_migrate_variables(); - -#if !defined(__PRE_RAM__) - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); - - move_gdt(); -#endif -} - /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 9d9517a..e13d3bc 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -32,7 +32,7 @@ struct gdtarg { /* Copy GDT to new location and reload it. * FIXME: We only do this for BSP CPU. */ -void move_gdt(void) +static void move_gdt(void) { void *newgdt; u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; @@ -55,3 +55,4 @@ void move_gdt(void) __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); printk(BIOS_DEBUG, "ok\n"); } +RAMSTAGE_CBMEM_INIT_HOOK(move_gdt) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index bfb1201..d9f1cd7 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -29,13 +29,6 @@ asm(".previous"); #define CAR_GLOBAL __attribute__((used,section(".car.global_data#"))) #endif /* __clang__ */ -#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate"))) - -/* Call migrate_fn_() when CAR globals are migrated. */ -#define CAR_MIGRATE(migrate_fn_) \ - static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \ - migrate_fn_; - /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); @@ -50,17 +43,12 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) -/* Migrate the CAR variables to memory. */ -void car_migrate_variables(void); - #else #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif #endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index ae7049b..74e665f 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -34,15 +34,14 @@ SECTIONS *(.text); *(.text.*); *(.rom.data); + . = ALIGN(4); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); - _car_migrate_start = .; - KEEP(*(.car.migrate)); - LONG(0); - _car_migrate_end = .; - . = ALIGN(16); _erom = .; } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 165a0e6..ffcf0db 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -136,21 +136,9 @@ static void do_car_migrate_variables(void) car_migrated = ~0; } -static void do_car_migrate_hooks(void) +static void car_migrate_variables(void) { - car_migration_func_t *migrate_func; - /* Call all the migration functions. */ - migrate_func = &_car_migrate_start; - while (*migrate_func != NULL) { - (*migrate_func)(); - migrate_func++; - } -} - -void car_migrate_variables(void) -{ - if (!IS_ENABLED(PLATFORM_USES_FSP1_0)) + if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE) && !IS_ENABLED(PLATFORM_USES_FSP1_0)) do_car_migrate_variables(); - - do_car_migrate_hooks(); } +ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 68fd0fa..a6de8b2 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -682,7 +682,7 @@ static void migrate_ehci_debug(void) memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); car_set_var(glob_dbg_info_p, dbg_info_cbmem); } -CAR_MIGRATE(migrate_ehci_debug); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); #endif int dbgp_ep_is_active(struct dbgp_pipe *pipe) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 6e8e5f9..9a76971 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -22,6 +22,7 @@ #define _CBMEM_H_ #include <cbmem_id.h> +#include <rules.h> #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ ! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) @@ -110,6 +111,7 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +typedef void (* const cbmem_init_hook_t)(void); void cbmem_run_init_hooks(void); void cbmem_fail_resume(void); @@ -120,6 +122,26 @@ void cbmem_add_bootmem(void); void cbmem_list(void); #endif /* __PRE_RAM__ */ +#if ENV_RAMSTAGE +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#elif ENV_ROMSTAGE +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#else +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused2_ __attribute__((unused)) = init_fn_; +#endif /* ENV_RAMSTAGE */ + + /* These are for compatibility with old boards only. Any new chipset and board * must implement cbmem_top() for both romstage and ramstage to support * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index e9ec66e..06013f2 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -25,12 +25,6 @@ void cbmemc_init(void); void cbmemc_tx_byte(unsigned char data); -#if CONFIG_CONSOLE_CBMEM -void cbmemc_reinit(void); -#else -static inline void cbmemc_reinit(void) {} -#endif - #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ (ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) && \ (ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE)))) diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 8525a3c..a96b0e4 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -28,7 +28,4 @@ extern char _secondary_gdt_addr[]; extern char _secondary_start[]; extern char _secondary_start_end[]; -/* Defined in src/arch/x86/boot/gdt.c */ -void move_gdt(void); - #endif /* CPU_X86_GDT */ diff --git a/src/include/symbols.h b/src/include/symbols.h index 4a47de1..9102e82 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -33,6 +33,10 @@ extern u8 _epreram_cbmem_console[]; #define _preram_cbmem_console_size \ (_epreram_cbmem_console - _preram_cbmem_console) +extern u8 _cbmem_init_hooks[]; +extern u8 _ecbmem_init_hooks[]; +#define _cbmem_init_hooks_size (_ecbmem_init_hooks - _cbmem_init_hooks) + extern u8 _stack[]; extern u8 _estack[]; #define _stack_size (_estack - _stack) diff --git a/src/include/timestamp.h b/src/include/timestamp.h index d9afeea..a248ea4 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -92,12 +92,10 @@ enum timestamp_id { void timestamp_init(uint64_t base); void timestamp_add(enum timestamp_id id, uint64_t ts_time); void timestamp_add_now(enum timestamp_id id); -void timestamp_reinit(void); #else #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) -#define timestamp_reinit() #endif /* Implemented by the architecture code */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index e9beb5f..496bafa 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,30 +20,28 @@ #include <cbmem.h> #include <bootstate.h> #include <rules.h> +#include <symbols.h> #if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> #endif -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <console/cbmem_console.h> -#include <timestamp.h> - - -/* FIXME: Replace with CBMEM_INIT_HOOKS API. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) void cbmem_run_init_hooks(void) { - /* Relocate CBMEM console. */ - cbmemc_reinit(); + cbmem_init_hook_t *init_hook_ptr = (cbmem_init_hook_t*) &_cbmem_init_hooks; + cbmem_init_hook_t *einit_hook_ptr = (cbmem_init_hook_t*) &_ecbmem_init_hooks; - /* Relocate timestamps stash. */ - timestamp_reinit(); + if (_cbmem_init_hooks_size == 0) + return; + + while (init_hook_ptr != einit_hook_ptr) { + (*init_hook_ptr)(); + init_hook_ptr++; + } } void __attribute__((weak)) cbmem_fail_resume(void) { } -#endif #if ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) static void init_cbmem_post_device(void *unused) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index e9607f3..4866454 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -208,7 +208,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, new_cons_p->buffer_cursor = cursor; } -void cbmemc_reinit(void) +static void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p; const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; @@ -233,6 +233,8 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, size, flags); } +ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) #if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART) void cbmem_dump_console(void) @@ -249,6 +251,3 @@ void cbmem_dump_console(void) uart_tx_byte(0, cbm_cons_p->buffer_body[cursor]); } #endif - -/* Call cbmemc_reinit() at CAR migration time. */ -CAR_MIGRATE(cbmemc_reinit) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 30b18a7..402f495 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -64,6 +64,9 @@ LONG(0); LONG(0); _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata) *(.rodata.*) diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 70a2d3d..0e9c880 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -55,6 +55,9 @@ SECTIONS LONG(0); LONG(0); _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; . = ALIGN(8); diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld index 34e76c0..7d552a7 100644 --- a/src/lib/romstage.ld +++ b/src/lib/romstage.ld @@ -29,6 +29,10 @@ } : to_load .data . : { + . = ALIGN(8); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.data); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 8c82649..3b886b6 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -157,7 +157,7 @@ void timestamp_init(uint64_t base) #endif } -void timestamp_reinit(void) +static void timestamp_reinit(void) { if (!timestamp_should_run()) return; @@ -172,8 +172,9 @@ void timestamp_reinit(void) timestamp_do_sync(); } -/* Call timestamp_reinit at CAR migration time. */ -CAR_MIGRATE(timestamp_reinit) +/* Call timestamp_reinit CBMEM init hooks. */ +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) /* Provide default timestamp implementation using monotonic timer. */ uint64_t __attribute__((weak)) timestamp_get(void) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a32db02..3f35bde 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -158,7 +158,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 22ec8a6..ce52b49 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -50,7 +50,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ static int prev_sleep_state(struct chipset_power_state *ps) diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index fedc1d4..6476e06 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -76,8 +76,6 @@ void romstage(void) romstage_mainboard_init(); - cbmemc_reinit(); - run_ramstage(); }

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Patch merged into coreboot/master: 09705ab AMD K8 fam10: Use parent subordinate to track HT enumeration
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 09705ab72457423fc88672cda932f474fee0cfbe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 21 11:11:58 2015 +0200 AMD K8 fam10: Use parent subordinate to track HT enumeration Change-Id: I930f2beacdc95d0a7edd07db66a1c2e58bb2f3cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8566 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8566 for details. -gerrit

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Patch merged into coreboot/master: ed7bc2c AMD K8 fam10: Drop extra HT scan_chain() parameters
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit ed7bc2c9cfc690cdb23cc9eb317511431c779e89 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 08:27:13 2015 +0200 AMD K8 fam10: Drop extra HT scan_chain() parameters Change-Id: Ice7cb89c19585cf725b6f73c33443050f8d65418 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8565 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8565 for details. -gerrit

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Patch merged into coreboot/master: e8ea712 AMD K8 fam10: Drop local is_sblink in scan_chains
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit e8ea71278c6998f03abd690491fad5f884c618f2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 08:54:45 2015 +0200 AMD K8 fam10: Drop local is_sblink in scan_chains We can define is_sblink = (max == 0) as sblink is always the very first chain we scan. Change-Id: Ibd6b3ea23954ca919ae148604bca2495e9f8753b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8564 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8564 for details. -gerrit

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Patch merged into coreboot/master: 328531f AMD K8 fam10: Drop redundant parameters on scan_chain()
by gerrit＠coreboot.org 05 Jun '15

05 Jun '15

the following patch was just integrated into master: commit 328531ffc70e4f07bbf475a88bc190f47f4b5900 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 28 12:03:20 2015 +0200 AMD K8 fam10: Drop redundant parameters on scan_chain() Change-Id: I6041b666e6792cf97b8273ed54832d86af8ed23e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8563 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/8563 for details. -gerrit

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coreboot-gerrit June 2015