coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d70bf7c cbmem_console: fix it for x86
by gerrit＠coreboot.org 23 Apr '15

23 Apr '15

the following patch was just integrated into master: commit d70bf7cc219f8478e8336f60542a50c078bf531b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 20 15:24:19 2015 -0500 cbmem_console: fix it for x86 The Kconfig options pertaining cbmem console in the preram environment no longer make sense with the linker script changes. Remove them and their usage within cbmem_console. Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9851 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9851 for details. -gerrit

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Patch merged into coreboot/master: be34797 ramstage: don't drop cbmem console
by gerrit＠coreboot.org 23 Apr '15

23 Apr '15

the following patch was just integrated into master: commit be34797e4c2a5b74bb8fcbbe9e4301b471d185e5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 21 11:57:18 2015 -0500 ramstage: don't drop cbmem console In commit b0d8f5e9 I moved the call to cbmem_initialize() in the CONFIG_EARLY_CBMEM_INIT case to the very beginning of ramstage. However, that caused an issue in the ordering of the cbmem console driver in that it expects cbmemc_init() to be called prior to cbmemc_reinit(). Therefore, ensure console is called as the first thing even if some time is lost w.r.t. timestamp tracking. Change-Id: I42137d28116e0bccb9235f4e3f394d4fd8b84e37 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9933 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9933 for details. -gerrit

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Patch merged into coreboot/master: 58decc5 memlayout: Make sure preram_cbmem_console symbols exist
by gerrit＠coreboot.org 23 Apr '15

23 Apr '15

the following patch was just integrated into master: commit 58decc540dd40c180542d214f74773c7c17b4f28 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 23 14:40:22 2015 +0200 memlayout: Make sure preram_cbmem_console symbols exist This enables its _size variable (a macro) to work even when the console has no location assigned to it in the chip/board's memlayout.ld. Since _size == 0, the code will do the right thing. Change-Id: I6b42ed0c5c3aaa613603680728b61cbdb24c4b61 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/9973 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/9973 for details. -gerrit

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Patch merged into coreboot/master: a52f903 src/mainboard/*/*/board_info.txt: Added Release year for boards
by gerrit＠coreboot.org 23 Apr '15

23 Apr '15

the following patch was just integrated into master: commit a52f9033dfd604e5c2c794ae30f2b684ba643fb9 Author: Mathias Friman <mathias(a)workplays.se> Date: Wed Apr 22 18:23:00 2015 +0200 src/mainboard/*/*/board_info.txt: Added Release year for boards To simplify browsing the "Supported hardware" list, I added Release year for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel, lenovo, apple, jetway and hp. Still several models and manufacturers to add information to. This is more of a proof-of-concept. The "Release year" will be shown in the wiki page. Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947 Signed-off-by: Mathias Friman <mathias(a)workplays.se> Reviewed-on: http://review.coreboot.org/9963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9963 for details. -gerrit

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New patch to review for coreboot: 7dab238 memlayout: Make sure preram_cbmem_console symbols exist
by Patrick Georgi 23 Apr '15

23 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9973 -gerrit commit 7dab23847b2a20e421ed44f89a40d6d53e4fdf01 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 23 14:40:22 2015 +0200 memlayout: Make sure preram_cbmem_console symbols exist This enables its _size variable (a macro) to work even when the console has no location assigned to it in the chip/board's memlayout.ld. Since _size == 0, the code will do the right thing. Change-Id: I6b42ed0c5c3aaa613603680728b61cbdb24c4b61 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/lib/bootblock.ld | 2 ++ src/lib/romstage.ld | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld index 9bd8a86..8c93342 100644 --- a/src/lib/bootblock.ld +++ b/src/lib/bootblock.ld @@ -35,6 +35,8 @@ *(.bss.*); *(.sbss); *(.sbss.*); + _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; + _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; _ebootblock = .; _eprogram = .; } : to_load = 0xff diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld index c3a2643..1e80962 100644 --- a/src/lib/romstage.ld +++ b/src/lib/romstage.ld @@ -33,6 +33,8 @@ *(.rodata.*); *(.data); *(.data.*); + _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; + _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; . = ALIGN(8); }

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Patch set updated for coreboot: 5642ec0 ramstage: don't drop cbmem console
by Patrick Georgi 23 Apr '15

23 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9933 -gerrit commit 5642ec084449e2e76b69ad29c7fcefb6cc2b7162 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Apr 21 11:57:18 2015 -0500 ramstage: don't drop cbmem console In commit b0d8f5e9 I moved the call to cbmem_initialize() in the CONFIG_EARLY_CBMEM_INIT case to the very beginning of ramstage. However, that caused an issue in the ordering of the cbmem console driver in that it expects cbmemc_init() to be called prior to cbmemc_reinit(). Therefore, ensure console is called as the first thing even if some time is lost w.r.t. timestamp tracking. Change-Id: I42137d28116e0bccb9235f4e3f394d4fd8b84e37 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/hardwaremain.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 3d1b8f2..295edcd 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -434,6 +434,12 @@ static void boot_state_schedule_static_entries(void) void main(void) { + /* console_init() MUST PRECEDE ALL printk()! Additionally, ensure + * it is the very first thing done in ramstage.*/ + console_init(); + + post_code(POST_CONSOLE_READY); + /* * CBMEM needs to be recovered in the EARLY_CBMEM_INIT case because * timestamps, APCI, etc rely on the cbmem infrastructure being @@ -448,11 +454,6 @@ void main(void) timestamp_add_now(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); - /* console_init() MUST PRECEDE ALL printk()! */ - console_init(); - - post_code(POST_CONSOLE_READY); - /* Handoff sleep type from romstage. */ #if CONFIG_HAVE_ACPI_RESUME acpi_is_wakeup();

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Patch set updated for coreboot: b068a21 cbmem_console: fix it for x86
by Patrick Georgi 23 Apr '15

23 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9851 -gerrit commit b068a2187de0d01d5331552025c6b0efb4f814cc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Apr 20 15:24:19 2015 -0500 cbmem_console: fix it for x86 The Kconfig options pertaining cbmem console in the preram environment no longer make sense with the linker script changes. Remove them and their usage within cbmem_console. Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/console/Kconfig | 5 ----- src/cpu/amd/model_10xxx/Kconfig | 5 ----- src/include/console/cbmem_console.h | 4 ++-- src/lib/cbmem_console.c | 34 ++++++++++++++++++++++------------ 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 09cfb39..2807039 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -184,11 +184,6 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. -config CONSOLE_PRERAM_BUFFER_BASE - hex - default 0xabadbeef if !CACHE_AS_RAM || LATE_CBMEM_INIT - default 0x0 - endif config CONSOLE_QEMU_DEBUGCON diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index a0d5cb4..cd69cae 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -72,9 +72,4 @@ config UDELAY_LAPIC_FIXED_FSB int default 200 -config CONSOLE_PRERAM_BUFFER_SIZE - hex - default 0x0 if CONSOLE_PRERAM_BUFFER_BASE = 0xabadbeef - default 0x8000 - endif # CPU_AMD_MODEL_10XXX diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 81bc10f..3431459 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -32,8 +32,8 @@ static inline void cbmemc_reinit(void) {} #endif #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ - (ENV_RAMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE && \ - ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || ENV_ROMSTAGE))) + (ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) && \ + (ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE)))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 770c1d2..628d3b9 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -83,7 +83,7 @@ static inline void init_console_ptr(void *storage, u32 total_space, int flags) { struct cbmem_console *cbm_cons_p = storage; - if (!cbm_cons_p) { + if (!cbm_cons_p || total_space == 0) { current_console_set(NULL); return; } @@ -209,22 +209,32 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, void cbmemc_reinit(void) { - struct cbmem_console *cbm_cons_p = NULL; + struct cbmem_console *cbm_cons_p; + const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; int flags = CBMEMC_APPEND; - if (ENV_ROMSTAGE && (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) - return; - - /* If CBMEM entry already existed, old contents is not altered. */ - cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, - CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); + /* No appending when no preram console available and adding for + * the first time. */ + if (!ENV_RAMSTAGE && _preram_cbmem_console_size == 0) + flags = CBMEMC_RESET; - /* Clear old contents of CBMEM buffer. */ - if (ENV_ROMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) + /* Need to reset the newly added cbmem console in romstage. */ + if (ENV_ROMSTAGE) flags |= CBMEMC_RESET; - init_console_ptr(cbm_cons_p, - CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); + /* Need to reset the newly added cbmem console in ramstage + * when there was no console in preram environment. */ + if (ENV_RAMSTAGE) { + cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); + if (cbm_cons_p == NULL) + flags |= CBMEMC_RESET; + } + + /* If CBMEM entry already existed, old contents is not altered. */ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size); + + init_console_ptr(cbm_cons_p, size, flags); } + /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit)

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Patch set updated for coreboot: 1a83185 i945/raminit.c: fix write Cache Control for 82945G/GZ/P/PL
by HAOUAS Elyes 23 Apr '15

23 Apr '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9971 -gerrit commit 1a8318501250a01849a631a696ee6b8a98e4bef6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Apr 23 12:10:17 2015 +0200 i945/raminit.c: fix write Cache Control for 82945G/GZ/P/PL Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index bd6e0c9..f18780c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2326,8 +2326,14 @@ static void sdram_pre_jedec_initialization(void) u32 reg32; reg32 = MCHBAR32(WCC); - reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) + { + reg32 &= 0xf3fff7ff; + reg32 |= (1 << 25) | (3 << 22) | (1 << 10); + } else { + reg32 &= 0x113ff3ff; + reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + } MCHBAR32(WCC) = reg32; MCHBAR32(SMVREFC) |= (1 << 6);

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New patch to review for coreboot: 43b7794 intel: Correct several MMIO related ACPI table settings
by Dave Frodin 23 Apr '15

23 Apr '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9972 -gerrit commit 43b7794f8ba69866d03abd9aff5fbe522c3625a6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Apr 23 06:04:46 2015 -0600 intel: Correct several MMIO related ACPI table settings 1) The rangeley chipset has the MMIO PCI config space feature enabled at 0xe0000000-0xefffffff. This is a 256MB space which covers all of config space. The ACPI table for this space only defines it as being 64MB. This table setting has been corrected in the rangeley.asl file. 2) Several of the intel platforms define the region reserved for PCI memory resources in a location where it overlaps with the MMIO (MCFG) region. Using the memory map from mohon_peak as an example: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007fbcffff: RAM 4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES 5. 000000007fc00000-000000007fdfffff: RESERVED 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000fee00000-00000000fee00fff: RESERVED 8. 0000000100000000-000000017fffffff: RAM The ACPI table describing the space set aside for PCI memory (not to be confused with the MMIO config space) is defined as the region from BMBOUND (the top of DRAM below 4GB) to a hardcode value of 0xfebfffff. That region would overlap the MMIO region at 0xe0000000-0xefffffff. For rangeley the upper bound of the PCI memory space should be set to 0xe0000000 - 1. The MCFG regions for several of the affected chipsets are: rangeley 0xe0000000-0xefffffff baytrail 0xe0000000-0xefffffff haswell 0xf0000000-0xf3ffffff sandybridge 0xf8000000-0xfbffffff Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl | 8 ++++---- src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl | 2 +- src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 +++--- src/northbridge/intel/sandybridge/acpi/hostbridge.asl | 6 +++--- src/soc/intel/baytrail/acpi/southcluster.asl | 6 +++--- src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 6 +++--- 6 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl index 5cefaeb..4159c30 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl @@ -111,11 +111,11 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) + // PCI Memory Region (Top of memory-0xdfffffff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xe0000000,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, @@ -131,7 +131,7 @@ Method (_CRS, 0, Serialized) // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (BMBD, PMIN) // Memory goes from BMBOUND to 0xfebfffff (PM01 above) + Store (BMBD, PMIN) // Memory goes from BMBOUND to 0xdfffffff (PM01 above) Add(Subtract(PMAX, PMIN), 1, PLEN) // Store Memory Size Return (MCRS) diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl index 6a8c2e0..08dba89 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl +++ b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl @@ -30,7 +30,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000) + Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000) }) // Current Resource Settings diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9bc5549..eb5aa76 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -426,11 +426,11 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) + // PCI Memory Region (Top of memory-0xefffffff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + 0x00000000, 0x00000000, 0xefffffff, 0x00000000, + 0xf0000000,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 26f7514..aba832c 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -344,11 +344,11 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) + // PCI Memory Region (Top of memory-0xf7ffffff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + 0x00000000, 0x00000000, 0xf7ffffff, 0x00000000, + 0xf8000000,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 47151a3..1385bd5 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -158,11 +158,11 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfeafffff) + // PCI Memory Region (Top of memory-0xdfffffff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, - 0x00100000,,, PMEM) + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xe0000000,,, PMEM) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl index 3ee9ee0..12e9daa 100644 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -157,11 +157,11 @@ Name (MCRS, ResourceTemplate() 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfeafffff) + // PCI Memory Region (Top of memory-0xdfffffff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, - 0x00100000,,, PMEM) + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xe0000000,,, PMEM) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,

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New patch to review for coreboot: 6e975d0 i945/raminit.c: fix write Cache Control
by HAOUAS Elyes 23 Apr '15

23 Apr '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9971 -gerrit commit 6e975d043b6032a29cf09bb9aa18b3f15f8891a2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Apr 23 12:10:17 2015 +0200 i945/raminit.c: fix write Cache Control Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index bd6e0c9..0f1741a 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2326,8 +2326,8 @@ static void sdram_pre_jedec_initialization(void) u32 reg32; reg32 = MCHBAR32(WCC); - reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + reg32 &= 0xf3fff7ff; + reg32 |= (1 << 25) | (3 << 22) | (1 << 10); MCHBAR32(WCC) = reg32; MCHBAR32(SMVREFC) |= (1 << 6);

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coreboot-gerrit April 2015