coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 933790f resource: Adjust memory resources high earlier
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8890 -gerrit commit 933790f650a7bb1a6096eda0592d5b571f1a3505 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 23 14:22:22 2015 +0200 resource: Adjust memory resources high earlier Do this to avoid reporting incorrect resource window in the logs. Change-Id: Icb7978deeb54f0ec6c29473ce9034fe44b6d7602 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 8cc5527..35bb6e2 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -746,6 +746,10 @@ static void avoid_fixed_resources(struct device *dev) if (res->limit > lim->limit) res->limit = lim->limit; + /* MEM resources need to start at the highest address manageable. */ + if (res->flags & IORESOURCE_MEM) + res->base = resource_max(res); + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); } @@ -1057,21 +1061,6 @@ void dev_configure(void) if (child->path.type == DEVICE_PATH_DOMAIN) avoid_fixed_resources(child); - /* - * Now we need to adjust the resources. MEM resources need to start at - * the highest address manageable. - */ - for (child = root->link_list->children; child; child = child->sibling) { - if (child->path.type != DEVICE_PATH_DOMAIN) - continue; - for (res = child->resource_list; res; res = res->next) { - if (!(res->flags & IORESOURCE_MEM) || - res->flags & IORESOURCE_FIXED) - continue; - res->base = resource_max(res); - } - } - /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); for (child = root->link_list->children; child; child = child->sibling) {

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Patch set updated for coreboot: c609dd6 resource: Enhance resource reporting
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8889 -gerrit commit c609dd6c30c483f79235cb05263b592dd0f635e3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 23 19:37:38 2015 +0200 resource: Enhance resource reporting Remove some redundancy in both source code and console output. Change-Id: I32350966de7af30b3ca4ac747fe3bf623ea9484b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 70 ++++++++++++++++++++++++++--------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 117bd18..8cc5527 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -191,6 +191,17 @@ static resource_t round(resource_t val, unsigned long pow) return val; } +static const char * resource2str(struct resource *res) +{ + if (res->flags & IORESOURCE_IO) + return "io"; + if (res->flags & IORESOURCE_PREFETCH) + return "prefmem"; + if (res->flags & IORESOURCE_MEM) + return "mem"; + return "undefined"; +} + /** * Read the resources on all devices of a given bus. * @@ -325,10 +336,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, resource_t base; base = round(bridge->base, bridge->align); - printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", base, bridge->size, bridge->align, + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" + " limit: %llx\n", dev_path(bus->dev), resource2str(bridge), + base, bridge->size, bridge->align, bridge->gran, bridge->limit); /* For each child which is a bridge, compute the resource needs. */ @@ -430,9 +440,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", dev_path(dev), resource->index, resource->base, resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO) ? "io" : - (resource->flags & IORESOURCE_PREFETCH) ? - "prefmem" : "mem"); + resource2str(resource)); } /* @@ -444,10 +452,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, bridge->size = round(base, bridge->gran) - round(bridge->base, bridge->align); - printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx done\n", dev_path(bus->dev), __func__, - (bridge->flags & IORESOURCE_IO) ? "io" : - (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", + printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" + " limit: %llx done\n", dev_path(bus->dev), + resource2str(bridge), base, bridge->size, bridge->align, bridge->gran, bridge->limit); } @@ -473,10 +480,9 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, resource_t base; base = bridge->base; - printk(BIOS_SPEW, "%s %s_%s: base:%llx size:%llx align:%d gran:%d " - "limit:%llx\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", + printk(BIOS_SPEW, "%s %s: base:%llx size:%llx align:%d gran:%d " + "limit:%llx\n", dev_path(bus->dev), + resource2str(bridge), base, bridge->size, bridge->align, bridge->gran, bridge->limit); /* Remember we haven't found anything yet. */ @@ -542,18 +548,13 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, ? "Assigned: " : "", dev_path(dev), resource->index, resource->base, resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO) ? "io" - : (resource->flags & IORESOURCE_PREFETCH) - ? "prefmem" : "mem"); + resource2str(resource)); } - printk(BIOS_SPEW, "%s%s %02lx * [0x%llx - 0x%llx] %s\n", - (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: " - : "", dev_path(dev), resource->index, resource->base, + printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(dev), resource->index, resource->base, resource->size ? resource->base + resource->size - 1 : - resource->base, (resource->flags & IORESOURCE_IO) - ? "io" : (resource->flags & IORESOURCE_PREFETCH) - ? "prefmem" : "mem"); + resource->base, resource2str(resource)); } /* @@ -565,10 +566,9 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, bridge->flags |= IORESOURCE_ASSIGNED; - printk(BIOS_SPEW, "%s %s_%s: next_base: %llx size: %llx align: %d " - "gran: %d done\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", base, bridge->size, bridge->align, + printk(BIOS_SPEW, "%s %s: next_base: %llx size: %llx align: %d " + "gran: %d done\n", dev_path(bus->dev), + resource2str(bridge), base, bridge->size, bridge->align, bridge->gran); /* For each child which is a bridge, allocate_resources. */ @@ -633,8 +633,6 @@ static void constrain_resources(struct device *dev, struct constraints* limits) struct resource *lim; struct bus *link; - printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); - /* Constrain limits based on the fixed resources of this device. */ for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_FIXED)) @@ -665,6 +663,10 @@ static void constrain_resources(struct device *dev, struct constraints* limits) || (res->base > lim->limit)) continue; + printk(BIOS_SPEW, "%s: %s %02lx base %08llx limit %08llx %s (fixed)\n", + __func__, dev_path(dev), res->index, res->base, + res->base + res->size - 1, resource2str(res)); + /* * Choose to be above or below fixed resources. This check is * signed so that "negative" amounts of space are handled @@ -738,16 +740,14 @@ static void avoid_fixed_resources(struct device *dev) else continue; - printk(BIOS_SPEW, "%s2: %s@%02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); - printk(BIOS_SPEW, "\tlim->base %08llx lim->limit %08llx\n", - lim->base, lim->limit); - /* Is the resource outside the limits? */ if (lim->base > res->base) res->base = lim->base; if (res->limit > lim->limit) res->limit = lim->limit; + + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", + __func__, dev_path(dev), res->index, res->base, res->limit); } }

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Patch set updated for coreboot: cf19421 resource: Report correct secondary resource window
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8888 -gerrit commit cf19421288b7eb3492ea46e65a2360e30b450827 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 23 19:58:23 2015 +0200 resource: Report correct secondary resource window Once a bridge window resource is allocated, it becomes the base and limit for any resource on the secondary bus. Upper limit was incorrectly reported in the log while assigning secondary resources. Change-Id: I69f0a02aae6d13f77aaa2dace924b8970b23edad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/device/device.c b/src/device/device.c index b3b8d24..117bd18 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -525,6 +525,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, /* Base must be aligned. */ base = round(base, resource->align); resource->base = base; + resource->limit = resource->base + resource->size - 1; resource->flags |= IORESOURCE_ASSIGNED; resource->flags &= ~IORESOURCE_STORED; base += resource->size;

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Patch set updated for coreboot: a6bbd5f resource: Add prefetchable memory resource for PCI domain
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8892 -gerrit commit a6bbd5f2e422816e6d740b34e6d336ac07dc0308 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 26 23:27:54 2015 +0200 resource: Add prefetchable memory resource for PCI domain With the change, prefetchable and non-prefetchable MMIO resources will no longer be interleaved for the domain, but one window will appear below the other in memory space. There is no need to negotiate the resource limits via intermediate limits structure. Recursively walk the devicetree for each type of resource and apply the constraints directly on the domain path. Change-ID: Ibf44deab0aed0a05759e78855e23146fc45cdc43 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 169 +++++++++++++----------------------------------- src/device/pci_device.c | 6 ++ 2 files changed, 50 insertions(+), 125 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 72f2373..51cd4c6 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -278,10 +278,11 @@ static void pick_largest_resource(void *gp, struct device *dev, static struct device *largest_resource(struct bus *bus, struct resource **result_res, - unsigned long type_mask, - unsigned long type) + struct resource *bridge) { struct pick_largest_state state; + u32 type_mask = (IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH); + u32 type = bridge->flags & type_mask; state.last = *result_res; state.result_dev = NULL; @@ -295,6 +296,20 @@ static struct device *largest_resource(struct bus *bus, return state.result_dev; } +static int resource_match(struct resource *res, struct resource *lim) +{ + return (res->flags & IORESOURCE_TYPE_MASK) == + (lim->flags & IORESOURCE_TYPE_MASK); +} + +static int resource_match_bridge(struct resource *res, struct resource *win) +{ + u32 type_mask = (IORESOURCE_TYPE_MASK | IORESOURCE_PREFETCH); + if (!(res->flags & IORESOURCE_BRIDGE)) + return 0; + return (res->flags & type_mask) == (win->flags & type_mask); +} + /** * This function is the guts of the resource allocator. * @@ -324,12 +339,8 @@ static struct device *largest_resource(struct bus *bus, * * @param bus The bus we are traversing. * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. - * @return TODO */ -static void compute_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) +static void compute_resources(struct bus *bus, struct resource *bridge) { struct device *dev; struct resource *resource; @@ -353,17 +364,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, child_bridge = child_bridge->next) { struct bus* link; - if (!(child_bridge->flags & IORESOURCE_BRIDGE) - || (child_bridge->flags & type_mask) != type) + if (!resource_match_bridge(child_bridge, bridge)) continue; - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ link = dev->link_list; while (link && link->link_num != IOINDEX_LINK(child_bridge->index)) @@ -375,10 +378,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, dev_path(dev)); } - compute_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); + compute_resources(link, child_bridge); } } @@ -390,7 +390,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * amount of address space taken by them. Take granularity and * alignment into account. */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { + while ((dev = largest_resource(bus, &resource, bridge))) { /* Size 0 resources can be skipped. */ if (!resource->size) @@ -467,13 +467,10 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * * @param bus The bus we are traversing. * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets ANDed with the resource type. - * @param type This value must match the result of the AND. * * @see compute_resources */ -static void allocate_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) +static void allocate_resources(struct bus *bus, struct resource *bridge) { struct device *dev; struct resource *resource; @@ -492,7 +489,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, * Walk through all the resources on the current bus and allocate them * address space. */ - while ((dev = largest_resource(bus, &resource, type_mask, type))) { + while ((dev = largest_resource(bus, &resource, bridge))) { /* Propagate the bridge limit to the resource register. */ if (resource->limit > bridge->limit) @@ -583,17 +580,9 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, child_bridge = child_bridge->next) { struct bus* link; - if (!(child_bridge->flags & IORESOURCE_BRIDGE) || - (child_bridge->flags & type_mask) != type) + if (!resource_match_bridge(child_bridge, bridge)) continue; - /* - * Split prefetchable memory if combined. Many domains - * use the same address space for prefetchable memory - * and non-prefetchable memory. Bridges below them need - * it separated. Add the PREFETCH flag to the type_mask - * and type. - */ link = dev->link_list; while (link && link->link_num != IOINDEX_LINK(child_bridge->index)) @@ -603,47 +592,25 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, IOINDEX_LINK(child_bridge->index), dev_path(dev)); - allocate_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); + allocate_resources(link, child_bridge); } } } -static int resource_is(struct resource *res, u32 type) -{ - return (res->flags & IORESOURCE_TYPE_MASK) == type; -} - -struct constraints { - struct resource io, mem; -}; - -static struct resource * resource_limit(struct constraints *limits, struct resource *res) -{ - struct resource *lim = NULL; - - /* MEM, or I/O - skip any others. */ - if (resource_is(res, IORESOURCE_MEM)) - lim = &limits->mem; - else if (resource_is(res, IORESOURCE_IO)) - lim = &limits->io; - - return lim; -} - -static void constrain_resources(struct device *dev, struct constraints* limits) +static void constrain_resources(struct device *dev, struct resource *lim) { struct device *child; struct resource *res; - struct resource *lim; struct bus *link; /* Constrain limits based on the fixed resources of this device. */ for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_FIXED)) continue; + + if (!resource_match(res, lim)) + continue; + if (!res->size) { /* It makes no sense to have 0-sized, fixed resources.*/ printk(BIOS_ERR, "skipping %s@%lx fixed resource, " @@ -651,10 +618,6 @@ static void constrain_resources(struct device *dev, struct constraints* limits) continue; } - lim = resource_limit(limits, res); - if (!lim) - continue; - /* * Is it a fixed resource outside the current known region? * If so, we don't have to consider it - it will be handled @@ -684,63 +647,35 @@ static void constrain_resources(struct device *dev, struct constraints* limits) for (link = dev->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { if (child->enabled) - constrain_resources(child, limits); + constrain_resources(child, lim); } } } static void avoid_fixed_resources(struct device *dev) { - struct constraints limits; struct resource *res; - struct resource *lim; + resource_t mem_limit = 0xffffffffULL; printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); - /* Initialize constraints to maximum size. */ - limits.io.base = 0; - limits.io.limit = 0xffffffffffffffffULL; - limits.mem.base = 0; - limits.mem.limit = 0xffffffffffffffffULL; - /* Constrain the limits to dev's initial resources. */ for (res = dev->resource_list; res; res = res->next) { if ((res->flags & IORESOURCE_FIXED)) continue; - printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); - - lim = resource_limit(&limits, res); - if (!lim) - continue; - - if (res->base > lim->base) - lim->base = res->base; - if (res->limit < lim->limit) - lim->limit = res->limit; - } - - /* Look through the tree for fixed resources and update the limits. */ - constrain_resources(dev, &limits); - - /* Update dev's resources with new limits. */ - for (res = dev->resource_list; res; res = res->next) { - if ((res->flags & IORESOURCE_FIXED)) - continue; - lim = resource_limit(&limits, res); - if (!lim) - continue; + /* Place MEM resources one after other. */ + if ((res->flags & IORESOURCE_MEM) && (res->limit > mem_limit)) + res->limit = mem_limit; - /* Is the resource outside the limits? */ - if (lim->base > res->base) - res->base = lim->base; - if (res->limit > lim->limit) - res->limit = lim->limit; + /* Look through the tree for fixed resources and update the limits. */ + constrain_resources(dev, res); /* MEM resources need to start at the highest address manageable. */ - if (res->flags & IORESOURCE_MEM) + if (res->flags & IORESOURCE_MEM) { res->base = resource_max(res); + mem_limit = res->base - 1; + } printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); @@ -1030,16 +965,8 @@ void dev_configure(void) for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } + + compute_resources(child->link_list, res); } } @@ -1057,16 +984,8 @@ void dev_configure(void) for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; - if (res->flags & IORESOURCE_MEM) { - allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - allocate_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); - continue; - } + + allocate_resources(child->link_list, res); } } assign_resources(root->link_list); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4651258..c8e6692 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -447,6 +447,12 @@ void pci_domain_read_resources(struct device *dev) res->limit = 0xffffffffULL; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0)); + res->limit = 0xffffffffULL; + res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; } static void pci_set_resource(struct device *dev, struct resource *resource)

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New patch to review for coreboot: 4906706 nvidia/cbootimage: update to 1.5
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9982 -gerrit commit 490670673505e9ab1d532bf2c534a2f4fc3eb020 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Apr 24 10:52:52 2015 +0200 nvidia/cbootimage: update to 1.5 Change-Id: I16e7c376fe6d79676734df325ac61449bb2d0871 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/nvidia/Makefile.inc | 6 +++++- util/nvidia/cbootimage | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/util/nvidia/Makefile.inc b/util/nvidia/Makefile.inc index 91c8a94..133778f 100644 --- a/util/nvidia/Makefile.inc +++ b/util/nvidia/Makefile.inc @@ -7,11 +7,13 @@ CBOOTIMAGE_RAW_SRCS:= \ aes_ref.c \ context.c \ parse.c \ + t210/parse_t210.c \ t132/parse_t132.c \ t124/parse_t124.c \ t114/parse_t114.c \ t30/parse_t30.c \ t20/parse_t20.c \ + t210/nvbctlib_t210.c \ t132/nvbctlib_t132.c \ t124/nvbctlib_t124.c \ t114/nvbctlib_t114.c \ @@ -33,7 +35,9 @@ CBOOTIMAGE_RAW_SRCS:= \ t124/nvboot_bct_t124.h \ t124/nvboot_sdram_param_t124.h \ t132/nvboot_bct_t132.h \ - t132/nvboot_sdram_param_t132.h + t132/nvboot_sdram_param_t132.h \ + t210/nvboot_bct_t210.h \ + t210/nvboot_sdram_param_t210.h CBOOTIMAGE_SRCS:=$(addprefix util/nvidia/cbootimage/src/,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS))) CBOOTIMAGE_OBJS:=$(addprefix $(objutil)/nvidia/cbootimage/,$(patsubst %.c,%.o,$(filter %.c,$(CBOOTIMAGE_RAW_SRCS)))) diff --git a/util/nvidia/cbootimage b/util/nvidia/cbootimage index 2eb9a86..b7d5b2d 160000 --- a/util/nvidia/cbootimage +++ b/util/nvidia/cbootimage @@ -1 +1 @@ -Subproject commit 2eb9a86724db0d86c9ab9b6aeca21d1000d74e78 +Subproject commit b7d5b2d6a6dd05874d86ee900ff441d261f9034c

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New patch to review for coreboot: 89aa1cf arm64: save/restore cptr_el3 and cpacr_el1 registers
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9981 -gerrit commit 89aa1cf73ae0f3192b9bc92446122fb466604ddd Author: Joseph Lo <josephl(a)nvidia.com> Date: Fri Apr 17 15:31:59 2015 +0800 arm64: save/restore cptr_el3 and cpacr_el1 registers CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level and access right of the FPU/SIMD instructions. Need to save/restore them in every power cycle to keep the settings consistent. BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057 Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266073 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> --- src/arch/arm64/include/arch/startup.h | 4 +++- src/arch/arm64/include/armv8/arch/lib_helpers.h | 10 ++++++++++ src/arch/arm64/stage_entry.S | 6 ++++++ src/arch/arm64/startup.c | 5 ++++- 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/include/arch/startup.h b/src/arch/arm64/include/arch/startup.h index 671c13e..6e55190 100644 --- a/src/arch/arm64/include/arch/startup.h +++ b/src/arch/arm64/include/arch/startup.h @@ -30,8 +30,10 @@ #define SCR_INDEX 3 #define VBAR_INDEX 4 #define CNTFRQ_INDEX 5 +#define CPTR_INDEX 6 +#define CPACR_INDEX 7 /* IMPORTANT!!! If any new element is added please update NUM_ELEMENTS */ -#define NUM_ELEMENTS 6 +#define NUM_ELEMENTS 8 #ifndef __ASSEMBLY__ diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index bb7300f..315a0c0 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -261,6 +261,16 @@ 402: .endm +/* Macro to read from an el1 register */ +.macro read_el1 xreg sysreg + mrs \xreg, \sysreg\()_el1 +.endm + +/* Macro to write to an el1 register */ +.macro write_el1 sysreg xreg temp + msr \sysreg\()_el1, \xreg +.endm + /* Macro to read from an el0 register */ .macro read_el0 xreg sysreg mrs \xreg, \sysreg\()_el0 diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index cfe8edd..b7dc1b5 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -193,6 +193,12 @@ ENDPROC(__rmodule_entry) get_element_addr CNTFRQ_INDEX write_el0 cntfrq, x0, x1 + get_element_addr CPTR_INDEX + write_el3 cptr, x0, x1 + + get_element_addr CPACR_INDEX + write_el1 cpacr, x0, x1 + dsb sy isb diff --git a/src/arch/arm64/startup.c b/src/arch/arm64/startup.c index 6a85940..ba480bc 100644 --- a/src/arch/arm64/startup.c +++ b/src/arch/arm64/startup.c @@ -46,9 +46,12 @@ void startup_save_cpu_data(void) save_element(TTBR0_INDEX, raw_read_ttbr0_current()); save_element(VBAR_INDEX, raw_read_vbar_current()); save_element(CNTFRQ_INDEX, raw_read_cntfrq_el0()); + save_element(CPACR_INDEX, raw_read_cpacr_el1()); - if (get_current_el() == EL3) + if (get_current_el() == EL3) { save_element(SCR_INDEX, raw_read_scr_el3()); + save_element(CPTR_INDEX, raw_read_cptr_el3()); + } dcache_clean_by_mva(_arm64_startup_data, NUM_ELEMENTS * PER_ELEMENT_SIZE_BYTES);

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New patch to review for coreboot: 0f47a53 arm64: implement CPU power down sequence as per A57/A53/A72 TRM
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9980 -gerrit commit 0f47a53b543ca595c33d45762315c683f1eefe06 Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Apr 15 10:09:50 2015 +0800 arm64: implement CPU power down sequence as per A57/A53/A72 TRM Implement the individual core powerdown sequence as per Cortex-A57/A53/A72 TRM. Based-on-the-work-by: Varun Wadekar <vwadekar(a)nvidia.com> BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74 Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265827 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/cpu-stubs.c | 6 +++ src/arch/arm64/cpu/Kconfig | 5 ++ src/arch/arm64/cpu/cortex_a57.S | 95 +++++++++++++++++++++++++++++++++ src/arch/arm64/cpu/cortex_a57.h | 6 +++ src/arch/arm64/include/armv8/arch/cpu.h | 14 +++++ 5 files changed, 126 insertions(+) diff --git a/src/arch/arm64/cpu-stubs.c b/src/arch/arm64/cpu-stubs.c index c7b083e..da76759 100644 --- a/src/arch/arm64/cpu-stubs.c +++ b/src/arch/arm64/cpu-stubs.c @@ -18,8 +18,14 @@ */ void arm64_cpu_early_setup(void); +void cortex_a57_cpu_power_down(int l2_flush); void __attribute__((weak)) arm64_cpu_early_setup(void) { /* Default empty implementation */ } + +void __attribute__((weak)) cortex_a57_cpu_power_down(int l2_flush) +{ + /* Default empty implementation */ +} diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig index fadd48a..20304be 100644 --- a/src/arch/arm64/cpu/Kconfig +++ b/src/arch/arm64/cpu/Kconfig @@ -21,3 +21,8 @@ config ARCH_ARM64_CPU_CORTEX_A57 bool default n depends on ARCH_ARM64 + +config ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT + bool + default n + depends on ARCH_ARM64 && ARCH_ARM64_CPU_CORTEX_A57 diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S index 5039d1c..ae05175 100644 --- a/src/arch/arm64/cpu/cortex_a57.S +++ b/src/arch/arm64/cpu/cortex_a57.S @@ -18,6 +18,7 @@ */ #include <arch/asm.h> +#include <arch/cache_helpers.h> #include "cortex_a57.h" ENTRY(arm64_cpu_early_setup) @@ -27,3 +28,97 @@ ENTRY(arm64_cpu_early_setup) isb ret ENDPROC(arm64_cpu_early_setup) + +/* + * CPU power down sequence as per A57/A53/A72 TRM + * + * x0 - L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported + * + */ +#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) +ENTRY(cortex_a57_cpu_power_down) + /* Store L2 cache flush request */ + mov x13, x0 + + /* 1. Stop allocations to our data cache */ + mrs x0, sctlr_el1 + bic x0, x0, #1 << 2 // clear SCTLR.C + msr sctlr_el1, x0 + isb + + mrs x0, sctlr_el3 + bic x0, x0, #1 << 2 // clear SCTLR.C + msr sctlr_el3, x0 + isb + + mrs x0, midr_el1 + ubfx x0, x0, #4, #12 + cmp x0, #CORTEX_A53_PN + b.eq a53 + + /* 2. Disable L2 prefetch */ + mrs x0, CPUECTLR_EL1 // CPUECTLR_EL1 + /* CPUECTLR[38], disable table walk descriptor access L2 prefetch */ + orr x0, x0, #1 << 38 + /* + * CPUECTLR[36:35] L2 instruction fetch prefetch distance + * 0 => disable instruction prefetch + */ + bic x0, x0, #3 << 35 + /* + * CPUECTLR[33:32] L2 load/store prefetch distance + * 0 => disable instruction prefetch + */ + bic x0, x0, #3 << 32 + msr CPUECTLR_EL1, x0 + + /* 3. ISB to ensure ectlr write is complete */ + isb + + /* 4. DSB to ensure prior prefetches are complete */ + dsb sy + +a53: + /* 5. Clean and invalidate L1 and L2 if X13 == 1 */ + mov x0, #DCCISW + cmp x13, #1 + bne 1f + bl flush_dcache_all + b 2f +1: + bl flush_dcache_louis +2: + + /* 6. Leave coherency, clear SMPEN */ + mrs x0, CPUECTLR_EL1 + bic x0, x0, #(1 << SMPEN_SHIFT) + msr CPUECTLR_EL1, x0 + + /* 7. Set the DBGOSDLR.DLK, Double lock control bit */ + mrs x0, osdlr_el1 + orr x0, x0, #OSDLR_DBL_LOCK_BIT + msr osdlr_el1, x0 + + /* + * 9. Execute an ISB instruction to ensure that all of the + * System register changes from the previous steps have + * been committed. + */ + isb + + /* + * 10. Execute a DSB instruction to ensure that all + * instruction cache, TLB, and branch predictor + * maintenance operations issued by any processor in the + * multiprocessor before the SMPEN bit was cleared have + * completed. + */ + dsb sy + + /* 11. wfi */ +3: wfi + + /* we never return here */ + b 3b +ENDPROC(cortex_a57_cpu_power_down) +#endif diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/cpu/cortex_a57.h index 9e66f4d..9e12e8b 100644 --- a/src/arch/arm64/cpu/cortex_a57.h +++ b/src/arch/arm64/cpu/cortex_a57.h @@ -23,4 +23,10 @@ #define CPUECTLR_EL1 S3_1_c15_c2_1 #define SMPEN_SHIFT 6 +/* Cortex MIDR[15:4] PN */ +#define CORTEX_A53_PN 0xd03 + +/* Double lock control bit */ +#define OSDLR_DBL_LOCK_BIT 1 + #endif /* __ARCH_ARM64_CORTEX_A57_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 14635e3..4e15209 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -187,4 +187,18 @@ void arm64_cpu_startup_resume(void); */ void arm64_arch_timer_init(void); +/* + * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM. + * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported. + */ +#define NO_L2_FLUSH 0 +#define L2_FLUSH_HW 0 +#define L2_FLUSH_SW 1 + +#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) +void cortex_a57_cpu_power_down(int l2_flush); +#else +static inline void cortex_a57_cpu_power_down(int l2_flush) {} +#endif + #endif /* __ARCH_CPU_H__ */

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New patch to review for coreboot: 66604d8 arm64: introduce data cache ops by set/way to the level specified
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9979 -gerrit commit 66604d8217d39306d1801de4aa24dbe1ed37bb94 Author: Joseph Lo <josephl(a)nvidia.com> Date: Tue Apr 14 16:03:58 2015 +0800 arm64: introduce data cache ops by set/way to the level specified This patchs introduces level specific data cache maintenance operations to cache_helpers.S. It's derived form ARM trusted firmware repository. Please reference here. https://github.com/ARM-software/arm-trusted-firmware/blob/master/ lib/aarch64/cache_helpers.S BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82 Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265826 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/armv8/Makefile.inc | 4 + src/arch/arm64/armv8/cache.c | 5 +- src/arch/arm64/armv8/cache_helpers.S | 123 ++++++++++++++++++++++++++++ src/arch/arm64/armv8/cpu.S | 59 +------------ src/arch/arm64/armv8/secmon/Makefile.inc | 1 + src/arch/arm64/include/arch/cache_helpers.h | 47 +++++++++++ src/arch/arm64/include/armv8/arch/cache.h | 5 +- 7 files changed, 184 insertions(+), 60 deletions(-) diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 5532b47..d043921 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -37,6 +37,7 @@ bootblock-y += bootblock.S bootblock-y += bootblock_simple.c endif bootblock-y += cache.c +bootblock-y += cache_helpers.S bootblock-y += cpu.S bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c @@ -52,6 +53,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y) verstage-y += cache.c verstage-y += cpu.S +verstage-y += cache_helpers.S verstage-y += exception.c verstage-c-ccopts += $(armv8_flags) @@ -65,6 +67,7 @@ endif ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += cache.c +romstage-y += cache_helpers.S romstage-y += cpu.S romstage-y += exception.c @@ -82,6 +85,7 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += cache.c +ramstage-y += cache_helpers.S ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += mmu.c diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index d568f26..db9b388 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -34,6 +34,7 @@ #include <stdint.h> #include <arch/cache.h> +#include <arch/cache_helpers.h> #include <arch/lib_helpers.h> void tlb_invalidate_all(void) @@ -126,7 +127,7 @@ void dcache_mmu_disable(void) { uint32_t sctlr; - flush_dcache_all(); + flush_dcache_all(DCCISW); sctlr = raw_read_sctlr_current(); sctlr &= ~(SCTLR_C | SCTLR_M); raw_write_sctlr_current(sctlr); @@ -143,6 +144,6 @@ void dcache_mmu_enable(void) void cache_sync_instructions(void) { - flush_dcache_all(); /* includes trailing DSB (in assembly) */ + flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */ icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ } diff --git a/src/arch/arm64/armv8/cache_helpers.S b/src/arch/arm64/armv8/cache_helpers.S new file mode 100644 index 0000000..dc74dad --- /dev/null +++ b/src/arch/arm64/armv8/cache_helpers.S @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch/asm.h> +#include <arch/cache_helpers.h> + + /* --------------------------------------------------------------- + * Data cache operations by set/way to the level specified + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in cache_helpers.h + * x3: The last cache level to operate on + * x9: clidr_el1 + * and will carry out the operation on each data cache from level 0 + * to the level in x3 in sequence + * + * The dcsw_op macro sets up the x3 and x9 parameters based on + * clidr_el1 cache information before invoking the main function + * --------------------------------------------------------------- + */ + +.macro dcsw_op shift, fw, ls + mrs x9, clidr_el1 + ubfx x3, x9, \shift, \fw + lsl x3, x3, \ls + b do_dcsw_op +.endm + +do_dcsw_op: + cbz x3, exit + mov x10, xzr + adr x14, dcsw_loop_table // compute inner loop address + add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions + mov x0, x9 + mov w8, #1 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt level_done // nothing to do if no cache or icache + + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + ubfx x4, x1, #3, #10 // maximum way number + clz w5, w4 // bit position of way size increment + lsl w9, w4, w5 // w9 = aligned max way number + lsl w16, w8, w5 // w16 = way number loop decrement + orr w9, w10, w9 // w9 = combine way and cache number + ubfx w6, w1, #13, #15 // w6 = max set number + lsl w17, w8, w2 // w17 = set number loop decrement + dsb sy // barrier before we start this level + br x14 // jump to DC operation specific loop + +level_done: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 + msr csselr_el1, xzr // select cache level 0 in csselr + dsb sy // barrier to complete final cache operation + isb +exit: + ret + +.macro dcsw_loop _op +loop2_\_op: + lsl w7, w6, w2 // w7 = aligned max set number + +loop3_\_op: + orr w11, w9, w7 // combine cache, way and set number + dc \_op, x11 + subs w7, w7, w17 // decrement set number + b.ge loop3_\_op + + subs x9, x9, x16 // decrement way number + b.ge loop2_\_op + + b level_done +.endm + +dcsw_loop_table: + dcsw_loop isw + dcsw_loop cisw + dcsw_loop csw + +ENTRY(flush_dcache_louis) + dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +ENDPROC(flush_dcache_louis) + +ENTRY(flush_dcache_all) + dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +ENDPROC(flush_dcache_all) diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 1eecc2b..80e083e 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -19,63 +19,7 @@ */ #include <arch/asm.h> - -/* - * flush_dcache_all() - * - * Flush the whole D-cache. - * - * Corrupted registers: x0-x7, x9-x11 - * From: Linux arch/arm64/mm/cache.S - */ -ENTRY(flush_dcache_all) - dsb sy // ensure ordering with previous memory accesses - mrs x0, clidr_el1 // read clidr - and x3, x0, #0x7000000 // extract loc from clidr - lsr x3, x3, #23 // left align loc bit field - cbz x3, finished // if loc is 0, then no need to clean - mov x10, #0 // start clean at cache level 0 -loop1: - add x2, x10, x10, lsr #1 // work out 3x current cache level - lsr x1, x0, x2 // extract cache type bits from clidr - and x1, x1, #7 // mask of the bits for current cache only - cmp x1, #2 // see what cache we have at this level - b.lt skip // skip if no cache, or just i-cache - mrs x9, daif // make CSSELR and CCSIDR access atomic - msr csselr_el1, x10 // select current cache level in csselr - isb // isb to sych the new cssr&csidr - mrs x1, ccsidr_el1 // read the new ccsidr - msr daif, x9 - and x2, x1, #7 // extract the length of the cache lines - add x2, x2, #4 // add 4 (line length offset) - mov x4, #0x3ff - and x4, x4, x1, lsr #3 // find maximum number on the way size - clz x5, x4 // find bit position of way size increment - mov x7, #0x7fff - and x7, x7, x1, lsr #13 // extract max number of the index size -loop2: - mov x9, x4 // create working copy of max way size -loop3: - lsl x6, x9, x5 - orr x11, x10, x6 // factor way and cache number into x11 - lsl x6, x7, x2 - orr x11, x11, x6 // factor index number into x11 - dc cisw, x11 // clean & invalidate by set/way - subs x9, x9, #1 // decrement the way - b.ge loop3 - subs x7, x7, #1 // decrement the index - b.ge loop2 -skip: - add x10, x10, #2 // increment cache number - cmp x3, x10 - b.gt loop1 -finished: - mov x10, #0 // swith back to cache level 0 - msr csselr_el1, x10 // select current cache level in csselr - dsb sy - isb - ret -ENDPROC(flush_dcache_all) +#include <arch/cache_helpers.h> /* * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a @@ -92,6 +36,7 @@ ENTRY(arm_init_caches) /* FIXME: How to enable branch prediction on ARMv8? */ /* Flush and invalidate dcache */ + mov x0, #DCCISW bl flush_dcache_all /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc index ace00b4..11dcb9a 100644 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ b/src/arch/arm64/armv8/secmon/Makefile.inc @@ -35,6 +35,7 @@ secmon-y += psci.c secmon-y += smc.c secmon-y += trampoline.S secmon-y += ../cache.c +secmon-y += ../cache_helpers.S secmon-y += ../cpu.S secmon-y += ../exception.c secmon-y += ../../cpu.c diff --git a/src/arch/arm64/include/arch/cache_helpers.h b/src/arch/arm64/include/arch/cache_helpers.h new file mode 100644 index 0000000..2919d99 --- /dev/null +++ b/src/arch/arm64/include/arch/cache_helpers.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CACHE_HELPERS_H + +/* CLIDR definitions */ +#define LOUIS_SHIFT 21 +#define LOC_SHIFT 24 +#define CLIDR_FIELD_WIDTH 3 + +/* CSSELR definitions */ +#define LEVEL_SHIFT 1 + +/* D$ set/way op type defines */ +#define DCISW 0x0 +#define DCCISW 0x1 +#define DCCSW 0x2 + +#endif /* __CACHE_HELPERS_H */ diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 27fe8e0..5e2a4a1 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -69,7 +69,10 @@ void dcache_clean_invalidate_by_mva(void const *addr, size_t len); void dcache_invalidate_by_mva(void const *addr, size_t len); /* dcache invalidate all */ -void flush_dcache_all(void); +void flush_dcache_all(int op_type); + +/* flush the dcache up to the Level of Unification Inner Shareable */ +void flush_dcache_louis(int op_type); /* returns number of bytes per cache line */ unsigned int dcache_line_bytes(void);

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New patch to review for coreboot: 8972dfa arm64: perform early setup in secmon too
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9978 -gerrit commit 8972dfa351aaca2bbbbcab67889768ca4b321b18 Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Apr 15 14:30:55 2015 +0800 arm64: perform early setup in secmon too Same as commit fe0eac5f416e "arm64: Allow cpu specific early setup", we need the same in secmon too. BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: I5b1347880306a95f99233db12cb99547bad4aa8c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1f70fd940ff92eb5b8991cd777c2894b7a9633cf Original-Change-Id: Ifce5a6d636051e7a447d055c8e09ed4e29e091c7 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265825 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> --- src/arch/arm64/cpu/Makefile.inc | 1 + src/arch/arm64/stage_entry.S | 1 + 2 files changed, 2 insertions(+) diff --git a/src/arch/arm64/cpu/Makefile.inc b/src/arch/arm64/cpu/Makefile.inc index b4f39a5..47aa0d0 100644 --- a/src/arch/arm64/cpu/Makefile.inc +++ b/src/arch/arm64/cpu/Makefile.inc @@ -21,4 +21,5 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) ramstage-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S +secmon-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S endif diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 66e40fb..cfe8edd 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -216,6 +216,7 @@ ENDPROC(arm64_cpu_startup) CPU_RESET_ENTRY(arm64_cpu_startup_resume) split_bsp_path + bl arm64_cpu_early_setup setup_sctlr startup_restore b arm64_c_environment

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New patch to review for coreboot: 31b9af5 arm64: Allow cpu specific early setup
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9977 -gerrit commit 31b9af5798ecf858516611ecb4e0399e0fba2401 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Mar 27 22:55:59 2015 -0700 arm64: Allow cpu specific early setup Call arm64_cpu_early_setup to allow cpu-specific initialization to be performed. Also, add support for setting SMPEN bit for cortex a57 within arm64_cpu_early_setup. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and SMP works for foster Change-Id: Ifa4e6134dbce3ad63046b3dd9b947c3d9134d5e7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fe0eac5f416efcf9f7b05388a17444205a8352c0 Original-Change-Id: I28a05a20e6adf084cd0bf94bdd0c3b492632107c Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262993 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/Kconfig | 1 + src/arch/arm64/Makefile.inc | 6 +++++- src/arch/arm64/cpu-stubs.c | 25 +++++++++++++++++++++++++ src/arch/arm64/cpu/Kconfig | 23 +++++++++++++++++++++++ src/arch/arm64/cpu/Makefile.inc | 24 ++++++++++++++++++++++++ src/arch/arm64/cpu/cortex_a57.S | 29 +++++++++++++++++++++++++++++ src/arch/arm64/cpu/cortex_a57.h | 26 ++++++++++++++++++++++++++ src/arch/arm64/stage_entry.S | 1 + 8 files changed, 134 insertions(+), 1 deletion(-) diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 47e7b67..c51387c 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -30,6 +30,7 @@ config ARCH_SPINTABLE depends on ARCH_RAMSTAGE_ARM64 source src/arch/arm64/armv8/Kconfig +source src/arch/arm64/cpu/Kconfig # If a custom bootblock is necessary, this option should be "select"-ed by # the thing that needs it, probably the CPU. diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c9c93b1..7d36bf4 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -27,7 +27,7 @@ # Take care of subdirectories ################################################################################ -subdirs-y += armv8/ +subdirs-y += armv8/ cpu/ ################################################################################ # ARM specific options @@ -60,6 +60,7 @@ $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h bootblock-y += boot.c bootblock-y += c_entry.c bootblock-y += stage_entry.S +bootblock-y += cpu-stubs.c bootblock-y += stages.c bootblock-y += eabi_compat.c bootblock-y += transition.c transition_asm.S @@ -107,6 +108,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) romstage-y += boot.c romstage-y += c_entry.c romstage-y += stage_entry.S +romstage-y += cpu-stubs.c romstage-y += stages.c romstage-y += div0.c romstage-y += eabi_compat.c @@ -149,6 +151,7 @@ ramstage-y += ../../lib/memset.c ramstage-y += ../../lib/memcpy.c ramstage-y += ../../lib/memmove.c ramstage-y += stage_entry.S +ramstage-y += cpu-stubs.c ramstage-$(CONFIG_ARCH_SPINTABLE) += spintable.c spintable_asm.S ramstage-y += transition.c transition_asm.S @@ -158,6 +161,7 @@ rmodules_arm64-y += ../../lib/memmove.c rmodules_arm64-y += eabi_compat.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += stage_entry.S +secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu-stubs.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += startup.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/malloc.c secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memset.c diff --git a/src/arch/arm64/cpu-stubs.c b/src/arch/arm64/cpu-stubs.c new file mode 100644 index 0000000..c7b083e --- /dev/null +++ b/src/arch/arm64/cpu-stubs.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +void arm64_cpu_early_setup(void); + +void __attribute__((weak)) arm64_cpu_early_setup(void) +{ + /* Default empty implementation */ +} diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig new file mode 100644 index 0000000..fadd48a --- /dev/null +++ b/src/arch/arm64/cpu/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config ARCH_ARM64_CPU_CORTEX_A57 + bool + default n + depends on ARCH_ARM64 diff --git a/src/arch/arm64/cpu/Makefile.inc b/src/arch/arm64/cpu/Makefile.inc new file mode 100644 index 0000000..b4f39a5 --- /dev/null +++ b/src/arch/arm64/cpu/Makefile.inc @@ -0,0 +1,24 @@ +################################################################################ +## +## This file is part of the coreboot project. +## +## Copyright 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +################################################################################ + +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y) +ramstage-$(CONFIG_ARCH_ARM64_CPU_CORTEX_A57) += cortex_a57.S +endif diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S new file mode 100644 index 0000000..5039d1c --- /dev/null +++ b/src/arch/arm64/cpu/cortex_a57.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/asm.h> +#include "cortex_a57.h" + +ENTRY(arm64_cpu_early_setup) + mrs x0, CPUECTLR_EL1 + orr x0, x0, #(1 << SMPEN_SHIFT) + msr CPUECTLR_EL1, x0 + isb + ret +ENDPROC(arm64_cpu_early_setup) diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/cpu/cortex_a57.h new file mode 100644 index 0000000..9e66f4d --- /dev/null +++ b/src/arch/arm64/cpu/cortex_a57.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef __ARCH_ARM64_CORTEX_A57_H__ +#define __ARCH_ARM64_CORTEX_A57_H__ + +#define CPUECTLR_EL1 S3_1_c15_c2_1 +#define SMPEN_SHIFT 6 + +#endif /* __ARCH_ARM64_CORTEX_A57_H__ */ diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 6fdd20e..66e40fb 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -209,6 +209,7 @@ ENDPROC(__rmodule_entry) CPU_RESET_ENTRY(arm64_cpu_startup) split_bsp_path + bl arm64_cpu_early_setup setup_sctlr b arm64_c_environment ENDPROC(arm64_cpu_startup)

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coreboot-gerrit April 2015