coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 04baa2b cbmem: add and use a function to dump console buffer
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9984 -gerrit commit 04baa2bc288911c7782a7d34f973272cb4030ccf Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 18:04:04 2015 -0700 cbmem: add and use a function to dump console buffer The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. Some .h files' tweaking was required to ensure proper exposure of external declarations of uart_init(). BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/console/Kconfig | 9 +++++++++ src/include/console/cbmem_console.h | 1 + src/lib/cbmem_console.c | 17 +++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 2 ++ src/vendorcode/google/chromeos/vboot_common.c | 2 ++ 5 files changed, 31 insertions(+) diff --git a/src/console/Kconfig b/src/console/Kconfig index 2807039..9adab6d 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -184,6 +184,15 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_CBMEM_DUMP_TO_UART + depends on !CONSOLE_SERIAL + bool "Dump CBMEM console on resets" + default n + help + Enable this to have CBMEM console buffer contents dumped on the + serial output in case serial console is disabled and the device + resets itself while trying to boot the payload + endif config CONSOLE_QEMU_DEBUGCON diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 3431459..8f7fcb2 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -43,4 +43,5 @@ static inline void __cbmemc_init(void) {} static inline void __cbmemc_tx_byte(u8 data) {} #endif +void cbmem_dump_console(void); #endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 628d3b9..9d292bf 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <console/cbmem_console.h> +#include <console/uart.h> #include <cbmem.h> #include <arch/early_variables.h> #include <symbols.h> @@ -236,5 +237,21 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, size, flags); } +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART) +void cbmem_dump_console(void) +{ + struct cbmem_console *cbm_cons_p; + int cursor; + + cbm_cons_p = current_console(); + if (!cbm_cons_p) + return; + + uart_init(0); + for (cursor = 0; cursor < cbm_cons_p->buffer_cursor; cursor++) + uart_tx_byte(0, cbm_cons_p->buffer_body[cursor]); +} +#endif + /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit) diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index 44fe9e3..a151f54 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -234,6 +234,8 @@ static void init_vboot(int bootmode) #if !MOCK_TPM printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); post_code(POST_TPM_FAILURE); + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); hard_reset(); #endif } diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 3c1a9c3..2e38563 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -129,6 +129,8 @@ void *vboot_get_payload(int *len) void vboot_reboot(void) { + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); hard_reset(); die("failed to reboot"); }

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New patch to review for coreboot: 0b11c62 lint: remove test for build dir handling
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9988 -gerrit commit 0b11c62ac98333f08fe14770922bd86c0c0f33fb Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Apr 24 13:39:19 2015 +0200 lint: remove test for build dir handling This test outlives its usefulness and only slows down commits. We can now be confident that out-of-tree builds work because some of our automated builders do them regularly. Change-Id: I7c27e613ddd16f7bacbd4e232596b8a76e0c3301 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/lint/lint-stable-002-build-dir-handling | 73 ---------------------------- 1 file changed, 73 deletions(-) diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling deleted file mode 100755 index 013d84a..0000000 --- a/util/lint/lint-stable-002-build-dir-handling +++ /dev/null @@ -1,73 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Patrick Georgi <patrick(a)georgi-clan.de> -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# DESCR: Check that build directories can be chosen freely - -# $1: command to test for GNU make -search_make() { -if [ -n "`$1 --version 2>&1 | grep GNU`" ]; then MAKE=$1; fi -} - -# if $1 and $2 differ, exit with failure -compare_output() { -if ! [ "$1" = "$2" ]; then - echo \'$1\' should be \'$2\' - exit 1 -fi -} - -# $1: object directory -run_printall() { -$MAKE CONFIG_USE_BLOBS=n CONFIG_CCACHE=n NOMKDIR=1 \ - DOTCONFIG=$TMPCONFIG obj=$1 printall | \ - sed -e "s,^ *,," -e "s,^r.mstage-objs:=,," \ - -e "s,mainboard/[^/]*/[^/]*/,.../,g" | \ - tr " " "\n" | GREP_OPTIONS= grep "/static.*\.[co]" | sort | \ - tr '\012\015' ' ' | sed -e "s, *, ,g" -e "s, *$,," -} - -# find GNU make -MAKE= -search_make make -[ -z $MAKE ] && search_make gmake -[ -z $MAKE ] && search_make gnumake - -if [ "$MAKE" = "" ]; then - echo Could not identify GNU make - exit 1 -fi - -# prepare a config to use -TMPOBJ=`mktemp .tmpobj.XXXXXX` -rm $TMPOBJ -mkdir -p ${TMPOBJ} -TMPCONFIG=`mktemp .tmpconfig.XXXXXX` -rm -f $TMPCONFIG -$MAKE obj=$TMPOBJ DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null - -# look up parent directory -CURRENTDIR=`pwd -P` -PARENTDIR=`dirname $CURRENTDIR` - -compare_output "`run_printall build`" "build/.../static.c build/.../static.c build/.../static.romstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.romstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.romstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.romstage.o" - -rm -rf $TMPCONFIG $TMPOBJ -

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New patch to review for coreboot: f39ac53 chromeec: ec_mec: Fix misaligned data access
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9987 -gerrit commit f39ac53968ba8d1a940cb89cd8374f57670bdd37 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Apr 21 09:30:10 2015 -0700 chromeec: ec_mec: Fix misaligned data access Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/ec/google/chromeec/ec_mec.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/ec_mec.c b/src/ec/google/chromeec/ec_mec.c index 9836eda..a062371 100644 --- a/src/ec/google/chromeec/ec_mec.c +++ b/src/ec/google/chromeec/ec_mec.c @@ -76,12 +76,22 @@ void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum) { int i = 0; int io_addr; + u8 access_mode, new_access_mode; if (length == 0) return; + /* + * Long access cannot be used on misaligned data since reading B0 loads + * the data register and writing B3 flushes. + */ + if (port & 0x3) + access_mode = ACCESS_TYPE_BYTE; + else + access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT; + /* Initialize I/O at desired address */ - mec_emi_write_address(port, ACCESS_TYPE_LONG_AUTO_INCREMENT); + mec_emi_write_address(port, access_mode); /* Skip bytes in case of misaligned port */ io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3); @@ -94,11 +104,26 @@ void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum) if (csum) *csum += buf[i]; + port++; /* Extra bounds check in case of misaligned length */ if (++i == length) return; } + /* + * Use long auto-increment access except for misaligned write, + * since writing B3 triggers the flush. + */ + if (length - i < 4 && write) + new_access_mode = ACCESS_TYPE_BYTE; + else + new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT; + if (new_access_mode != access_mode || + access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) { + access_mode = new_access_mode; + mec_emi_write_address(port, access_mode); + } + /* Access [B0, B3] on each loop pass */ io_addr = MEC_EMI_EC_DATA_B0; }

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New patch to review for coreboot: cc3abb6 storm: enable CBMEM console dump
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9986 -gerrit commit cc3abb62fb4ce1c2b6c3cdd4b227dbfe443d31dd Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 19:23:16 2015 -0700 storm: enable CBMEM console dump This patch enables on storm the recently introduced 'console buffer dump on reboot' capability. BRANCH=none BUG=chromium:475347 TEST=generated storm image with serial console disabled and both rw firmware A and B sections corrupted. Programmed the new image on an SP5 device and rebooted it. Observed the device dump cbmem console buffer to the serial output, terminating with VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa Reboot requested (1008000a) Saving nvdata SF: Detected S25FL128S_256K with page size 10000, total 2000000 and the LED ring started flashing indicating recovery mode. Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8 Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265295 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/storm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index d2c011b..dfa00cc 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER - select VBOOT_DISABLE_DEV_ON_RECOVERY + select CONSOLE_CBMEM_DUMP_TO_UART select DRIVERS_I2C_WW_RING select HAVE_HARD_RESET select MAINBOARD_HAS_BOOTBLOCK_INIT @@ -34,6 +34,7 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO + select VBOOT_DISABLE_DEV_ON_RECOVERY select VIRTUAL_DEV_SWITCH select WIPEOUT_SUPPORTED

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New patch to review for coreboot: e7a5e5c Cygnus: add TZ functions and set everything non-secure in bootblock
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9985 -gerrit commit e7a5e5cc53dc9ed7e43b4a961c7748506eba6c0f Author: Corneliu Doban <cdoban(a)broadcom.com> Date: Fri Apr 10 15:51:55 2015 -0700 Cygnus: add TZ functions and set everything non-secure in bootblock To allow an OS to run in non-secure mode: - Set all peripherals and system components non-secure except SOTP and TZPC. - Sets all memory non-secure (ROM, SRAM, DDR, flash). - Enable A9 access to entire M0 address space except M0 ROM. BUG=chrome-os-partner:37533 BRANCH=broadcom-firmware TEST=boot kernel from usb stick Change-Id: I3bbd288863923011ff1413be353ac4b178ffdd07 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6de56bbe73ed8d87ad572da711a193985ee68e3a Original-Signed-off-by: Corneliu Doban <cdoban(a)broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212735 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)google.com> Original-Tested-by: Daisuke Nojiri <dnojiri(a)google.com> Original-Change-Id: Ibac7de03a72a98fbd95659d0113833049b4871a5 Original-Reviewed-on: https://chromium-review.googlesource.com/266593 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/broadcom/cygnus/Makefile.inc | 1 + src/soc/broadcom/cygnus/hw_init.c | 228 +++++++++++++----------- src/soc/broadcom/cygnus/include/soc/tz.h | 226 ++++++++++++++++++++++++ src/soc/broadcom/cygnus/tz.c | 287 +++++++++++++++++++++++++++++++ 4 files changed, 643 insertions(+), 99 deletions(-) diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index edeb687..4e09bed 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += bootblock.c bootblock-y += cbmem.c bootblock-y += i2c.c bootblock-y += timer.c +bootblock-y += tz.c bootblock-y += hw_init.c bootblock-$(CONFIG_SPI_FLASH) += spi.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c index 12adf66..e3fa49e 100644 --- a/src/soc/broadcom/cygnus/hw_init.c +++ b/src/soc/broadcom/cygnus/hw_init.c @@ -18,75 +18,139 @@ #include <arch/io.h> #include <delay.h> #include <console/console.h> +#include <soc/tz.h> #include <soc/hw_init.h> /***************************************************************************** * TrustZone *****************************************************************************/ -#define TZPC_TZPCDECPROT0SET 0x18034804 -#define TZPC_TZPCDECPROT0CLR 0x18034808 -#define TZPC_TZPCDECPROT1SET 0x18034810 -#define TZPC_TZPCDECPROT1CLR 0x18034814 -#define TZPC_TZPCDECPROT2SET 0x1803481c -#define TZPC_TZPCDECPROT2CLR 0x18034820 - -#define TZPCDECPROT0_MASK 0x000000FF -#define TZPCDECPROT1_MASK 0x000000FF -#define TZPCDECPROT2_MASK 0x000000FF - -#define TZ_STATE_SECURE 0 -#define TZ_STATE_NON_SECURE 1 - -#define CYGNUS_M_PCIE0_M0 0x00000003 -#define CYGNUS_M_PCIE1_M0 0x0000000c -#define CYGNUS_M_CMICD_M0 0x00000030 -#define CYGNUS_M_EXT_M0 0x000000c0 - -#define CYGNUS_M_EXT_M1 (0x00000003 << 8) -#define CYGNUS_M_SDIO_M0 (0x0000000c << 8) -#define CYGNUS_M_SDIO_M1 (0x00000030 << 8) -#define CYGNUS_M_AMAC_M0 (0x000000c0 << 8) - -#define CYGNUS_M_AMAC_M1 (0x00000003 << 16) -#define CYGNUS_M_USB2H_M0 (0x0000000c << 16) -#define CYGNUS_M_USB2D_M0 (0x00000030 << 16) -#define CYGNUS_M_A9JTAG_M0 (0x000000c0 << 16) - -#define IPROC_M_PCIE (CYGNUS_M_PCIE0_M0 | CYGNUS_M_PCIE1_M0) -#define IPROC_M_EXT (CYGNUS_M_EXT_M0 | CYGNUS_M_EXT_M1) -#define IPROC_M_SDIO (CYGNUS_M_SDIO_M0 | CYGNUS_M_SDIO_M1) -#define IPROC_M_AMAC (CYGNUS_M_AMAC_M0 | CYGNUS_M_AMAC_M1) -#define IPROC_M_USB (CYGNUS_M_USB2H_M0 | CYGNUS_M_USB2D_M0) -#define IPROC_M_CMICD (CYGNUS_M_CMICD_M0) - -static void tz_set_masters_security(uint32_t masters, uint32_t ns_bit) +#define IHOST_SCU_SECURE_ACCESS 0x19020054 + +#define SMAU_NIC_IDM_TZ_BASE 0x180150a0 +#define SMAU_DDR_TZ_BASE 0x18015200 +#define SMAU_FLASH0_TZ_BASE 0x18015300 +#define SMAU_FLASH1_TZ_BASE 0x18015308 +#define SMAU_FLASH2_TZ_BASE 0x18015310 +#define SMAU_FLASH3_TZ_BASE 0x18015318 +#define SMAU_TZ_BASE_ENABLE 0x00000001 + +#define CRMU_IPROC_ADDR_RANGE0_LOW 0x03024c30 +#define CRMU_IPROC_ADDR_RANGE0_HIGH 0x03024c34 +#define CRMU_ADDR_MASK 0xffffff00 +#define CRMU_ADDR_VALID 0x00000001 +#define CRMU_ADDR_START 0x03010000 +#define CRMU_ADDR_END 0x03100000 + +static void scu_ns_config(void) { - uint32_t val = 0; - - /* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */ - if (masters & TZPCDECPROT0_MASK) { - val = masters & TZPCDECPROT0_MASK; - if (ns_bit) - write32((void *)TZPC_TZPCDECPROT0SET, val); - else - write32((void *)TZPC_TZPCDECPROT0CLR, val); - } - /* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */ - if ((masters >> 8) & TZPCDECPROT1_MASK) { - val = (masters >> 8) & TZPCDECPROT1_MASK; - if (ns_bit) - write32((void *)TZPC_TZPCDECPROT1SET, val); - else - write32((void *)TZPC_TZPCDECPROT1CLR, val); - } - /* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */ - if ((masters >> 16) & TZPCDECPROT2_MASK) { - val = (masters >> 16) & TZPCDECPROT2_MASK; - if (ns_bit) - write32((void *)TZPC_TZPCDECPROT2SET, val); - else - write32((void *)TZPC_TZPCDECPROT2CLR, val); - } + /* + * Enable NS SCU access to ARM global timer, private timer, and + * components + */ + write32((void *)IHOST_SCU_SECURE_ACCESS, 0xFFF); +} + +static void smau_ns_config(void) +{ + unsigned int val; + + /* Disable SMAU NIC IDM TZ */ + val = read32((void *)SMAU_NIC_IDM_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_NIC_IDM_TZ_BASE, val); + + /* + * Disable DDR TZ base + * + * This means the entire DDR is marked as NS + * + * NOTE: In the future, multiple regions of DDR may need to be marked + * as SECURE for secure OS and other TZ usages + */ + val = read32((void *)SMAU_DDR_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_DDR_TZ_BASE, val); + + + /* + * Disable flash TZ support + * + * The entire flash is currently marked as NS + * + * NOTE: In the future, multiple regions of flash may need to be marked + * as SECURE for secure OS and other TZ firmware/data storage + */ + + /* Flash 0: ROM */ + val = read32((void *)SMAU_FLASH0_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH0_TZ_BASE, val); + + /* Flash 1: QSPI */ + val = read32((void *)SMAU_FLASH1_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH1_TZ_BASE, val); + + /* Flash 2: NAND */ + val = read32((void *)SMAU_FLASH2_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH2_TZ_BASE, val); + + /* Flash 3: PNOR */ + val = read32((void *)SMAU_FLASH3_TZ_BASE); + val &= ~SMAU_TZ_BASE_ENABLE; + write32((void *)SMAU_FLASH3_TZ_BASE, val); +} + +static void crmu_ns_config(void) +{ + + /* + * Currently open up the entire CRMU to allow iPROC NS access + * + * NOTE: In the future, we might want to protect particular CRMU + * sub-blocks to allow SECURE access only. That can be done by + * programing the CRMU IPROC address range registers. Up to 4 access + * windows can be created + */ + write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW, + (CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID); + write32((void *)CRMU_IPROC_ADDR_RANGE0_HIGH, + (CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID); +} + +static void tz_init(void) +{ + /* Configure the Cygnus for non-secure access */ + /* ARM Cortex A9 SCU NS access configuration */ + scu_ns_config(); + + /* SMAU NS related configurations */ + smau_ns_config(); + + /* CRMU NS related configurations */ + crmu_ns_config(); + + /* + * Configure multiple masters and slaves to run in NS + */ + tz_set_non_virtual_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + tz_set_periph_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + tz_set_masters_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + tz_set_wrapper_security(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + TZ_STATE_NON_SECURE); + tz_set_cfg_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + + tz_set_ext_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE); + + /* configure sec peripherals to be accessed from non-secure world */ + tz_set_sec_periphs_security(0xFFFFFFFF & + ~(CYGNUS_sec_periph_APBz_sotp | + CYGNUS_sec_periph_APBz_tzpc), + TZ_STATE_NON_SECURE); + + /* default sram to non-secure */ + tz_set_sram_sec_region(0); } /***************************************************************************** @@ -350,10 +414,6 @@ static void ccu_init(void) /***************************************************************************** * LCD *****************************************************************************/ -#define ASIU_TOP_LCD_AXI_SB_CTRL 0x180aa02c -#define ASIU_TOP_LCD_AXI_SB_CTRL_LCD_ARPROT_MASK 0x03800000 -#define ASIU_TOP_LCD_AXI_SB_CTRL_LCD_HPROT_NON_SECURE 0x40000000 - #define ASIU_TOP_CLK_GATING_CTRL 0x180aa024 #define ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN 0x00000010 #define ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN 0x00000008 @@ -364,12 +424,6 @@ static void lcd_init(void) { unsigned int val; - val = read32((void *)ASIU_TOP_LCD_AXI_SB_CTRL); - /* set LCD_ARPROT and LCD_HPROT_NON_SECURE to 0 */ - val &= ~(ASIU_TOP_LCD_AXI_SB_CTRL_LCD_ARPROT_MASK | - ASIU_TOP_LCD_AXI_SB_CTRL_LCD_HPROT_NON_SECURE); - write32((void *)ASIU_TOP_LCD_AXI_SB_CTRL, val); - /* make sure the LCD clock is ungated */ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL); val |= ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN; @@ -423,22 +477,10 @@ static void lcd_qos_init(unsigned int qos) /***************************************************************************** * V3D *****************************************************************************/ -#define ASIU_TOP_GFX_AXI_SB_CTRL 0x180aa034 -#define ASIU_TOP_GFX_AXI_SB_CTRL_GFX_ARPROT_MASK 0x03800000 -#define ASIU_TOP_GFX_AXI_SB_CTRL_GFX_AWPROT_MASK 0x00700000 - static void v3d_init(void) { unsigned int val; - val = read32((void *)ASIU_TOP_GFX_AXI_SB_CTRL); - /* - * set both GFX_ARPROT and GFX_AWPROT to 0 - */ - val &= ~(ASIU_TOP_GFX_AXI_SB_CTRL_GFX_ARPROT_MASK | - ASIU_TOP_GFX_AXI_SB_CTRL_GFX_AWPROT_MASK); - write32((void *)ASIU_TOP_GFX_AXI_SB_CTRL, val); - /* make sure the V3D clock is ungated */ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL); val |= ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN | @@ -455,10 +497,6 @@ static void v3d_init(void) #define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO 0x00000200 #define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN 0x00000100 -#define ASIU_TOP_AUD_AXI_SB_CTRL 0x180aa028 -#define ASIU_TOP_AUD_AXI_SB_CTRL_AUD_ARPROT_MASK 0x03800000 -#define ASIU_TOP_AUD_AXI_SB_CTRL_AUD_AWPROT_MASK 0x00700000 - static void audio_init(void) { unsigned int val; @@ -475,12 +513,6 @@ static void audio_init(void) val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL; val &= ~CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN; write32((void *)CRMU_PLL_AON_CTRL, val); - - /* Clear AWPROT and ARPROT signals to audio block. */ - val = read32((void *)ASIU_TOP_AUD_AXI_SB_CTRL); - val &= ~(ASIU_TOP_AUD_AXI_SB_CTRL_AUD_AWPROT_MASK | - ASIU_TOP_AUD_AXI_SB_CTRL_AUD_ARPROT_MASK); - write32((void *)ASIU_TOP_AUD_AXI_SB_CTRL, val); } /***************************************************************************** @@ -707,12 +739,10 @@ static void sdio_init(void) void hw_init(void) { - tz_set_masters_security(IPROC_M_PCIE | IPROC_M_EXT | IPROC_M_SDIO | - IPROC_M_AMAC | IPROC_M_USB | IPROC_M_CMICD, - TZ_STATE_SECURE); + tz_init(); printk(BIOS_INFO, "trustzone initialized\n"); dmac_init(); - printk(BIOS_INFO, "PL022 DMAC initialized\n"); + printk(BIOS_INFO, "PL330 DMAC initialized\n"); lcd_init(); lcd_qos_init(15); printk(BIOS_INFO, "LCD initialized\n"); diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h new file mode 100644 index 0000000..cb9ae63 --- /dev/null +++ b/src/soc/broadcom/cygnus/include/soc/tz.h @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_BROADCOM_CYGNUS_TZ_H__ +#define __SOC_BROADCOM_CYGNUS_TZ_H__ + +#define TZ_STATE_SECURE 0 +#define TZ_STATE_NON_SECURE 1 + +/* + * Masters (for parameter masters in "tz_set_masters_security") + */ +#define CYGNUS_M_Pcie0_m0 0x00000003 +#define CYGNUS_M_Pcie1_m0 0x0000000c +#define CYGNUS_M_cmicd_m0 0x00000030 +#define CYGNUS_M_ext_m0 0x000000c0 + +#define CYGNUS_M_ext_m1 (0x00000003 << 8) +#define CYGNUS_M_sdio_m0 (0x0000000c << 8) +#define CYGNUS_M_sdio_m1 (0x00000030 << 8) +#define CYGNUS_M_amac_m0 (0x000000c0 << 8) + +#define CYGNUS_M_amac_m1 (0x00000003 << 16) +#define CYGNUS_M_usb2h_m0 (0x0000000c << 16) +#define CYGNUS_M_usb2d_m0 (0x00000030 << 16) +#define CYGNUS_M_a9jtag_m0 (0x000000c0 << 16) + +/* + * Non virtual slaves (for parameter slave_vector in "tz_set_non_virtual_slaves_security") + * Note: the order has to match the order in non_virtual_slave_regs[] array from tz.c + */ +#define CYGNUS_S_Ihost_acp (0x1 << 0) +#define CYGNUS_S_PCIe0_s0 (0x1 << 1) +#define CYGNUS_S_PCIe1_s0 (0x1 << 2) +#define CYGNUS_S_ihost_s0 (0x1 << 3) +#define CYGNUS_S_A9jtag_s0 (0x1 << 4) +#define CYGNUS_S_CMICd_s0 (0x1 << 5) +#define CYGNUS_S_mhost0_s0 (0x1 << 6) +#define CYGNUS_S_mhost1_s0 (0x1 << 7) +#define CYGNUS_S_Crypto_s0 (0x1 << 8) +#define CYGNUS_S_DMU_s0 (0x1 << 9) + +/* + * Peripherals (for parameter slave_vector in "tz_set_periph_security") + */ +#define CYGNUS_periph_APBx_DMU 0x00008000 +#define CYGNUS_periph_APBx_cru 0x00004000 +#define CYGNUS_periph_APBx_ccg_smbus1 0x00000800 +#define CYGNUS_periph_APBx_ccg_gpio 0x00000400 +#define CYGNUS_periph_APBx_ccg_watchdog 0x00000200 +#define CYGNUS_periph_APBx_ccg_smbus0 0x00000100 +#define CYGNUS_periph_APBx_ccg_srab 0x00000080 +#define CYGNUS_periph_APBx_ccg_timer3 0x00000040 +#define CYGNUS_periph_APBx_ccg_timer2 0x00000020 +#define CYGNUS_periph_APBx_ccg_timer1 0x00000010 +#define CYGNUS_periph_APBx_ccg_timer0 0x00000008 +#define CYGNUS_periph_APBx_ccg_mdio 0x00000004 +#define CYGNUS_periph_APBx_ccg_pwm 0x00000002 +#define CYGNUS_periph_APBx_icfg 0x00000001 + +#define CYGNUS_periph_APBy_ccg_spi5 (0x00002000 << 16) +#define CYGNUS_periph_APBy_ccg_spi4 (0x00001000 << 16) +#define CYGNUS_periph_APBy_ccg_spi3 (0x00000800 << 16) +#define CYGNUS_periph_APBy_ccg_spi2 (0x00000400 << 16) +#define CYGNUS_periph_APBy_ccg_spi1 (0x00000200 << 16) +#define CYGNUS_periph_APBy_ccg_spi0 (0x00000100 << 16) +#define CYGNUS_periph_APBy_ccg_uart4 (0x00000010 << 16) +#define CYGNUS_periph_APBy_ccg_uart3 (0x00000008 << 16) +#define CYGNUS_periph_APBy_ccg_uart2 (0x00000004 << 16) +#define CYGNUS_periph_APBy_ccg_uart1 (0x00000002 << 16) +#define CYGNUS_periph_APBy_ccg_uart0 (0x00000001 << 16) + +/* + * Sececure Peripherals (for parameter slave_vector in "tz_set_sec_periphs_security") + */ +#define CYGNUS_sec_periph_APBz_sotp 0x00000020 +#define CYGNUS_sec_periph_APBz_tzpc 0x00000010 +#define CYGNUS_sec_periph_APBz_ccg_wdog 0x00000008 +#define CYGNUS_sec_periph_APBz_ccs_rng 0x00000004 +#define CYGNUS_sec_periph_APBz_ccs_pka 0x00000002 +#define CYGNUS_sec_periph_APBz_ccs_gpio 0x00000001 + +/* + * Cfg Slaves (for parameter slave_vector in "tz_set_cfg_slaves_security") + */ +#define CYGNUS_cfg_slv_APBr_mhost0 0x00004000 +#define CYGNUS_cfg_slv_APBr_dma_s1 0x00000200 +#define CYGNUS_cfg_slv_APBr_dma_s0 0x00000100 +#define CYGNUS_cfg_slv_APBr_acpal 0x00000040 +#define CYGNUS_cfg_slv_APBr_smau 0x00000020 +#define CYGNUS_cfg_slv_APBr_pcie1 0x00000008 +#define CYGNUS_cfg_slv_APBr_pcie0 0x00000004 +#define CYGNUS_cfg_slv_APBr_ddr 0x00000001 + +#define CYGNUS_cfg_slv_APBs_sram (0x00004000 << 16) +#define CYGNUS_cfg_slv_APBs_usb2d (0x00001000 << 16) +#define CYGNUS_cfg_slv_APBs_amac1 (0x00000400 << 16) +#define CYGNUS_cfg_slv_APBs_usb2h_apb2 (0x00000200 << 16) +#define CYGNUS_cfg_slv_APBs_usb2h_apb1 (0x00000100 << 16) +#define CYGNUS_cfg_slv_APBs_qspi (0x00000080 << 16) +#define CYGNUS_cfg_slv_APBs_nand (0x00000040 << 16) +#define CYGNUS_cfg_slv_APBs_nor (0x00000020 << 16) +#define CYGNUS_cfg_slv_APBs_sdio1 (0x00000008 << 16) +#define CYGNUS_cfg_slv_APBs_amac0 (0x00000004 << 16) +#define CYGNUS_cfg_slv_APBs_sdio0 (0x00000002 << 16) + +/* + * Wrapper1 (for parameter wrapper1 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W1_wrp_master_ihost_m0 0x00000001 +#define CYGNUS_APB_W1_wrp_master_pcie0_m0 0x00000002 +#define CYGNUS_APB_W1_wrp_master_pcie1_m0 0x00000004 +#define CYGNUS_APB_W1_wrp_master_cmicd_m0 0x00000008 +#define CYGNUS_APB_W1_wrp_master_mhost0_m0 0x00000010 +#define CYGNUS_APB_W1_wrp_master_mhost1_m0 0x00000020 +#define CYGNUS_APB_W1_wrp_slave_ihost_acp 0x00000040 +#define CYGNUS_APB_W1_wrp_slave_ihost_s0 0x00000080 +#define CYGNUS_APB_W1_wrp_slave_pcie0_s0 0x00000100 +#define CYGNUS_APB_W1_wrp_slave_pcie1_s0 0x00000200 +#define CYGNUS_APB_W1_wrp_slave_cmicd_s0 0x00000400 +#define CYGNUS_APB_W1_wrp_slave_smau_s0 0x00000800 +#define CYGNUS_APB_W1_wrp_slave_mhost0_s0 0x00001000 +#define CYGNUS_APB_W1_wrp_slave_mhost1_s0 0x00002000 +#define CYGNUS_APB_W1_wrp_slave_apbr 0x00004000 +#define CYGNUS_APB_W1_wrp_master_dma_m0 0x00008000 + +/* + * Wrapper2 (for parameter wrapper2 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W2_wrp_ds_ds_2 0x00000008 +#define CYGNUS_APB_W2_sdrom 0x00000004 +#define CYGNUS_APB_W2_wrp_ds_ds_1 0x00000002 +#define CYGNUS_APB_W2_wrp_ds_ds_0 0x00000001 + +/* + * Wrapper3 (for parameter wrapper3 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W3_wrp_master_amac_m1 0x00002000 +#define CYGNUS_APB_W3_wrp_ds_ds_3 0x00001000 +#define CYGNUS_APB_W3_wrp_slave_apbs 0x00000800 +#define CYGNUS_APB_W3_wrp_slave_sram_s0 0x00000400 +#define CYGNUS_APB_W3_wrp_master_sdio_m1 0x00000200 +#define CYGNUS_APB_W3_wrp_slave_a9jtag_s0 0x00000100 +#define CYGNUS_APB_W3_wrp_slave_crypto_s0 0x00000080 +#define CYGNUS_APB_W3_wrp_master_usb2h_m0 0x00000040 +#define CYGNUS_APB_W3_wrp_master_a9jtag_m0 0x00000020 +#define CYGNUS_APB_W3_wrp_master_ext_m1 0x00000010 +#define CYGNUS_APB_W3_wrp_master_sdio_m0 0x00000008 +#define CYGNUS_APB_W3_wrp_master_ext_m0 0x00000004 +#define CYGNUS_APB_W3_wrp_master_usb2d_m0 0x00000002 +#define CYGNUS_APB_W3_wrp_master_amac_m0 0x00000001 + +/* + * Wrapper4 (for parameter wrapper4 in "tz_set_wrapper_security") + */ +#define CYGNUS_APB_W4_wrp_slave_ext_s1 0x00000040 +#define CYGNUS_APB_W4_wrp_slave_dmu_s0 0x00000020 +#define CYGNUS_APB_W4_wrp_slave_ext_s0 0x00000010 +#define CYGNUS_APB_W4_wrp_master_dmu_m0 0x00000008 +#define CYGNUS_APB_W4_wrp_slave_apbz 0x00000004 +#define CYGNUS_APB_W4_wrp_slave_apby 0x00000002 +#define CYGNUS_APB_W4_wrp_slave_apbx 0x00000001 + +/* + * Ext Slaves (for parameter slave_vector in "tz_set_ext_slaves_security") + */ +#define CYGNUS_AXIIC_ext_s0_slave_0 0x00000001 /* LCD */ +#define CYGNUS_AXIIC_ext_s0_slave_1 0x00000002 /* Camera */ +#define CYGNUS_AXIIC_ext_s0_slave_2 0x00000004 +#define CYGNUS_AXIIC_ext_s0_slave_3 0x00000008 /* Smartcard */ +#define CYGNUS_AXIIC_ext_s0_slave_4 0x00000010 /* S-GPIO */ +#define CYGNUS_AXIIC_ext_s0_slave_5 0x00000020 /* GPIO */ +#define CYGNUS_AXIIC_ext_s0_slave_6 0x00000040 /* ADC_APB */ +#define CYGNUS_AXIIC_ext_s0_slave_7 0x00000080 +#define CYGNUS_AXIIC_ext_s0_slave_8 0x00000100 /* GFX_S0 */ +#define CYGNUS_AXIIC_ext_s0_slave_9 0x00000200 /* MIPI */ +#define CYGNUS_AXIIC_ext_s0_slave_10 0x00000400 /* ASIU_TOP */ +#define CYGNUS_AXIIC_ext_s0_slave_11 0x00000800 /* D1W */ +#define CYGNUS_AXIIC_ext_s0_slave_12 0x00001000 /* Keypad */ +#define CYGNUS_AXIIC_ext_s0_slave_13 0x00002000 /* Keypad */ +#define CYGNUS_AXIIC_ext_s0_slave_14 0x00004000 /* Audio */ +#define CYGNUS_AXIIC_ext_s0_slave_15 0x00008000 + +#define CYGNUS_AXIIC_ext_s1_slave_0 (0x00000001 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_1 (0x00000002 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_2 (0x00000004 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_3 (0x00000008 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_4 (0x00000010 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_5 (0x00000020 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_6 (0x00000040 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_7 (0x00000080 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_8 (0x00000100 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_9 (0x00000200 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_10 (0x00000400 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_11 (0x00000800 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_12 (0x00001000 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_13 (0x00002000 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_14 (0x00004000 << 16) +#define CYGNUS_AXIIC_ext_s1_slave_15 (0x00008000 << 16) + +void tz_set_masters_security(uint32_t masters, uint32_t ns_bit); +void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2, + uint32_t wrapper3, uint32_t wrapper4, + uint32_t ns_bit); +void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit); +void tz_set_sram_sec_region(uint32_t r0size); +void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit); + +#endif diff --git a/src/soc/broadcom/cygnus/tz.c b/src/soc/broadcom/cygnus/tz.c new file mode 100644 index 0000000..e35669b --- /dev/null +++ b/src/soc/broadcom/cygnus/tz.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/tz.h> + +#define TZPC_TZPCR0SIZE 0x18034000 +#define TZPC_TZPCR0SIZE_MASK 0x000003ff + +#define TZPC_TZPCDECPROT0SET 0x18034804 +#define TZPC_TZPCDECPROT0CLR 0x18034808 +#define TZPC_TZPCDECPROT1SET 0x18034810 +#define TZPC_TZPCDECPROT1CLR 0x18034814 +#define TZPC_TZPCDECPROT2SET 0x1803481c +#define TZPC_TZPCDECPROT2CLR 0x18034820 + +#define TZPCDECPROT0_MASK 0x000000FF +#define TZPCDECPROT1_MASK 0x000000FF +#define TZPCDECPROT2_MASK 0x000000FF + +#define AXIIC_Ihost_acp_security 0x1a000008 +#define AXIIC_PCIe0_s0_security 0x1a000010 +#define AXIIC_PCIe1_s0_security 0x1a000014 +#define AXIIC_APBY_s0_security 0x1a00002c +#define AXIIC_APBZ_s0_security 0x1a000030 +#define AXIIC_APBX_s0_security 0x1a000034 +#define AXIIC_ihost_s0_security 0x1a000038 +#define AXIIC_A9jtag_s0_security 0x1a00003c +#define AXIIC_APB_W1_security 0x1a000040 +#define AXIIC_APB_W2_security 0x1a000044 +#define AXIIC_APB_W3_security 0x1a000048 +#define AXIIC_APB_W4_security 0x1a00004c +#define AXIIC_APBR_s0_security 0x1a00006c +#define AXIIC_APBS_s0_security 0x1a000070 +#define AXIIC_CMICd_s0_security 0x1a000074 +#define AXIIC_mhost0_s0_security 0x1a000078 +#define AXIIC_mhost1_s0_security 0x1a00007c +#define AXIIC_Crypto_s0_security 0x1a000080 +#define AXIIC_DMU_s0_security 0x1a000084 +#define AXIIC_ext_s0_security 0x1a000088 +#define AXIIC_ext_s1_security 0x1a00008c + +#define AXIIC_APBY_s0_security_MASK 0x00003f1f +#define AXIIC_APBZ_s0_security_MASK 0x0000003f +#define AXIIC_APBX_s0_security_MASK 0x0000cfff +#define AXIIC_ext_s0_security_MASK 0xffffffff +#define AXIIC_ext_s1_security_MASK 0xffffffff +#define AXIIC_APBR_s0_security_MASK 0x0000436d +#define AXIIC_APBS_s0_security_MASK 0x000057ee +#define AXIIC_APB_W1_security_MASK 0x0000ffff +#define AXIIC_APB_W2_security_MASK 0x0000000f +#define AXIIC_APB_W3_security_MASK 0x00003fff +#define AXIIC_APB_W4_security_MASK 0x0000007f + +/* + * Note: the order need to match corresponding definitions for + * non virtual slave slave_vector in tz.h + */ +static uint32_t non_virtual_slave_regs[] = { + AXIIC_Ihost_acp_security, + AXIIC_PCIe0_s0_security, + AXIIC_PCIe1_s0_security, + AXIIC_ihost_s0_security, + AXIIC_A9jtag_s0_security, + AXIIC_CMICd_s0_security, + AXIIC_mhost0_s0_security, + AXIIC_mhost1_s0_security, + AXIIC_Crypto_s0_security, + AXIIC_DMU_s0_security +}; + +/* + * Set master security. + * Use defines in tz.h for both parameters. + */ +void tz_set_masters_security(uint32_t masters, uint32_t ns_bit) +{ + uint32_t val; + + /* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */ + if (masters & TZPCDECPROT0_MASK) { + val = masters & TZPCDECPROT0_MASK; + if (ns_bit) + write32((void *)TZPC_TZPCDECPROT0SET, val); + else + write32((void *)TZPC_TZPCDECPROT0CLR, val); + } + /* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */ + if ((masters >> 8) & TZPCDECPROT1_MASK) { + val = (masters >> 8) & TZPCDECPROT1_MASK; + if (ns_bit) + write32((void *)TZPC_TZPCDECPROT1SET, val); + else + write32((void *)TZPC_TZPCDECPROT1CLR, val); + } + /* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */ + if ((masters >> 16) & TZPCDECPROT2_MASK) { + val = (masters >> 16) & TZPCDECPROT2_MASK; + if (ns_bit) + write32((void *)TZPC_TZPCDECPROT2SET, val); + else + write32((void *)TZPC_TZPCDECPROT2CLR, val); + } +} + +/* + * Set non virtual slave security. + * Use defines in tz.h for both parameters. + */ +void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t i; + uint32_t total = sizeof(non_virtual_slave_regs) / + sizeof(non_virtual_slave_regs[0]); + uint32_t mask = ~(0xffffffff << total); + + ns_bit &= 0x1; + slave_vector = slave_vector & mask; + for (i = 0; i < total; i++) { + if (slave_vector & (0x1 << i)) + write32((void *)(non_virtual_slave_regs[i]), ns_bit); + } +} + +/* + * Set peripheral security. + * Use defines in tz.h for both parameters. + */ +void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask_x = AXIIC_APBX_s0_security_MASK; + uint32_t mask_y = AXIIC_APBY_s0_security_MASK; + uint32_t tz_periphs_sec_status = + (mask_x & read32((void *)AXIIC_APBX_s0_security)) | + ((mask_y & read32((void *)AXIIC_APBY_s0_security)) << 16); + + if (ns_bit == TZ_STATE_SECURE) + tz_periphs_sec_status &= ~slave_vector; + else + tz_periphs_sec_status |= slave_vector; + + val = tz_periphs_sec_status & mask_x; + write32((void *)AXIIC_APBX_s0_security, val); + + val = (tz_periphs_sec_status >> 16) & mask_y; + write32((void *)AXIIC_APBY_s0_security, val); +} + +/* + * Set sec peripheral security. + * Use defines in tz.h for both parameters. + */ +void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask = AXIIC_APBZ_s0_security_MASK; + uint32_t tz_sec_periphs_sec_status = + read32((void *)AXIIC_APBZ_s0_security); + + if (ns_bit == TZ_STATE_SECURE) + tz_sec_periphs_sec_status &= ~slave_vector; + else + tz_sec_periphs_sec_status |= slave_vector; + + val = tz_sec_periphs_sec_status & mask; + write32((void *)AXIIC_APBZ_s0_security, val); +} + +/* + * Set external slave security. + * Use defines in tz.h for both parameters. + */ +void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask_s0 = AXIIC_ext_s0_security_MASK; + uint32_t mask_s1 = AXIIC_ext_s1_security_MASK; + uint32_t tz_ext_slaves_sec_status = + (mask_s0 & read32((void *)AXIIC_ext_s0_security)) | + ((mask_s1 & read32((void *)AXIIC_ext_s0_security)) << 16); + + if (ns_bit == TZ_STATE_SECURE) + tz_ext_slaves_sec_status &= ~slave_vector; + else + tz_ext_slaves_sec_status |= slave_vector; + + val = tz_ext_slaves_sec_status & mask_s0; + write32((void *)AXIIC_ext_s0_security, val); + + val = (tz_ext_slaves_sec_status >> 16) & mask_s1; + write32((void *)AXIIC_ext_s1_security, val); +} + +/* + * Set cfg slave security + * Use defines in tz.h for both parameters. + */ +void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit) +{ + uint32_t val; + uint32_t mask_r = AXIIC_APBR_s0_security_MASK; + uint32_t mask_s = AXIIC_APBS_s0_security_MASK; + uint32_t tz_cfg_slaves_sec_status = + (mask_r & read32((void *)AXIIC_APBR_s0_security)) | + ((mask_s & read32((void *)AXIIC_APBS_s0_security)) << 16); + + if (ns_bit == TZ_STATE_SECURE) + tz_cfg_slaves_sec_status &= ~slave_vector; + else + tz_cfg_slaves_sec_status |= slave_vector; + + val = tz_cfg_slaves_sec_status & mask_r; + write32((void *)AXIIC_APBR_s0_security, val); + + val = (tz_cfg_slaves_sec_status >> 16) & mask_s; + write32((void *)AXIIC_APBS_s0_security, val); +} + +/* + * Set SRAM secure region + * parameter 'r0size' specify the secure RAM region in 4KB steps: + * 0x00000000 = no secure region + * 0x00000001 = 4KB secure region + * 0x00000002 = 8KB secure region + * ....... + * 0x000001FF = 2044KB secure region. + * 0x00000200 or above sets the entire SRAM to secure regardless of size + */ +void tz_set_sram_sec_region(uint32_t r0size) +{ + uint32_t mask = TZPC_TZPCR0SIZE_MASK; + + write32((void *)TZPC_TZPCR0SIZE, r0size & mask); +} + +/* + * Set wrapper security + * Use defines in tz.h for all parameters. + */ +void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2, + uint32_t wrapper3, uint32_t wrapper4, + uint32_t ns_bit) +{ + uint32_t mask_w4 = AXIIC_APB_W4_security_MASK; + uint32_t mask_w3 = AXIIC_APB_W3_security_MASK; + uint32_t mask_w2 = AXIIC_APB_W2_security_MASK; + uint32_t mask_w1 = AXIIC_APB_W1_security_MASK; + uint32_t tz_wrapper1_sec_status = read32((void *)AXIIC_APB_W1_security); + uint32_t tz_wrapper2_sec_status = read32((void *)AXIIC_APB_W2_security); + uint32_t tz_wrapper3_sec_status = read32((void *)AXIIC_APB_W3_security); + uint32_t tz_wrapper4_sec_status = read32((void *)AXIIC_APB_W4_security); + + if (ns_bit == TZ_STATE_SECURE) { + tz_wrapper1_sec_status &= ~wrapper1; + tz_wrapper2_sec_status &= ~wrapper2; + tz_wrapper3_sec_status &= ~wrapper3; + tz_wrapper4_sec_status &= ~wrapper4; + } else { + tz_wrapper1_sec_status |= wrapper1; + tz_wrapper2_sec_status |= wrapper2; + tz_wrapper3_sec_status |= wrapper3; + tz_wrapper4_sec_status |= wrapper4; + } + write32((void *)AXIIC_APB_W1_security, + tz_wrapper1_sec_status & mask_w1); + write32((void *)AXIIC_APB_W2_security, + tz_wrapper2_sec_status & mask_w2); + write32((void *)AXIIC_APB_W3_security, + tz_wrapper3_sec_status & mask_w3); + write32((void *)AXIIC_APB_W4_security, + tz_wrapper4_sec_status & mask_w4); +}

1 0

New patch to review for coreboot: 361cc1d cbmem: add and use a function to dump console buffer
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9984 -gerrit commit 361cc1dd3f59c1bde1d1890b9c2e2feded90ffeb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Apr 10 18:04:04 2015 -0700 cbmem: add and use a function to dump console buffer The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. Some .h files' tweaking was required to ensure proper exposure of external declarations of uart_init(). BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/console/Kconfig | 9 +++++++++ src/include/console/cbmem_console.h | 1 + src/lib/cbmem_console.c | 17 +++++++++++++++++ src/vendorcode/google/chromeos/vboot.c | 2 ++ src/vendorcode/google/chromeos/vboot_common.c | 2 ++ 5 files changed, 31 insertions(+) diff --git a/src/console/Kconfig b/src/console/Kconfig index 2807039..9adab6d 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -184,6 +184,15 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_CBMEM_DUMP_TO_UART + depends on !CONSOLE_SERIAL + bool "Dump CBMEM console on resets" + default n + help + Enable this to have CBMEM console buffer contents dumped on the + serial output in case serial console is disabled and the device + resets itself while trying to boot the payload + endif config CONSOLE_QEMU_DEBUGCON diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 3431459..8f7fcb2 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -43,4 +43,5 @@ static inline void __cbmemc_init(void) {} static inline void __cbmemc_tx_byte(u8 data) {} #endif +void cbmem_dump_console(void); #endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 628d3b9..27b4afa 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <console/cbmem_console.h> +#include <console/uart.h> #include <cbmem.h> #include <arch/early_variables.h> #include <symbols.h> @@ -236,5 +237,21 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, size, flags); } +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART) +void cbmem_dump_console(void) +{ + struct cbmem_console *cbm_cons_p; + int cursor; + + cbm_cons_p = current_console(); + if (!cbm_cons_p) + return; + + uart_init(); + for (cursor = 0; cursor < cbm_cons_p->buffer_cursor; cursor++) + uart_tx_byte(cbm_cons_p->buffer_body[cursor]); +} +#endif + /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit) diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c index 44fe9e3..a151f54 100644 --- a/src/vendorcode/google/chromeos/vboot.c +++ b/src/vendorcode/google/chromeos/vboot.c @@ -234,6 +234,8 @@ static void init_vboot(int bootmode) #if !MOCK_TPM printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); post_code(POST_TPM_FAILURE); + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); hard_reset(); #endif } diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 3c1a9c3..2e38563 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -129,6 +129,8 @@ void *vboot_get_payload(int *len) void vboot_reboot(void) { + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); hard_reset(); die("failed to reboot"); }

1 0

New patch to review for coreboot: 4ffe119 lib: tlcl: build with mocked_tlcl.c if MOCK_TPM=1
by Patrick Georgi 24 Apr '15

24 Apr '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9983 -gerrit commit 4ffe119697b2cabe45071b9173b3cba03d695578 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed Apr 8 16:55:17 2015 -0700 lib: tlcl: build with mocked_tlcl.c if MOCK_TPM=1 And, the new mocked_tlcl.c returns TPM_E_NO_DEVICE for all calls. BRANCH=None BUG=None TEST=manual MOCK_TPM=1 emerge-foster coreboot, and coreboot can boot to kernel Change-Id: Id7e79b58fabeac929b874385064b2417db49a708 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a9a91a65af115657e7317754eda931120750c56d Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Change-Id: I8dcf0db14cf2bc76c67a3bd7f06114e70e08764d Original-Reviewed-on: https://chromium-review.googlesource.com/264946 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/lib/Makefile.inc | 6 +++ src/lib/mocked_tlcl.c | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f0fb02874..78b16d9 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -35,7 +35,13 @@ verstage-y += cbfs.c verstage-y += memcmp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c + +ifeq ($(MOCK_TPM),1) +verstage-y += mocked_tlcl.c +else verstage-y += tlcl.c +endif + verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c diff --git a/src/lib/mocked_tlcl.c b/src/lib/mocked_tlcl.c new file mode 100644 index 0000000..628afc2 --- /dev/null +++ b/src/lib/mocked_tlcl.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <tpm_lite/tlcl.h> + +#ifdef FOR_TEST +#include <stdio.h> +#define VBDEBUG(format, args...) printf(format, ## args) +#else +#include <console/console.h> +#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) +#endif + +uint32_t tlcl_lib_init(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_startup(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_resume(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_self_test_full(void) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_continue_self_test(void) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + + +uint32_t tlcl_assert_physical_presence(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_physical_presence_cmd_enable(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_finalize_physical_presence(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_nv_locked(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_force_clear(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_enable(void) { + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_deactivated(uint8_t flag) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, + uint8_t *nvlocked) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_set_global_lock(void) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +} + +uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, + uint8_t* out_digest) +{ + VBDEBUG("MOCK_TPM: %s\n", __func__); + return TPM_E_NO_DEVICE; +}

1 0

Patch set updated for coreboot: 62258c3 OxPCIe: Fix UART base addresses
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8780 -gerrit commit 62258c30bb1576c8fe9331fa657bcf7e9da51366 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 20 08:51:57 2015 +0200 OxPCIe: Fix UART base addresses The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/oxpcie_early.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index 9daafc5..d560513 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -30,7 +30,6 @@ static unsigned int oxpcie_present CAR_GLOBAL; static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { @@ -79,10 +78,8 @@ static int oxpcie_uart_active(void) uintptr_t uart_platform_base(int idx) { - if (idx == 0 && oxpcie_uart_active()) - return uart0_base; - if (idx == 1 && oxpcie_uart_active()) - return uart1_base; + if ((idx >= 0) && (idx < 8) && oxpcie_uart_active()) + return uart0_base + idx * 0x200; return 0; } @@ -90,7 +87,6 @@ uintptr_t uart_platform_base(int idx) void oxford_remap(u32 new_base) { uart0_base = new_base + 0x1000; - uart1_base = new_base + 0x2000; } void uart_fill_lb(void *data)

1 0

Patch set updated for coreboot: 641760e PCI subsystem: Drop PCI_64BIT_PREF_MEM option
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8705 -gerrit commit 641760ef486ef454a8a39f00925f3385c8cd562f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 17 06:42:54 2015 +0200 PCI subsystem: Drop PCI_64BIT_PREF_MEM option No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 5 -- src/device/device.c | 35 ++------- src/mainboard/asus/kfsn4-dre/Kconfig | 4 -- src/mainboard/asus/m2n-e/Kconfig | 4 -- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 4 -- src/mainboard/gigabyte/m57sli/Kconfig | 4 -- src/mainboard/msi/ms7260/Kconfig | 4 -- src/mainboard/msi/ms9282/Kconfig | 4 -- src/mainboard/nvidia/l1_2pvv/Kconfig | 4 -- src/mainboard/tyan/s2912/Kconfig | 4 -- src/mainboard/tyan/s2912_fam10/Kconfig | 4 -- src/northbridge/amd/agesa/family10/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family12/northbridge.c | 81 +-------------------- src/northbridge/amd/agesa/family14/northbridge.c | 82 ---------------------- src/northbridge/amd/agesa/family15/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15rl/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family16kb/northbridge.c | 77 -------------------- src/northbridge/amd/amdfam10/northbridge.c | 76 -------------------- src/northbridge/amd/amdk8/northbridge.c | 68 ------------------ src/northbridge/amd/pi/00630F01/northbridge.c | 77 +------------------- src/northbridge/amd/pi/00730F01/northbridge.c | 78 -------------------- 22 files changed, 8 insertions(+), 915 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 8ddb58c..beb29fb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -205,11 +205,6 @@ config PCI bool default n -config PCI_64BIT_PREF_MEM - bool - depends on PCI - default n - config HYPERTRANSPORT_PLUGIN_SUPPORT bool depends on PCI diff --git a/src/device/device.c b/src/device/device.c index 35bb6e2..c0efa1f 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -611,19 +611,14 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, } } -#if CONFIG_PCI_64BIT_PREF_MEM -#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) -#else #define MEM_MASK (IORESOURCE_MEM) -#endif - #define IO_MASK (IORESOURCE_IO) #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) #define MEM_TYPE (IORESOURCE_MEM) #define IO_TYPE (IORESOURCE_IO) struct constraints { - struct resource pref, io, mem; + struct resource io, mem; }; static void constrain_resources(struct device *dev, struct constraints* limits) @@ -644,10 +639,8 @@ static void constrain_resources(struct device *dev, struct constraints* limits) continue; } - /* PREFETCH, MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == PREF_TYPE) - lim = &limits->pref; - else if ((res->flags & MEM_MASK) == MEM_TYPE) + /* MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == MEM_TYPE) lim = &limits->mem; else if ((res->flags & IO_MASK) == IO_TYPE) lim = &limits->io; @@ -696,8 +689,6 @@ static void avoid_fixed_resources(struct device *dev) printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); /* Initialize constraints to maximum size. */ - limits.pref.base = 0; - limits.pref.limit = 0xffffffffffffffffULL; limits.io.base = 0; limits.io.limit = 0xffffffffffffffffULL; limits.mem.base = 0; @@ -709,9 +700,7 @@ static void avoid_fixed_resources(struct device *dev) continue; printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, dev_path(dev), res->index, res->limit); - if ((res->flags & MEM_MASK) == PREF_TYPE && - (res->limit < limits.pref.limit)) - limits.pref.limit = res->limit; + if ((res->flags & MEM_MASK) == MEM_TYPE && (res->limit < limits.mem.limit)) limits.mem.limit = res->limit; @@ -730,10 +719,8 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & IORESOURCE_FIXED)) continue; - /* PREFETCH, MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == PREF_TYPE) - lim = &limits.pref; - else if ((res->flags & MEM_MASK) == MEM_TYPE) + /* MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == MEM_TYPE) lim = &limits.mem; else if ((res->flags & IO_MASK) == IO_TYPE) lim = &limits.io; @@ -1038,11 +1025,6 @@ void dev_configure(void) for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; - if (res->flags & IORESOURCE_PREFETCH) { - compute_resources(child->link_list, - res, MEM_MASK, PREF_TYPE); - continue; - } if (res->flags & IORESOURCE_MEM) { compute_resources(child->link_list, res, MEM_MASK, MEM_TYPE); @@ -1070,11 +1052,6 @@ void dev_configure(void) for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; - if (res->flags & IORESOURCE_PREFETCH) { - allocate_resources(child->link_list, - res, MEM_MASK, PREF_TYPE); - continue; - } if (res->flags & IORESOURCE_MEM) { allocate_resources(child->link_list, res, MEM_MASK, MEM_TYPE); diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 47fccda..558f758 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..c86de2d 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -65,10 +65,6 @@ config MAINBOARD_PART_NUMBER string default "M2N-E" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..660ac1c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -45,10 +45,6 @@ config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..3132d37 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..60ea9ea 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -47,10 +47,6 @@ config MAINBOARD_PART_NUMBER string default "MS-7260" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..e88f36f 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER string default "MS-9282" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..7694492 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -51,10 +51,6 @@ config MAINBOARD_PART_NUMBER string default "l1_2pvv" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..8b59eb5 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER string default "S2912" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..1e0d4d0 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index cd36192..3a18452 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -635,29 +635,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void amdfam10_domain_enable_resources(device_t dev) @@ -737,10 +715,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -751,57 +725,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 9d078ed..5328cec 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -509,9 +509,6 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM -//- pci_domain_read_resources(dev); - struct resource *resource; /* Initialize the system-wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -526,27 +523,7 @@ static void domain_read_resources(device_t dev) resource->limit = 0xdfffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -556,10 +533,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -570,58 +543,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - -printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4017944..f00c405 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -498,29 +498,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link = dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0 | (link->link_num << 2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void setup_uma_memory(void) @@ -553,10 +531,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -567,62 +541,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1 | (link->link_num << 2)); - mem2 = find_resource(dev, 2 | (link->link_num << 2)); - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem1->base), (u32) (mem1->limit), - (u32) (mem1->size), u32) (mem1->align)); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem2->base), (u32) (mem2->limit), - (u32) (mem2->size), (u32) (mem2->align)); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) - || ((mem1->limit > 0xffffffff) - && (mem2->limit > 0xffffffff))) { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 593579e..49e6783 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -668,30 +668,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -792,10 +769,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 223a0a0..abd281c 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -663,30 +663,7 @@ static void domain_read_resources(struct device *dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(struct device *dev) @@ -787,10 +764,6 @@ static void setup_uma_memory(void) static void domain_set_resources(struct device *dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -801,56 +774,6 @@ static void domain_set_resources(struct device *dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index a18da68..29bcb2a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -661,30 +661,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -785,10 +762,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -799,56 +772,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d0638ca..8de76f6 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,30 +677,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -803,10 +780,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -817,56 +790,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f857b72..1822bad 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -634,29 +634,8 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif #if CONFIG_MMCONF_SUPPORT struct resource *res = new_resource(dev, 0xc0010058); res->base = CONFIG_MMCONF_BASE_ADDRESS; @@ -752,10 +731,6 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; int i, idx; @@ -765,57 +740,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a17aa65..b42b6bf 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -667,13 +667,6 @@ static void amdk8_domain_read_resources(device_t dev) } pci_domain_read_resources(dev); - -#if CONFIG_PCI_64BIT_PREF_MEM - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; -#endif } static void my_tolm_test(void *gp, struct device *dev, struct resource *new) @@ -904,10 +897,6 @@ static void setup_uma_memory(void) static void amdk8_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -917,63 +906,6 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; -#endif -#if CONFIG_PCI_64BIT_PREF_MEM - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = my_find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f8b3246..e5fa0cb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -654,29 +654,8 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM)) pci_domain_read_resources(dev); - else { - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } - } + } static void domain_enable_resources(device_t dev) @@ -780,10 +759,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -794,56 +769,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b10da3d..d33f021 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -663,31 +663,7 @@ static void domain_read_resources(device_t dev) } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -796,10 +772,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -810,56 +782,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link);

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Patch set updated for coreboot: 4af421c resource: Refactor IORESOURCE flags use
by Kyösti Mälkki 24 Apr '15

24 Apr '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8891 -gerrit commit 4af421c95635b71b5410ad423f038969f23f9060 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 26 20:04:38 2015 +0200 resource: Refactor IORESOURCE flags use The type of a resource is really an enumeration but our implementation is as a bitmask. Compare all relevant bits and remove the shadowed declarations of IORESOURCE bits. Change-Id: I7f605d72ea702eb4fa6019ca1297f98d240c4f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 63 +++++++++++++++++++++++-------------------- src/include/device/resource.h | 2 ++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index c0efa1f..72f2373 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -611,16 +611,28 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, } } -#define MEM_MASK (IORESOURCE_MEM) -#define IO_MASK (IORESOURCE_IO) -#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) -#define MEM_TYPE (IORESOURCE_MEM) -#define IO_TYPE (IORESOURCE_IO) +static int resource_is(struct resource *res, u32 type) +{ + return (res->flags & IORESOURCE_TYPE_MASK) == type; +} struct constraints { struct resource io, mem; }; +static struct resource * resource_limit(struct constraints *limits, struct resource *res) +{ + struct resource *lim = NULL; + + /* MEM, or I/O - skip any others. */ + if (resource_is(res, IORESOURCE_MEM)) + lim = &limits->mem; + else if (resource_is(res, IORESOURCE_IO)) + lim = &limits->io; + + return lim; +} + static void constrain_resources(struct device *dev, struct constraints* limits) { struct device *child; @@ -639,12 +651,8 @@ static void constrain_resources(struct device *dev, struct constraints* limits) continue; } - /* MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == MEM_TYPE) - lim = &limits->mem; - else if ((res->flags & IO_MASK) == IO_TYPE) - lim = &limits->io; - else + lim = resource_limit(limits, res); + if (!lim) continue; /* @@ -685,6 +693,7 @@ static void avoid_fixed_resources(struct device *dev) { struct constraints limits; struct resource *res; + struct resource *lim; printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); @@ -701,12 +710,14 @@ static void avoid_fixed_resources(struct device *dev) printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, dev_path(dev), res->index, res->limit); - if ((res->flags & MEM_MASK) == MEM_TYPE && - (res->limit < limits.mem.limit)) - limits.mem.limit = res->limit; - if ((res->flags & IO_MASK) == IO_TYPE && - (res->limit < limits.io.limit)) - limits.io.limit = res->limit; + lim = resource_limit(&limits, res); + if (!lim) + continue; + + if (res->base > lim->base) + lim->base = res->base; + if (res->limit < lim->limit) + lim->limit = res->limit; } /* Look through the tree for fixed resources and update the limits. */ @@ -714,17 +725,11 @@ static void avoid_fixed_resources(struct device *dev) /* Update dev's resources with new limits. */ for (res = dev->resource_list; res; res = res->next) { - struct resource *lim; - if ((res->flags & IORESOURCE_FIXED)) continue; - /* MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == MEM_TYPE) - lim = &limits.mem; - else if ((res->flags & IO_MASK) == IO_TYPE) - lim = &limits.io; - else + lim = resource_limit(&limits, res); + if (!lim) continue; /* Is the resource outside the limits? */ @@ -1027,12 +1032,12 @@ void dev_configure(void) continue; if (res->flags & IORESOURCE_MEM) { compute_resources(child->link_list, - res, MEM_MASK, MEM_TYPE); + res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); continue; } if (res->flags & IORESOURCE_IO) { compute_resources(child->link_list, - res, IO_MASK, IO_TYPE); + res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); continue; } } @@ -1054,12 +1059,12 @@ void dev_configure(void) continue; if (res->flags & IORESOURCE_MEM) { allocate_resources(child->link_list, - res, MEM_MASK, MEM_TYPE); + res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); continue; } if (res->flags & IORESOURCE_IO) { allocate_resources(child->link_list, - res, IO_MASK, IO_TYPE); + res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); continue; } } diff --git a/src/include/device/resource.h b/src/include/device/resource.h index c01540a..768c86d 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -11,6 +11,8 @@ #define IORESOURCE_IRQ 0x00000400 #define IORESOURCE_DRQ 0x00000800 +#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_IRQ | IORESOURCE_DRQ) + #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ #define IORESOURCE_READONLY 0x00002000 #define IORESOURCE_CACHEABLE 0x00004000

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coreboot-gerrit April 2015