the following patch was just integrated into master:
commit c13ad6c6df709fda1d70743a860a406643620b9e
Author: York Yang <york.yang(a)intel.com>
Date: Thu Apr 23 13:00:20 2015 -0700
driver/intel/fsp: Correct the fastboot data (MRC data) printing length
Fastboot data in Intel FSP project is printed by hexdump32() in dword
length. So the data length needs to be divided by 4 when printing it.
Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159
Signed-off-by: York Yang <york.yang(a)intel.com>
Reviewed-on: http://review.coreboot.org/9976
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/9976 for details.
-gerrit
York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9976
-gerrit
commit 7608ec80ee94d290dc686425251c5acc6dbc9d8f
Author: York Yang <york.yang(a)intel.com>
Date: Thu Apr 23 13:00:20 2015 -0700
driver/intel/fsp: Correct the fastboot data (MRC data) printing length
Fastboot data in Intel FSP project is printed by hexdump32() in dword
length. So the data length needs to be divided by 4 when printing it.
Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159
Signed-off-by: York Yang <york.yang(a)intel.com>
---
src/drivers/intel/fsp1_0/fastboot_cache.c | 2 +-
src/drivers/intel/fsp1_0/fsp_util.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c
old mode 100644
new mode 100755
index bcf39ab..e8651bb
--- a/src/drivers/intel/fsp1_0/fastboot_cache.c
+++ b/src/drivers/intel/fsp1_0/fastboot_cache.c
@@ -230,7 +230,7 @@ void * find_and_set_fastboot_cache(void)
}
printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache);
printk(BIOS_SPEW, "Saved MRC data:\n");
- hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, mrc_cache->mrc_data_size);
+ hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4);
return (void *) mrc_cache->mrc_data;
}
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
old mode 100644
new mode 100755
index a00cb81..ab67147
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -292,7 +292,7 @@ int save_mrc_data(void *hob_start)
mrc_data->mrc_data_size);
printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n");
- hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len);
+ hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4);
return (1);
}
#endif /* CONFIG_ENABLE_MRC_CACHE */
the following patch was just integrated into master:
commit 11004878ce6241f157fa931c2fec60cfbc6b6c71
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Apr 24 18:13:31 2015 +0200
Revert "board-status: Add field for release year"
This reverts commit d555d5a2b5364d2eeb13e2ace00844c7b6321bb9.
It produces too much clutter, and is not particularly useful.
Change-Id: I62268a215a22a5cc76a10cdcfcae86349b466963
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Reviewed-on: http://review.coreboot.org/9990
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/9990 for details.
-gerrit
Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9972
-gerrit
commit a898eec052da1e4a8c296c3688caab0222dea7b8
Author: Dave Frodin <dave.frodin(a)se-eng.com>
Date: Thu Apr 23 06:04:46 2015 -0600
intel: Correct several MMIO related ACPI table settings
1) The Rangeley chipset has the MMIO PCI config space feature
enabled at 0xe0000000-0xefffffff. This is a 256MB space
which covers all of config space. The ACPI table for
this space only defines it as being 64MB. This table
setting has been corrected in the rangeley.asl file.
2) Several of the intel platforms define the region reserved
for PCI memory resources in a location where it overlaps
with the MMIO (MCFG) region.
Using the memory map from mohon_peak as an example:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fbcffff: RAM
4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES
5. 000000007fc00000-000000007fdfffff: RESERVED
6. 00000000e0000000-00000000efffffff: RESERVED
7. 00000000fee00000-00000000fee00fff: RESERVED
8. 0000000100000000-000000017fffffff: RAM
The ACPI table describing the space set aside for PCI memory
(not to be confused with the MMIO config space) is defined
as the region from BMBOUND (the top of DRAM below 4GB) to
a hardcoded value of 0xfebfffff. That region would overlap
the MMIO region at 0xe0000000-0xefffffff. For rangeley
the upper bound of the PCI memory space should be set
to 0xe0000000 - 1.
The MCFG regions for several of the affected chipsets are:
rangeley 0xe0000000-0xefffffff
baytrail 0xe0000000-0xefffffff
haswell 0xf0000000-0xf3ffffff
sandybridge 0xf8000000-0xfbffffff
TEST = intel/mohonpeak and intel/bayleybay.
Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90
Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com>
---
src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl | 8 ++++----
src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl | 2 +-
src/northbridge/intel/haswell/acpi/hostbridge.asl | 6 +++---
src/northbridge/intel/sandybridge/acpi/hostbridge.asl | 6 +++---
src/soc/intel/baytrail/acpi/southcluster.asl | 6 +++---
src/soc/intel/fsp_baytrail/acpi/southcluster.asl | 6 +++---
6 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
index 5cefaeb..4159c30 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
@@ -111,11 +111,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
+ // PCI Memory Region (Top of memory-0xdfffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xe0000000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -131,7 +131,7 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
- Store (BMBD, PMIN) // Memory goes from BMBOUND to 0xfebfffff (PM01 above)
+ Store (BMBD, PMIN) // Memory goes from BMBOUND to 0xdfffffff (PM01 above)
Add(Subtract(PMAX, PMIN), 1, PLEN) // Store Memory Size
Return (MCRS)
diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
index 6a8c2e0..08dba89 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl
@@ -30,7 +30,7 @@ Device (PDRC)
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x04000000)
+ Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000)
})
// Current Resource Settings
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 9bc5549..eb5aa76 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -426,11 +426,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
+ // PCI Memory Region (Top of memory-0xefffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ 0x00000000, 0x00000000, 0xefffffff, 0x00000000,
+ 0xf0000000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 26f7514..aba832c 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -344,11 +344,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfebfffff)
+ // PCI Memory Region (Top of memory-0xf7ffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
- 0xfec00000,,, PM01)
+ 0x00000000, 0x00000000, 0xf7ffffff, 0x00000000,
+ 0xf8000000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 47151a3..1385bd5 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -158,11 +158,11 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfeafffff)
+ // PCI Memory Region (Top of memory-0xdfffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
- 0x00100000,,, PMEM)
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xe0000000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
index 3ee9ee0..12e9daa 100644
--- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl
@@ -157,11 +157,11 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-0xfeafffff)
+ // PCI Memory Region (Top of memory-0xdfffffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
- 0x00100000,,, PMEM)
+ 0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+ 0xe0000000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9986
-gerrit
commit 8f1e78b536672b29ce89054b5abf26dfc74b01d6
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Fri Apr 10 19:23:16 2015 -0700
storm: enable CBMEM console dump
This patch enables on storm the recently introduced 'console buffer
dump on reboot' capability.
BRANCH=none
BUG=chromium:475347
TEST=generated storm image with serial console disabled and both rw
firmware A and B sections corrupted. Programmed the new image on
an SP5 device and rebooted it. Observed the device dump cbmem
console buffer to the serial output, terminating with
VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa
Reboot requested (1008000a)
Saving nvdata
SF: Detected S25FL128S_256K with page size 10000, total 2000000
and the LED ring started flashing indicating recovery mode.
Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8
Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/265295
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/storm/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig
index d2c011b..dfa00cc 100644
--- a/src/mainboard/google/storm/Kconfig
+++ b/src/mainboard/google/storm/Kconfig
@@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_8192
select COMMON_CBFS_SPI_WRAPPER
- select VBOOT_DISABLE_DEV_ON_RECOVERY
+ select CONSOLE_CBMEM_DUMP_TO_UART
select DRIVERS_I2C_WW_RING
select HAVE_HARD_RESET
select MAINBOARD_HAS_BOOTBLOCK_INIT
@@ -34,6 +34,7 @@ config BOARD_SPECIFIC_OPTIONS
select SPI_FLASH
select SPI_FLASH_SPANSION
select SPI_FLASH_STMICRO
+ select VBOOT_DISABLE_DEV_ON_RECOVERY
select VIRTUAL_DEV_SWITCH
select WIPEOUT_SUPPORTED