coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 3fbab29 arch/x86: Guard option table specific rules with HAVE_OPTION_TABLE
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9110 -gerrit commit 3fbab29da8d2e06d2321d8da632f41cedab266ab Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:14:58 2015 +0100 arch/x86: Guard option table specific rules with HAVE_OPTION_TABLE This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Ia22c9fcbf8c629d0eb3f1356f80c4565f117d8b8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/arch/x86/Makefile.inc | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 175a767..e6b4bad 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -29,14 +29,27 @@ subdirs-y += smp DISASSEMBLY=-Wa,--divide +################################################################################ +# i386 specific tools +NVRAMTOOL:=$(objutil)/nvramtool/nvramtool + OPTION_TABLE_H:= ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) + cbfs-files-y += cmos_layout.bin cmos_layout.bin-file = $(obj)/cmos_layout.bin cmos_layout.bin-type = 0x01aa +$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout + @printf " OPTION $(subst $(obj)/,,$(@))\n" + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ + OPTION_TABLE_H:=$(obj)/option_table.h -endif + +$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout + @printf " OPTION $(subst $(obj)/,,$(@))\n" + $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@ +endif # CONFIG_HAVE_OPTION_TABLE stripped_vgabios_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_ID)) cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom @@ -53,18 +66,6 @@ CBFSTOOL_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) -S ".car.data" endif -################################################################################ -# i386 specific tools -NVRAMTOOL:=$(objutil)/nvramtool/nvramtool - -$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@ - -$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" - $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ - ############################################################################### # bootblock

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New patch to review for coreboot: 7dbc264 build system: remove intermediate link step in vboot
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9109 -gerrit commit 7dbc264c61649f5f1225ba03f7b33966e97aadfe Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:08:03 2015 +0100 build system: remove intermediate link step in vboot This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I5405c0ee6bee203281e723feaecaee57fad8f6cb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/vendorcode/google/chromeos/Makefile.inc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 414a416..d8c57fb 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -61,7 +61,6 @@ CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include VBOOT_STUB_ELF = $(obj)/vendorcode/google/chromeos/vbootstub.elf VBOOT_STUB = $(VBOOT_STUB_ELF).rmod -VBOOT_STUB_DOTO = $(VBOOT_STUB_ELF:.elf=.o) # Dependency for the vboot rmodules. Ordering matters. VBOOT_STUB_DEPS += $(obj)/vendorcode/google/chromeos/vboot_wrapper.rmodules_$(ARCH-romstage-y).o @@ -75,11 +74,8 @@ VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/k VBOOT_CFLAGS += -DVBOOT_DEBUG VBOOT_CFLAGS += $(rmodules_$(ARCH-ROMSTAGE-y)-c-ccopts) -$(VBOOT_STUB_DOTO): $(VBOOT_STUB_DEPS) - $(CC_rmodules_$(ARCH-romstage-y)) $(CFLAGS_rmodules_$(ARCH-romstage-y)) -nostdlib -r -o $@ $^ - # Link the vbootstub module with a 64KiB-byte heap. -$(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000,$(ARCH-romstage-y))) +$(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DEPS), 0x10000,$(ARCH-romstage-y))) # Build vboot library without the default includes from coreboot proper. $(VB_LIB):

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New patch to review for coreboot: 958a8b0 build system: rename mips/bootblock.inc to mips/bootblock.S
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9108 -gerrit commit 958a8b02a3c3f1ae0569b6ae4c2e039507378ba0 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:03:22 2015 +0100 build system: rename mips/bootblock.inc to mips/bootblock.S This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I192fa50989b586fd8e967d4c22db56ac9de7a30e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/arch/mips/Makefile.inc | 2 +- src/arch/mips/bootblock.S | 44 ++++++++++++++++++++++++++++++++++++++++++++ src/arch/mips/bootblock.inc | 44 -------------------------------------------- 3 files changed, 45 insertions(+), 45 deletions(-) diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 956f2d5..42c3007 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -44,7 +44,7 @@ bootblock-y += ../../lib/memset.c bootblock_lds = $(src)/arch/mips/bootblock.ld -bootblock_inc += $(src)/arch/mips/bootblock.inc +bootblock_inc += $(src)/arch/mips/bootblock.S bootblock_inc += $(objgenerated)/bootblock.inc # Much of the assembly code is generated by the compiler, and may contain diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S new file mode 100644 index 0000000..dbde803 --- /dev/null +++ b/src/arch/mips/bootblock.S @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +.set noreorder /* Prevent assembler from "optimizing" this code. */ + +.section ".start", "ax", %progbits +.globl _start +_start: + /* Set the stack pointer */ + li $sp, CONFIG_BOOTBLOCK_STACK_TOP + + /* + * Initialise the stack to a known value, used later to check for + * overflow. + */ + li $t0, CONFIG_BOOTBLOCK_STACK_BOTTOM + addi $t1, $sp, -4 + li $t2, 0xdeadbeef +1: sw $t2, 0($t0) + bne $t0, $t1, 1b + addi $t0, $t0, 4 + + /* Run main */ + b main + + /* Should never return from main. */ +2: + b 2b diff --git a/src/arch/mips/bootblock.inc b/src/arch/mips/bootblock.inc deleted file mode 100644 index dbde803..0000000 --- a/src/arch/mips/bootblock.inc +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Imagination Technologies - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -.set noreorder /* Prevent assembler from "optimizing" this code. */ - -.section ".start", "ax", %progbits -.globl _start -_start: - /* Set the stack pointer */ - li $sp, CONFIG_BOOTBLOCK_STACK_TOP - - /* - * Initialise the stack to a known value, used later to check for - * overflow. - */ - li $t0, CONFIG_BOOTBLOCK_STACK_BOTTOM - addi $t1, $sp, -4 - li $t2, 0xdeadbeef -1: sw $t2, 0($t0) - bne $t0, $t1, 1b - addi $t0, $t0, 4 - - /* Run main */ - b main - - /* Should never return from main. */ -2: - b 2b

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New patch to review for coreboot: 4b93b74 build system: normalize linker script file names
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9107 -gerrit commit 4b93b74d4fca947ad36a89ec9fb613629bc3cbed Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 13:50:11 2015 +0100 build system: normalize linker script file names We have .lb, .lds, and .ld in the tree. Go for .ld everywhere. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/arch/riscv/id.ld | 6 +++ src/arch/riscv/id.lds | 6 --- src/arch/x86/Makefile.inc | 12 ++--- src/arch/x86/init/ldscript_failover.lb | 74 --------------------------- src/arch/x86/init/ldscript_failover.ld | 74 +++++++++++++++++++++++++++ src/arch/x86/lib/id.ld | 6 +++ src/arch/x86/lib/id.lds | 6 --- src/cpu/dmp/vortex86ex/Makefile.inc | 4 +- src/cpu/dmp/vortex86ex/biosdata.ld | 84 +++++++++++++++++++++++++++++++ src/cpu/dmp/vortex86ex/biosdata.lds | 84 ------------------------------- src/cpu/dmp/vortex86ex/biosdata_ex.ld | 35 +++++++++++++ src/cpu/dmp/vortex86ex/biosdata_ex.lds | 35 ------------- src/cpu/intel/fit/fit.ld | 6 +++ src/cpu/intel/fit/fit.lds | 6 --- src/cpu/x86/16bit/entry16.ld | 2 + src/cpu/x86/16bit/entry16.lds | 2 - src/cpu/x86/16bit/reset16.ld | 16 ++++++ src/cpu/x86/16bit/reset16.lds | 16 ------ src/cpu/x86/32bit/entry32.ld | 1 + src/cpu/x86/32bit/entry32.lds | 1 - src/northbridge/via/vx800/Makefile.inc | 2 +- src/northbridge/via/vx800/romstrap.ld | 26 ++++++++++ src/northbridge/via/vx800/romstrap.lds | 26 ---------- src/northbridge/via/vx900/Makefile.inc | 2 +- src/northbridge/via/vx900/romstrap.ld | 27 ++++++++++ src/northbridge/via/vx900/romstrap.lds | 27 ---------- src/southbridge/nvidia/ck804/Makefile.inc | 2 +- src/southbridge/nvidia/ck804/nic.c | 2 +- src/southbridge/nvidia/ck804/romstrap.ld | 26 ++++++++++ src/southbridge/nvidia/ck804/romstrap.lds | 26 ---------- src/southbridge/nvidia/mcp55/Makefile.inc | 2 +- src/southbridge/nvidia/mcp55/nic.c | 2 +- src/southbridge/nvidia/mcp55/romstrap.ld | 27 ++++++++++ src/southbridge/nvidia/mcp55/romstrap.lds | 27 ---------- src/southbridge/sis/sis966/Makefile.inc | 2 +- src/southbridge/sis/sis966/romstrap.ld | 27 ++++++++++ src/southbridge/sis/sis966/romstrap.lds | 27 ---------- src/southbridge/via/k8t890/Makefile.inc | 2 +- src/southbridge/via/k8t890/romstrap.ld | 29 +++++++++++ src/southbridge/via/k8t890/romstrap.lds | 29 ----------- 40 files changed, 408 insertions(+), 408 deletions(-) diff --git a/src/arch/riscv/id.ld b/src/arch/riscv/id.ld new file mode 100644 index 0000000..cfd091d --- /dev/null +++ b/src/arch/riscv/id.ld @@ -0,0 +1,6 @@ +SECTIONS { + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + .id (.): { + *(.id) + } +} diff --git a/src/arch/riscv/id.lds b/src/arch/riscv/id.lds deleted file mode 100644 index cfd091d..0000000 --- a/src/arch/riscv/id.lds +++ /dev/null @@ -1,6 +0,0 @@ -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - *(.id) - } -} diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5d49abc..175a767 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -72,13 +72,13 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) -bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb -bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds -bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds -bootblock_lds += $(src)/arch/x86/lib/id.lds +bootblock_lds = $(src)/arch/x86/init/ldscript_failover.ld +bootblock_lds += $(src)/cpu/x86/16bit/entry16.ld +bootblock_lds += $(src)/cpu/x86/16bit/reset16.ld +bootblock_lds += $(src)/arch/x86/lib/id.ld bootblock_lds += $(chipset_bootblock_lds) ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_lds += $(src)/cpu/intel/fit/fit.lds +bootblock_lds += $(src)/cpu/intel/fit/fit.ld endif bootblock_inc = $(src)/arch/x86/init/prologue.inc @@ -141,7 +141,7 @@ crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = ldscripts += $(src)/arch/x86/init/romstage.ld crt0s += $(src)/cpu/x86/32bit/entry32.inc -ldscripts += $(src)/cpu/x86/32bit/entry32.lds +ldscripts += $(src)/cpu/x86/32bit/entry32.ld crt0s += $(src)/cpu/x86/fpu_enable.inc ifeq ($(CONFIG_SSE),y) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb deleted file mode 100644 index 318f429..0000000 --- a/src/arch/x86/init/ldscript_failover.lb +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) - -MEMORY { - rom : ORIGIN = 0xffff0000, LENGTH = 64K -} - -TARGET(binary) -SECTIONS -{ - /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. Align .rom to next 4 byte - * boundary anyway, so no pad byte appears between _rom and _start. - */ - .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); - ROMLOC = .; - } >rom = 0xff - - /* This section might be better named .setup */ - .rom ROMLOC : { - _rom = .; - ap_sipi_vector = .; - *(.rom.text); - *(.rom.data); - *(.rom.data.*); - *(.rodata.*); - _erom = .; - } >rom = 0xff - - /* Allocation reserves extra 16 bytes here. Alignment requirements - * may cause the total size of a section to change when the start - * address gets applied. - */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); - - /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), - "Bad SIPI vector alignment"); - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), - "Address mismatch on AP_SIPI_VECTOR"); - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.iplt) - *(.rel.*) - *(.igot.*) - } -} diff --git a/src/arch/x86/init/ldscript_failover.ld b/src/arch/x86/init/ldscript_failover.ld new file mode 100644 index 0000000..318f429 --- /dev/null +++ b/src/arch/x86/init/ldscript_failover.ld @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +MEMORY { + rom : ORIGIN = 0xffff0000, LENGTH = 64K +} + +TARGET(binary) +SECTIONS +{ + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. Align .rom to next 4 byte + * boundary anyway, so no pad byte appears between _rom and _start. + */ + .bogus ROMLOC_MIN : { + . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + ROMLOC = .; + } >rom = 0xff + + /* This section might be better named .setup */ + .rom ROMLOC : { + _rom = .; + ap_sipi_vector = .; + *(.rom.text); + *(.rom.data); + *(.rom.data.*); + *(.rodata.*); + _erom = .; + } >rom = 0xff + + /* Allocation reserves extra 16 bytes here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || ((ap_sipi_vector & 0x0fff) == 0x0), + "Bad SIPI vector alignment"); + _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), + "Address mismatch on AP_SIPI_VECTOR"); + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.iplt) + *(.rel.*) + *(.igot.*) + } +} diff --git a/src/arch/x86/lib/id.ld b/src/arch/x86/lib/id.ld new file mode 100644 index 0000000..cfd091d --- /dev/null +++ b/src/arch/x86/lib/id.ld @@ -0,0 +1,6 @@ +SECTIONS { + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + .id (.): { + *(.id) + } +} diff --git a/src/arch/x86/lib/id.lds b/src/arch/x86/lib/id.lds deleted file mode 100644 index cfd091d..0000000 --- a/src/arch/x86/lib/id.lds +++ /dev/null @@ -1,6 +0,0 @@ -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - *(.id) - } -} diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index ff0b58c..c68bf9e 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -25,7 +25,7 @@ subdirs-y += ../../x86/smm chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc -chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.lds -chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.lds +chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.ld +chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.ld ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/cpu/dmp/vortex86ex/biosdata.ld b/src/cpu/dmp/vortex86ex/biosdata.ld new file mode 100644 index 0000000..b525b2a --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata.ld @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +SECTIONS { + + /* Vortex86 ROM fixed data areas used range is too big, we need + * to move bootblock from default address to another place, + * otherwise .dmp_frontdoor section can't be included. + * Address before ..fbc00 is available. + */ + ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) - + (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); + + . = 0xffffbc00; + .dmp_reserved (.): { + *(.dmp_reserved) + } + + . = 0xffffc000; + .dmp_kbd_fw_part2 (.): { + *(.dmp_kbd_fw_part2) + } + + . = 0xffffd000; + .dmp_mtbf_low_cnt (.): { + *(.dmp_mtbf_low_cnt) + } + + . = 0xffffe000; + .dmp_kbd_fw_part1 (.): { + *(.dmp_kbd_fw_part1) + } + + . = 0xfffff000; + .dmp_spi_flash_disk_driver (.): { + *(.dmp_spi_flash_disk_driver) + } + + . = 0xfffff800; + .dmp_frontdoor (.): { + *(.dmp_frontdoor) + } + + . = 0xfffffe00; + .dmp_isoinfo (.): { + *(.dmp_isoinfo) + } + + . = 0xffffffa0; + .dmp_isodata_checksum (.): { + *(.dmp_isodata_checksum) + } + + . = 0xffffffb0; + .dmp_mac (.): { + *(.dmp_mac) + } + + . = 0xffffffb8; + .dmp_mtbf_limit (.): { + *(.dmp_mtbf_limit) + } + + . = 0xffffffc0; + .dmp_isodata (.): { + *(.dmp_isodata) + } +} diff --git a/src/cpu/dmp/vortex86ex/biosdata.lds b/src/cpu/dmp/vortex86ex/biosdata.lds deleted file mode 100644 index b525b2a..0000000 --- a/src/cpu/dmp/vortex86ex/biosdata.lds +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -SECTIONS { - - /* Vortex86 ROM fixed data areas used range is too big, we need - * to move bootblock from default address to another place, - * otherwise .dmp_frontdoor section can't be included. - * Address before ..fbc00 is available. - */ - ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); - - . = 0xffffbc00; - .dmp_reserved (.): { - *(.dmp_reserved) - } - - . = 0xffffc000; - .dmp_kbd_fw_part2 (.): { - *(.dmp_kbd_fw_part2) - } - - . = 0xffffd000; - .dmp_mtbf_low_cnt (.): { - *(.dmp_mtbf_low_cnt) - } - - . = 0xffffe000; - .dmp_kbd_fw_part1 (.): { - *(.dmp_kbd_fw_part1) - } - - . = 0xfffff000; - .dmp_spi_flash_disk_driver (.): { - *(.dmp_spi_flash_disk_driver) - } - - . = 0xfffff800; - .dmp_frontdoor (.): { - *(.dmp_frontdoor) - } - - . = 0xfffffe00; - .dmp_isoinfo (.): { - *(.dmp_isoinfo) - } - - . = 0xffffffa0; - .dmp_isodata_checksum (.): { - *(.dmp_isodata_checksum) - } - - . = 0xffffffb0; - .dmp_mac (.): { - *(.dmp_mac) - } - - . = 0xffffffb8; - .dmp_mtbf_limit (.): { - *(.dmp_mtbf_limit) - } - - . = 0xffffffc0; - .dmp_isodata (.): { - *(.dmp_isodata) - } -} diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.ld b/src/cpu/dmp/vortex86ex/biosdata_ex.ld new file mode 100644 index 0000000..d711648 --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.ld @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +SECTIONS { + . = 0xfffffd00; + .a9123_crossbar_config (.): { + *(.a9123_crossbar_config) + } + + . = 0xffffffb6; + .a9123_strap_1 (.): { + *(.a9123_strap_1) + } + + . = 0xffffffbb; + .a9123_strap_2 (.): { + *(.a9123_strap_2) + } +} diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.lds b/src/cpu/dmp/vortex86ex/biosdata_ex.lds deleted file mode 100644 index d711648..0000000 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.lds +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -SECTIONS { - . = 0xfffffd00; - .a9123_crossbar_config (.): { - *(.a9123_crossbar_config) - } - - . = 0xffffffb6; - .a9123_strap_1 (.): { - *(.a9123_strap_1) - } - - . = 0xffffffbb; - .a9123_strap_2 (.): { - *(.a9123_strap_2) - } -} diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld new file mode 100644 index 0000000..9ccfe82 --- /dev/null +++ b/src/cpu/intel/fit/fit.ld @@ -0,0 +1,6 @@ +SECTIONS { + . = 0xffffffc0; + .fit_pointer (.): { + *(.fit_pointer) + } +} diff --git a/src/cpu/intel/fit/fit.lds b/src/cpu/intel/fit/fit.lds deleted file mode 100644 index 9ccfe82..0000000 --- a/src/cpu/intel/fit/fit.lds +++ /dev/null @@ -1,6 +0,0 @@ -SECTIONS { - . = 0xffffffc0; - .fit_pointer (.): { - *(.fit_pointer) - } -} diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld new file mode 100644 index 0000000..112d429 --- /dev/null +++ b/src/cpu/x86/16bit/entry16.ld @@ -0,0 +1,2 @@ + gdtptr16_offset = gdtptr16 & 0xffff; + nullidt_offset = nullidt & 0xffff; diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds deleted file mode 100644 index 112d429..0000000 --- a/src/cpu/x86/16bit/entry16.lds +++ /dev/null @@ -1,2 +0,0 @@ - gdtptr16_offset = gdtptr16 & 0xffff; - nullidt_offset = nullidt & 0xffff; diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld new file mode 100644 index 0000000..a31a580 --- /dev/null +++ b/src/cpu/x86/16bit/reset16.ld @@ -0,0 +1,16 @@ +/* + * _ROMTOP : The top of the rom used where we + * need to put the reset vector. + */ + +SECTIONS { + /* Trigger an error if I have an unuseable start address */ + _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report."); + _ROMTOP = 0xfffffff0; + . = _ROMTOP; + .reset . : { + *(.reset) + . = 15 ; + BYTE(0x00); + } +} diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds deleted file mode 100644 index a31a580..0000000 --- a/src/cpu/x86/16bit/reset16.lds +++ /dev/null @@ -1,16 +0,0 @@ -/* - * _ROMTOP : The top of the rom used where we - * need to put the reset vector. - */ - -SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report."); - _ROMTOP = 0xfffffff0; - . = _ROMTOP; - .reset . : { - *(.reset) - . = 15 ; - BYTE(0x00); - } -} diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld new file mode 100644 index 0000000..471b5f7 --- /dev/null +++ b/src/cpu/x86/32bit/entry32.ld @@ -0,0 +1 @@ +ENTRY(protected_start) diff --git a/src/cpu/x86/32bit/entry32.lds b/src/cpu/x86/32bit/entry32.lds deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.lds +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 39ebdbd..1963880 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -24,4 +24,4 @@ ramstage-y += lpc.c ramstage-y += ide.c chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc -chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.lds +chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.ld diff --git a/src/northbridge/via/vx800/romstrap.ld b/src/northbridge/via/vx800/romstrap.ld new file mode 100644 index 0000000..8aa570f --- /dev/null +++ b/src/northbridge/via/vx800/romstrap.ld @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +SECTIONS { + . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1; + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/northbridge/via/vx800/romstrap.lds b/src/northbridge/via/vx800/romstrap.lds deleted file mode 100644 index 8aa570f..0000000 --- a/src/northbridge/via/vx800/romstrap.lds +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -SECTIONS { - . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - *(.romstrap) - } -} diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 15fd859..85282dd 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -45,4 +45,4 @@ ramstage-y += ./../../../drivers/pc80/vga/vga_io.c chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc -chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds +chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.ld diff --git a/src/northbridge/via/vx900/romstrap.ld b/src/northbridge/via/vx900/romstrap.ld new file mode 100644 index 0000000..fc63c05 --- /dev/null +++ b/src/northbridge/via/vx900/romstrap.ld @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/> + */ + +SECTIONS { + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds deleted file mode 100644 index fc63c05..0000000 --- a/src/northbridge/via/vx900/romstrap.lds +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) - * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/> - */ - -SECTIONS { - . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); - .romstrap (.): { - *(.romstrap) - } -} diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index db145d0..dacfc9c 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -20,4 +20,4 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.ld diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index b827dcf..1207a95 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -90,7 +90,7 @@ static void nic_init(struct device *dev) /* If that is invalid we will read that from romstrap. */ if (!eeprom_valid) { u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */ + mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */ mac_l = read32(mac_pos) + nic_index; mac_h = read32(mac_pos + 1); } diff --git a/src/southbridge/nvidia/ck804/romstrap.ld b/src/southbridge/nvidia/ck804/romstrap.ld new file mode 100644 index 0000000..4d7996f --- /dev/null +++ b/src/southbridge/nvidia/ck804/romstrap.ld @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +SECTIONS { + . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.lds deleted file mode 100644 index 4d7996f..0000000 --- a/src/southbridge/nvidia/ck804/romstrap.lds +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - *(.romstrap) - } -} diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 03a34eb..b4dc460 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -19,4 +19,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.ld diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index 136d060..d8f691a 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -162,7 +162,7 @@ static void nic_init(struct device *dev) // if that is invalid we will read that from romstrap if(!eeprom_valid) { u32 *mac_pos; - mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds + mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld mac_l = read32(mac_pos) + nic_index; // overflow? mac_h = read32(mac_pos + 1); diff --git a/src/southbridge/nvidia/mcp55/romstrap.ld b/src/southbridge/nvidia/mcp55/romstrap.ld new file mode 100644 index 0000000..784e7d5 --- /dev/null +++ b/src/southbridge/nvidia/mcp55/romstrap.ld @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +SECTIONS { + . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.lds deleted file mode 100644 index 784e7d5..0000000 --- a/src/southbridge/nvidia/mcp55/romstrap.lds +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - *(.romstrap) - } -} diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 1a9ea65..5c69622 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -14,4 +14,4 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.ld diff --git a/src/southbridge/sis/sis966/romstrap.ld b/src/southbridge/sis/sis966/romstrap.ld new file mode 100644 index 0000000..784e7d5 --- /dev/null +++ b/src/southbridge/sis/sis966/romstrap.ld @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +SECTIONS { + . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/southbridge/sis/sis966/romstrap.lds b/src/southbridge/sis/sis966/romstrap.lds deleted file mode 100644 index 784e7d5..0000000 --- a/src/southbridge/sis/sis966/romstrap.lds +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -SECTIONS { - . = (0xffffffff - 0x10) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - *(.romstrap) - } -} diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 6d9407d..1c5ff3f 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -9,4 +9,4 @@ ramstage-y += error.c ramstage-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc -chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds +chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.ld diff --git a/src/southbridge/via/k8t890/romstrap.ld b/src/southbridge/via/k8t890/romstrap.ld new file mode 100644 index 0000000..235769d --- /dev/null +++ b/src/southbridge/via/k8t890/romstrap.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek(a)assembler.cz>. */ + +SECTIONS { + . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1; + .romstrap (.): { + *(.romstrap) + } +} diff --git a/src/southbridge/via/k8t890/romstrap.lds b/src/southbridge/via/k8t890/romstrap.lds deleted file mode 100644 index 235769d..0000000 --- a/src/southbridge/via/k8t890/romstrap.lds +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Modified for K8T890 ROM strap by Rudolf Marek <r.marek(a)assembler.cz>. */ - -SECTIONS { - . = (0xffffffff - 0x2c) - (__romstrap_end - __romstrap_start) + 1; - .romstrap (.): { - *(.romstrap) - } -}

1 0

Patch set updated for coreboot: e2659c9 arm64: provide entry points for BSP and non-BSP
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9090 -gerrit commit e2659c9f0bfacb49a30005b7d2b6fd636eae14e5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 18 13:48:49 2014 -0500 arm64: provide entry points for BSP and non-BSP It's helpful to differentiate the startup paths for the BSP and the non-BSP. Therefore have c_entry be an 2 element array of function pointers. The non-BSP paths have an entry point one instruction after stage/module entry. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218844 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/c_entry.c | 21 +++++++++------------ src/arch/arm64/include/arch/stages.h | 18 +++++++++++++++--- src/arch/arm64/stage_entry.S | 32 +++++++++++++++++++++++++++----- 3 files changed, 51 insertions(+), 20 deletions(-) diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index f4a9848..5e3dfe8 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -24,13 +24,6 @@ #include <arch/stages.h> #include "cpu-internal.h" -/* - * This variable holds entry point for CPUs starting up. Before the other - * CPUs are brought up this value will change to provide the secondary - * code path. - */ -void (*c_entry)(void) = &arm64_init; - void __attribute__((weak)) arm64_soc_init(void) { /* Default weak implementation does nothing. */ @@ -54,7 +47,7 @@ static void seed_stack(void) *slot++ = 0xdeadbeefdeadbeefULL; } -void arm64_init(void) +static void arm64_init(void) { cpu_set_bsp(); seed_stack(); @@ -71,11 +64,15 @@ static void secondary_cpu_start(void) arch_secondary_cpu_init(); } +/* + * This variable holds entry point for CPUs starting up. The first + * element is the BSP path, and the second is the non-BSP path. + */ +void (*c_entry[2])(void) = { &arm64_init, &secondary_cpu_start }; + extern void arm64_cpu_startup(void); + void *prepare_secondary_cpu_startup(void) { - c_entry = &secondary_cpu_start; - dcache_clean_invalidate_by_mva(c_entry, sizeof(c_entry)); - - return &arm64_cpu_startup; + return secondary_entry_point(&arm64_cpu_startup); } diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index 9771492..fd633e4 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -20,18 +20,30 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H +#include <stdint.h> + extern void main(void); void stage_entry(void); void stage_exit(void *); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); -/* C entry point for all arm64 stages. */ -void arm64_init(void); - /* This function is called upon initial entry of each stage. It is called prior * to main(). That means all of the common infrastructure will most likely not * be available to be used (such as console). */ void arm64_soc_init(void); +/* + * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided + * a pointer the correct non-BSP entry point will be returned. The + * first instruction is for BSP and the 2nd is for non-BSP. Instructions + * are all 32-bit on arm64. + */ +static inline void *secondary_entry_point(void *e) +{ + uintptr_t nonbsp = (uintptr_t)e; + + return (void *)(nonbsp + sizeof(uint32_t)); +} + #endif diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 6b8ca7b..5a5ddab 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -105,6 +105,8 @@ ENTRY(arm64_c_environment) /* Get entry point by dereferencing c_entry. */ ldr x1, 1f + /* Retrieve entry in c_entry array using x26 as the index. */ + adds x1, x1, x26, lsl #3 ldr x1, [x1] /* Move back the arguments from x25 to x0 */ mov x0, x25 @@ -114,14 +116,28 @@ ENTRY(arm64_c_environment) .quad c_entry ENDPROC(arm64_c_environment) +/* The first 2 instructions are for BSP and secondary CPUs, + * respectively. x26 holds the index into c_entry array. */ +.macro split_bsp_path + b 2000f + b 2001f + 2000: + mov x26, #0 + b 2002f + 2001: + mov x26, #1 + 2002: +.endm + ENTRY(__rmodule_entry) + split_bsp_path /* Save the arguments to secmon in x25 */ - mov x25, x0 - b arm64_c_environment + mov x25, x0 + b arm64_c_environment ENDPROC(__rmodule_entry) -CPU_RESET_ENTRY(arm64_cpu_startup) - read_current x0, sctlr +ENTRY(_arm64_cpu_startup) + read_current x0, sctlr bic x0, x0, #(1 << 25) /* Little Endian */ bic x0, x0, #(1 << 19) /* XN not enforced */ bic x0, x0, #(1 << 12) /* Disable Instruction Cache */ @@ -129,8 +145,14 @@ CPU_RESET_ENTRY(arm64_cpu_startup) write_current sctlr, x0, x1 isb b arm64_c_environment +ENDPROC(_arm64_cpu_startup) + +CPU_RESET_ENTRY(arm64_cpu_startup) + split_bsp_path + b _arm64_cpu_startup ENDPROC(arm64_cpu_startup) ENTRY(stage_entry) - b arm64_cpu_startup + split_bsp_path + b _arm64_cpu_startup ENDPROC(stage_entry)

1 0

Patch set updated for coreboot: 37ed3c0 arm64: initialize secmon environment
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9091 -gerrit commit 37ed3c069e0607916e9ca9bedeef43fa3f9e7314 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 18 14:23:59 2014 -0500 arm64: initialize secmon environment The exception vectors were not reinitialized in secmon yet. Add that as well as the split BSP vs non-BSP path. In doing so bring in the cpu.c semantics for determining bsp at runtime. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also noted only one CPU printing messages. Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32 Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218845 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/secmon/Makefile.inc | 2 ++ src/arch/arm64/armv8/secmon/secmon_init.c | 45 ++++++++++++++++++++----------- src/arch/arm64/armv8/secmon_loader.c | 16 ++++++++--- 3 files changed, 43 insertions(+), 20 deletions(-) diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc index b140941..5dadfa9 100644 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ b/src/arch/arm64/armv8/secmon/Makefile.inc @@ -32,6 +32,8 @@ secmon-c-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kc secmon-S-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__ secmon-y += secmon_init.c +secmon-y += ../exception.c +secmon-y += ../../cpu.c secmon-y += ../../transition_asm.S ../../transition.c ramstage-srcs += $(SECMON_SRC) diff --git a/src/arch/arm64/armv8/secmon/secmon_init.c b/src/arch/arm64/armv8/secmon/secmon_init.c index e8bdd82..660d6d4 100644 --- a/src/arch/arm64/armv8/secmon/secmon_init.c +++ b/src/arch/arm64/armv8/secmon/secmon_init.c @@ -21,6 +21,7 @@ #include <arch/barrier.h> #include <arch/io.h> +#include <arch/exception.h> #include <arch/lib_helpers.h> #include <arch/secmon.h> #include <arch/transition.h> @@ -28,14 +29,15 @@ #include <rmodule.h> #include <stddef.h> -static void secmon_wait(void) +static void cpu_init(int bsp) { - /* - * TODO(furquan): This should be a point of no-return. Once we have PSCI - * support we need to respond to kernel calls - */ - while (1) - wfe(); + struct cpu_info *ci = cpu_info(); + + ci->id = smp_processor_id(); + cpu_mark_online(ci); + + if (bsp) + cpu_set_bsp(); } static void secmon_el3_init(void) @@ -52,12 +54,12 @@ static void secmon_el3_init(void) isb(); } -static void secmon_init(void *arg) +static void secmon_init(struct secmon_params *params, int bsp) { struct exc_state exc_state; - struct secmon_params *params = arg; - printk(BIOS_DEBUG, "ARM64: secmon in %s\n", __func__); + exception_hwinit(); + cpu_init(bsp); secmon_el3_init(); @@ -66,18 +68,29 @@ static void secmon_init(void *arg) * 1) If yes, we make an EL2 transition to that entry point * 2) If no, we just wait */ - if (params == NULL) { - secmon_wait(); + if (params != NULL) { + memset(&exc_state, 0, sizeof(exc_state)); + exc_state.elx.spsr = + get_eret_el(params->elx_el, params->elx_mode); + + transition_with_entry(params->entry, params->arg, &exc_state); } - memset(&exc_state, 0, sizeof(exc_state)); - exc_state.elx.spsr = get_eret_el(params->elx_el, params->elx_mode); + arch_cpu_wait_for_action(); +} - transition_with_entry(params->entry, params->arg, &exc_state); +static void secmon_init_bsp(void *arg) +{ + secmon_init(arg, 1); +} + +static void secmon_init_nonbsp(void *arg) +{ + secmon_init(arg, 0); } /* * This variable holds entry point for secmon init code. Once the stacks are * setup by the stage_entry.S, it jumps to c_entry. */ -void (*c_entry)(void*) = &secmon_init; +void (*c_entry[2])(void*) = { &secmon_init_bsp, &secmon_init_nonbsp }; diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c index 4d83764..e571b51 100644 --- a/src/arch/arm64/armv8/secmon_loader.c +++ b/src/arch/arm64/armv8/secmon_loader.c @@ -25,6 +25,7 @@ #include <arch/lib_helpers.h> #include <arch/secmon.h> #include <arch/spintable.h> +#include <arch/stages.h> #include <console/console.h> #include <rmodule.h> #include <string.h> @@ -85,15 +86,22 @@ struct secmon_runit { static void secmon_start(void *arg) { uint32_t scr; + secmon_entry_t entry; struct secmon_params *p = NULL; struct secmon_runit *r = arg; + entry = r->entry; + if (cpu_is_bsp()) p = &r->bsp_params; - else if (r->secondary_params.entry != NULL) - p = &r->secondary_params; + else { + entry = secondary_entry_point(entry); + if (r->secondary_params.entry != NULL) + p = &r->secondary_params; + } - printk(BIOS_DEBUG, "CPU%x entering secure monitor.\n", cpu_info()->id); + printk(BIOS_DEBUG, "CPU%x entering secure monitor %p.\n", + cpu_info()->id, entry); /* We want to enforce the following policies: * NS bit is set for lower EL @@ -102,7 +110,7 @@ static void secmon_start(void *arg) scr |= SCR_NS; raw_write_scr_el3(scr); - r->entry(p); + entry(p); } void secmon_run(void (*entry)(void *), void *cb_tables)

1 0

Patch set updated for coreboot: d0254d5 arm64: exception handler registration
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9088 -gerrit commit d0254d5c92fbd27701220c97eca58028a2b92c37 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 16 22:23:57 2014 -0500 arm64: exception handler registration In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/exception.c | 191 +++++++++++++++++--------- src/arch/arm64/include/arch/transition.h | 18 +++ src/arch/arm64/include/armv8/arch/exception.h | 31 +++++ src/arch/arm64/transition_asm.S | 32 ++--- 4 files changed, 189 insertions(+), 83 deletions(-) diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 0aef0e5..a633e3a 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -29,56 +29,30 @@ #include <stdint.h> #include <types.h> +#include <arch/barrier.h> #include <arch/cache.h> #include <arch/exception.h> #include <arch/transition.h> #include <console/console.h> #include <arch/lib_helpers.h> -static unsigned int test_exc; - -struct exception_handler_info -{ - const char *name; -}; - -enum { - EXC_SYNC_SP0 = 0, - EXC_IRQ_SP0, - EXC_FIQ_SP0, - EXC_SERROR_SP0, - EXC_SYNC_SP3, - EXC_IRQ_SP3, - EXC_FIQ_SP3, - EXC_SERROR_SP3, - EXC_SYNC_ELX_64, - EXC_IRQ_ELX_64, - EXC_FIQ_ELX_64, - EXC_SERROR_ELX_64, - EXC_SYNC_ELX_32, - EXC_IRQ_ELX_32, - EXC_FIQ_ELX_32, - EXC_SERROR_ELX_32, - EXC_COUNT -}; - -static struct exception_handler_info exceptions[EXC_COUNT] = { - [EXC_SYNC_SP0] = { "_sync_sp_el0" }, - [EXC_IRQ_SP0] = { "_irq_sp_el0" }, - [EXC_FIQ_SP0] = { "_fiq_sp_el0" }, - [EXC_SERROR_SP0] = {"_serror_sp_el0"}, - [EXC_SYNC_SP3] = { "_sync_sp_el3" }, - [EXC_IRQ_SP3] = { "_irq_sp_el3" }, - [EXC_FIQ_SP3] = { "_fiq_sp_el3" }, - [EXC_SERROR_SP3] = {"_serror_sp_el3"}, - [EXC_SYNC_ELX_64] = { "_sync_elx_64" }, - [EXC_IRQ_ELX_64] = { "_irq_elx_64" }, - [EXC_FIQ_ELX_64] = { "_fiq_elx_64" }, - [EXC_SERROR_ELX_64] = {"_serror_elx_64"}, - [EXC_SYNC_ELX_32] = { "_sync_elx_32" }, - [EXC_IRQ_ELX_32] = { "_irq_elx_32" }, - [EXC_FIQ_ELX_32] = { "_fiq_elx_32" }, - [EXC_SERROR_ELX_32] = {"_serror_elx_32"}, +static const char *exception_names[NUM_EXC_VIDS] = { + [EXC_VID_CUR_SP_EL0_SYNC] = "_sync_sp_el0", + [EXC_VID_CUR_SP_EL0_IRQ] = "_irq_sp_el0", + [EXC_VID_CUR_SP_EL0_FIRQ] = "_fiq_sp_el0", + [EXC_VID_CUR_SP_EL0_SERR] = "_serror_sp_el0", + [EXC_VID_CUR_SP_ELX_SYNC] = "_sync_sp_el3", + [EXC_VID_CUR_SP_ELX_IRQ] = "_irq_sp_el3", + [EXC_VID_CUR_SP_ELX_FIQ] = "_fiq_sp_el3", + [EXC_VID_CUR_SP_ELX_SERR] = "_serror_sp_el3", + [EXC_VID_LOW64_SYNC] = "_sync_elx_64", + [EXC_VID_LOW64_IRQ] = "_irq_elx_64", + [EXC_VID_LOW64_FIQ] = "_fiq_elx_64", + [EXC_VID_LOW64_SERR] = "_serror_elx_64", + [EXC_VID_LOW32_SYNC] = "_sync_elx_32", + [EXC_VID_LOW32_IRQ] = "_irq_elx_32", + [EXC_VID_LOW32_FIQ] = "_fiq_elx_32", + [EXC_VID_LOW32_SERR] = "_serror_elx_32" }; static void print_regs(struct exc_state *exc_state) @@ -98,39 +72,122 @@ static void print_regs(struct exc_state *exc_state) printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, regs->x[i]); } -void exc_dispatch(struct exc_state *exc_state, uint64_t idx) + +static struct exception_handler *handlers[NUM_EXC_VIDS]; + + +int exception_handler_register(uint64_t vid, struct exception_handler *h) { - if (idx >= EXC_COUNT) { - printk(BIOS_DEBUG, "Bad exception index %lx.\n", - (unsigned long)idx); - } else { - struct exception_handler_info *info = &exceptions[idx]; - - if (info->name) - printk(BIOS_DEBUG, "exception %s\n", info->name); - else - printk(BIOS_DEBUG, "exception _not_used.\n"); + if (vid >= NUM_EXC_VIDS) + return -1; + + /* Just place at head of queue. */ + h->next = handlers[vid]; + store_release(&handlers[vid], h); + + return 0; +} + +int exception_handler_unregister(uint64_t vid, struct exception_handler *h) +{ + struct exception_handler *cur; + struct exception_handler **prev; + + if (vid >= NUM_EXC_VIDS) + return -1; + + prev = &handlers[vid]; + + for (cur = handlers[vid]; cur != NULL; cur = cur->next) { + if (cur != h) + continue; + /* Update previous pointer. */ + store_release(prev, cur->next); + return 0; } - print_regs(exc_state); - if (test_exc) { - exc_state->elx.elr += 4; - raw_write_elr_current(exc_state->elx.elr); - test_exc = 0; - printk(BIOS_DEBUG, "new ELR = 0x%016llx\n", exc_state->elx.elr); - } else - die("exception"); + /* Not found */ + return -1; +} + +static void print_exception_info(struct exc_state *state, uint64_t idx) +{ + if (idx < NUM_EXC_VIDS) + printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]); + + print_regs(state); +} - exc_exit(&exc_state->regs); +static void print_exception_and_die(struct exc_state *state, uint64_t idx) +{ + print_exception_info(state, idx); + die("exception death"); +} + + +static int handle_exception(struct exc_state *state, uint64_t idx) +{ + int ret = EXC_RET_ABORT; + + struct exception_handler *h; + + for (h = handlers[idx]; h != NULL; h = h->next) { + int hret; + + hret = h->handler(state, idx); + + if (hret > ret) + ret = hret; + } + + return ret; +} + +void exc_dispatch(struct exc_state *state, uint64_t idx) +{ + int ret; + + if (idx >= NUM_EXC_VIDS) { + printk(BIOS_DEBUG, "Bad exception index %x.\n", (int)idx); + print_exception_and_die(state, idx); + } + + ret = handle_exception(state, idx); + + if (ret == EXC_RET_ABORT) + print_exception_and_die(state, idx); + + if (ret == EXC_RET_IGNORED || ret == EXC_RET_HANDLED_DUMP_STATE) + print_exception_info(state, idx); + + exc_exit(&state->regs); +} + + +static int test_exception_handler(struct exc_state *state, uint64_t vector_id) +{ + /* Update instruction pointer to next instrution. */ + state->elx.elr += sizeof(uint32_t); + raw_write_elr_current(state->elx.elr); + return EXC_RET_HANDLED; } static uint64_t test_exception(void) { - uint64_t *a = (uint64_t *)0xfffffffff0000000ULL; + struct exception_handler sync_elx; + struct exception_handler sync_el0; + unsigned long long *a = (void *)0xffffffff00000000ULL; + + sync_elx.handler = &test_exception_handler; + sync_el0.handler = &test_exception_handler; + + exception_handler_register(EXC_VID_CUR_SP_ELX_SYNC, &sync_elx); + exception_handler_register(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0); - test_exc = 1; + force_read(*a); - printk(BIOS_DEBUG, "%llx\n", *a); + exception_handler_unregister(EXC_VID_CUR_SP_ELX_SYNC, &sync_elx); + exception_handler_unregister(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0); return 0; } diff --git a/src/arch/arm64/include/arch/transition.h b/src/arch/arm64/include/arch/transition.h index e8ded5f..9da6b36 100644 --- a/src/arch/arm64/include/arch/transition.h +++ b/src/arch/arm64/include/arch/transition.h @@ -42,6 +42,24 @@ #define STACK_POP_BYTES 16 #define STACK_PUSH_BYTES -16 +#define EXC_VID_CUR_SP_EL0_SYNC 0 +#define EXC_VID_CUR_SP_EL0_IRQ 1 +#define EXC_VID_CUR_SP_EL0_FIRQ 2 +#define EXC_VID_CUR_SP_EL0_SERR 3 +#define EXC_VID_CUR_SP_ELX_SYNC 4 +#define EXC_VID_CUR_SP_ELX_IRQ 5 +#define EXC_VID_CUR_SP_ELX_FIQ 6 +#define EXC_VID_CUR_SP_ELX_SERR 7 +#define EXC_VID_LOW64_SYNC 8 +#define EXC_VID_LOW64_IRQ 9 +#define EXC_VID_LOW64_FIQ 10 +#define EXC_VID_LOW64_SERR 11 +#define EXC_VID_LOW32_SYNC 12 +#define EXC_VID_LOW32_IRQ 13 +#define EXC_VID_LOW32_FIQ 14 +#define EXC_VID_LOW32_SERR 15 +#define NUM_EXC_VIDS 16 + #ifndef __ASSEMBLY__ #include <stdint.h> diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index 11ffcb6..49ea747 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -30,8 +30,39 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H +#include <arch/transition.h> + /* Initialize the exception handling on the current CPU. */ void exception_hwinit(void); void exception_init(void); +/* + * Order matters for handling return values. The larger the value the higher + * the precedence. + */ +enum { + EXC_RET_IGNORED, + EXC_RET_ABORT, + EXC_RET_HANDLED, + EXC_RET_HANDLED_DUMP_STATE, +}; + +struct exception_handler { + int (*handler)(struct exc_state *state, uint64_t vector_id); + struct exception_handler *next; +}; + + +/* + * Register a handler provided with the associated vector id. Returns 0 on + * sucess, < 0 on error. Note that registration is not thread/interrupt safe. + */ +int exception_handler_register(uint64_t vid, struct exception_handler *h); + +/* + * Unregister a handler from the vector id. Return 0 on success, < 0 on error. + * Note that the unregistration is not thread/interrupt safe. + */ +int exception_handler_unregister(uint64_t vid, struct exception_handler *h); + #endif diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 9f48549..111efe0 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -77,22 +77,22 @@ */ ENTRY_WITH_ALIGN(exc_vectors, 11) -eentry sync_curr_sp0,#0 -eentry irq_curr_sp0,#1 -eentry fiq_curr_sp0,#2 -eentry serror_curr_sp0,#3 -eentry sync_curr_spx,#4 -eentry irq_curr_spx,#5 -eentry fiq_curr_spx,#6 -eentry serror_curr_spx,#7 -eentry sync_lower_64,#8 -eentry irq_lower_64,#9 -eentry fiq_lower_64,#10 -eentry serror_lower_64,#11 -eentry sync_lower_32,#12 -eentry irq_lower_32,#13 -eentry fiq_lower_32,#14 -eentry serror_lower_32,#15 +eentry sync_curr_sp0, #EXC_VID_CUR_SP_EL0_SYNC +eentry irq_curr_sp0, #EXC_VID_CUR_SP_EL0_IRQ +eentry fiq_curr_sp0, #EXC_VID_CUR_SP_EL0_FIRQ +eentry serror_curr_sp0, #EXC_VID_CUR_SP_EL0_SERR +eentry sync_curr_spx, #EXC_VID_CUR_SP_ELX_SYNC +eentry irq_curr_spx, #EXC_VID_CUR_SP_ELX_IRQ +eentry fiq_curr_spx, #EXC_VID_CUR_SP_ELX_FIQ +eentry serror_curr_spx, #EXC_VID_CUR_SP_ELX_SERR +eentry sync_lower_64, #EXC_VID_LOW64_SYNC +eentry irq_lower_64, #EXC_VID_LOW64_IRQ +eentry fiq_lower_64, #EXC_VID_LOW64_FIQ +eentry serror_lower_64, #EXC_VID_LOW64_SERR +eentry sync_lower_32, #EXC_VID_LOW32_SYNC +eentry irq_lower_32, #EXC_VID_LOW32_IRQ +eentry fiq_lower_32, #EXC_VID_LOW32_FIQ +eentry serror_lower_32, #EXC_VID_LOW32_SERR ENDPROC(exc_vectors)

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Patch set updated for coreboot: 38fbe3f arm64: split cpu.c
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9089 -gerrit commit 38fbe3f4449b34e31cd6acb4b88d42a85953f002 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 18 11:52:16 2014 -0500 arm64: split cpu.c The cpu.c contains some helpful construts as well as ramstage devicetree handling. Split the 2 pieces so that cpu.c can be reused in secmon. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted. Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218842 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/Makefile.inc | 1 + src/arch/arm64/cpu.c | 225 +------------------------------ src/arch/arm64/cpu_ramstage.c | 230 ++++++++++++++++++++++++++++++++ src/arch/arm64/include/armv8/arch/cpu.h | 20 +++ 4 files changed, 256 insertions(+), 220 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c2caf64..6d23dab 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -116,6 +116,7 @@ ramstage-y += c_entry.c ramstage-y += stages.c ramstage-y += div0.c ramstage-y += cpu.c +ramstage-y += cpu_ramstage.c ramstage-y += eabi_compat.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c index a263e1b..eb08735 100644 --- a/src/arch/arm64/cpu.c +++ b/src/arch/arm64/cpu.c @@ -19,163 +19,19 @@ #include <stdint.h> #include <stdlib.h> -#include <arch/barrier.h> #include <arch/lib_helpers.h> #include <cpu/cpu.h> #include <console/console.h> -#include <gic.h> #include "cpu-internal.h" -static struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; +struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; struct cpu_info *bsp_cpu_info; -static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) -{ - return &cpu_infos[id]; -} - struct cpu_info *cpu_info(void) { return cpu_info_for_cpu(smp_processor_id()); } -static int cpu_online(struct cpu_info *ci) -{ - return load_acquire(&ci->online) != 0; -} - -static void cpu_mark_online(struct cpu_info *ci) -{ - store_release(&ci->online, 1); -} - -static inline void cpu_disable_dev(device_t dev) -{ - dev->enabled = 0; -} - -static struct cpu_driver *locate_cpu_driver(uint32_t midr) -{ - struct cpu_driver *cur; - - for (cur = cpu_drivers; cur != ecpu_drivers; cur++) { - const struct cpu_device_id *id_table = cur->id_table; - - for (; id_table->midr != CPU_ID_END; id_table++) { - if (id_table->midr == midr) - return cur; - } - } - return NULL; -} - -static int cpu_set_device_operations(device_t dev) -{ - uint32_t midr; - struct cpu_driver *driver; - - midr = raw_read_midr_el1(); - driver = locate_cpu_driver(midr); - - if (driver == NULL) { - printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr); - return -1; - } - dev->ops = driver->ops; - return 0; -} - -/* Set up default SCR values. */ -static void el3_init(void) -{ - uint32_t scr; - - if (get_current_el() != EL3) - return; - - scr = raw_read_scr_el3(); - /* Default to non-secure EL1 and EL0. */ - scr &= ~(SCR_NS_MASK); - scr |= SCR_NS_ENABLE; - /* Disable IRQ, FIQ, and external abort interrupt routing. */ - scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); - scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; - /* Enable HVC */ - scr &= ~(SCR_HVC_MASK); - scr |= SCR_HVC_ENABLE; - /* Disable SMC */ - scr &= ~(SCR_SMC_MASK); - scr |= SCR_SMC_DISABLE; - /* Disable secure instruction fetches. */ - scr &= ~(SCR_SIF_MASK); - scr |= SCR_SIF_DISABLE; - /* All lower exception levels 64-bit by default. */ - scr &= ~(SCR_RW_MASK); - scr |= SCR_LOWER_AARCH64; - /* Disable secure EL1 access to secure timer. */ - scr &= ~(SCR_ST_MASK); - scr |= SCR_ST_DISABLE; - /* Don't trap on WFE or WFI instructions. */ - scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); - scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; - raw_write_scr_el3(scr); - isb(); -} - -static void init_this_cpu(void *arg) -{ - struct cpu_info *ci = arg; - device_t dev = ci->cpu; - - cpu_set_device_operations(dev); - - el3_init(); - - /* Initialize the GIC. */ - gic_init(); - - if (dev->ops != NULL && dev->ops->init != NULL) { - dev->initialized = 1; - printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); - dev->ops->init(dev); - } -} - -/* Fill in cpu_info structures according to device tree. */ -static void init_cpu_info(struct bus *bus) -{ - device_t cur; - - for (cur = bus->children; cur != NULL; cur = cur->sibling) { - struct cpu_info *ci; - unsigned int id = cur->path.cpu.id; - - if (cur->path.type != DEVICE_PATH_CPU) - continue; - - /* IDs are currently mapped 1:1 with logical CPU numbers. */ - if (id >= CONFIG_MAX_CPUS) { - printk(BIOS_WARNING, - "CPU id %x too large. Disabling.\n", id); - cpu_disable_dev(cur); - continue; - } - - ci = cpu_info_for_cpu(id); - if (ci->cpu != NULL) { - printk(BIOS_WARNING, - "Duplicate ID %x in device tree.\n", id); - cpu_disable_dev(cur); - } - - ci->cpu = cur; - ci->id = cur->path.cpu.id; - } - - /* Mark current cpu online. */ - cpu_mark_online(cpu_info()); -} - static inline int action_queue_empty(struct cpu_action_queue *q) { return load_acquire_exclusive(&q->todo) == NULL; @@ -246,8 +102,8 @@ static void action_run_on_cpu(struct cpu_info *ci, struct cpu_action *action, { struct cpu_action_queue *q = &ci->action_queue; - /* Don't run actions on non-online or enabled devices. */ - if (!cpu_online(ci) || ci->cpu == NULL || !ci->cpu->enabled) + /* Don't run actions on non-online cpus. */ + if (!cpu_online(ci)) return; if (ci->id == smp_processor_id()) { @@ -333,14 +189,12 @@ int arch_run_on_all_cpus_but_self_async(struct cpu_action *action) return __arch_run_on_all_cpus_but_self(action, 0); } -void arch_secondary_cpu_init(void) + +void arch_cpu_wait_for_action(void) { struct cpu_info *ci = cpu_info(); struct cpu_action_queue *q = &ci->action_queue; - /* Mark this CPU online. */ - cpu_mark_online(ci); - while (1) { struct cpu_action *orig; struct cpu_action action; @@ -351,72 +205,3 @@ void arch_secondary_cpu_init(void) action_queue_complete(q, orig); } } - -void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops) -{ - size_t max_cpus; - size_t i; - struct cpu_info *ci; - void (*entry)(void); - struct bus *bus; - - if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) { - printk(BIOS_ERR, - "CPU init failed. Device is not a CPU_CLUSTER: %s\n", - dev_path(cluster)); - return; - } - - bus = cluster->link_list; - - /* Check if no children under this device. */ - if (bus == NULL) - return; - - entry = prepare_secondary_cpu_startup(); - - /* Initialize the cpu_info structures. */ - init_cpu_info(bus); - max_cpus = cntrl_ops->total_cpus(); - - if (max_cpus > CONFIG_MAX_CPUS) { - printk(BIOS_WARNING, - "max_cpus (%zu) exceeds CONFIG_MAX_CPUS (%zu).\n", - max_cpus, (size_t)CONFIG_MAX_CPUS); - max_cpus = CONFIG_MAX_CPUS; - } - - for (i = 0; i < max_cpus; i++) { - device_t dev; - struct cpu_action action; - - ci = cpu_info_for_cpu(i); - dev = ci->cpu; - - /* Disregard CPUs not in device tree. */ - if (dev == NULL) - continue; - - /* Skip disabled CPUs. */ - if (!dev->enabled) - continue; - - if (!cpu_online(ci)) { - /* Start the CPU. */ - printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id); - if (cntrl_ops->start_cpu(ci->id, entry)) { - printk(BIOS_ERR, - "Failed to start CPU%x\n", ci->id); - continue; - } - /* Wait for CPU to come online. */ - while (!cpu_online(ci)); - printk(BIOS_DEBUG, "CPU%x online.\n", ci->id); - } - - /* Send it the init action. */ - action.run = init_this_cpu; - action.arg = ci; - action_run_on_cpu(ci, &action, 1); - } -} diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c new file mode 100644 index 0000000..0f26206 --- /dev/null +++ b/src/arch/arm64/cpu_ramstage.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/lib_helpers.h> +#include <cpu/cpu.h> +#include <console/console.h> +#include <gic.h> +#include "cpu-internal.h" + +static inline void cpu_disable_dev(device_t dev) +{ + dev->enabled = 0; +} + +static struct cpu_driver *locate_cpu_driver(uint32_t midr) +{ + struct cpu_driver *cur; + + for (cur = cpu_drivers; cur != ecpu_drivers; cur++) { + const struct cpu_device_id *id_table = cur->id_table; + + for (; id_table->midr != CPU_ID_END; id_table++) { + if (id_table->midr == midr) + return cur; + } + } + return NULL; +} + +static int cpu_set_device_operations(device_t dev) +{ + uint32_t midr; + struct cpu_driver *driver; + + midr = raw_read_midr_el1(); + driver = locate_cpu_driver(midr); + + if (driver == NULL) { + printk(BIOS_WARNING, "No CPU driver for MIDR %08x\n", midr); + return -1; + } + dev->ops = driver->ops; + return 0; +} + +/* Set up default SCR values. */ +static void el3_init(void) +{ + uint32_t scr; + + if (get_current_el() != EL3) + return; + + scr = raw_read_scr_el3(); + /* Default to non-secure EL1 and EL0. */ + scr &= ~(SCR_NS_MASK); + scr |= SCR_NS_ENABLE; + /* Disable IRQ, FIQ, and external abort interrupt routing. */ + scr &= ~(SCR_IRQ_MASK | SCR_FIQ_MASK | SCR_EA_MASK); + scr |= SCR_IRQ_DISABLE | SCR_FIQ_DISABLE | SCR_EA_DISABLE; + /* Enable HVC */ + scr &= ~(SCR_HVC_MASK); + scr |= SCR_HVC_ENABLE; + /* Disable SMC */ + scr &= ~(SCR_SMC_MASK); + scr |= SCR_SMC_DISABLE; + /* Disable secure instruction fetches. */ + scr &= ~(SCR_SIF_MASK); + scr |= SCR_SIF_DISABLE; + /* All lower exception levels 64-bit by default. */ + scr &= ~(SCR_RW_MASK); + scr |= SCR_LOWER_AARCH64; + /* Disable secure EL1 access to secure timer. */ + scr &= ~(SCR_ST_MASK); + scr |= SCR_ST_DISABLE; + /* Don't trap on WFE or WFI instructions. */ + scr &= ~(SCR_TWI_MASK | SCR_TWE_MASK); + scr |= SCR_TWI_DISABLE | SCR_TWE_DISABLE; + raw_write_scr_el3(scr); + isb(); +} + +static void init_this_cpu(void *arg) +{ + struct cpu_info *ci = arg; + device_t dev = ci->cpu; + + cpu_set_device_operations(dev); + + el3_init(); + + /* Initialize the GIC. */ + gic_init(); + + if (dev->ops != NULL && dev->ops->init != NULL) { + dev->initialized = 1; + printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); + dev->ops->init(dev); + } +} + +/* Fill in cpu_info structures according to device tree. */ +static void init_cpu_info(struct bus *bus) +{ + device_t cur; + + for (cur = bus->children; cur != NULL; cur = cur->sibling) { + struct cpu_info *ci; + unsigned int id = cur->path.cpu.id; + + if (cur->path.type != DEVICE_PATH_CPU) + continue; + + /* IDs are currently mapped 1:1 with logical CPU numbers. */ + if (id >= CONFIG_MAX_CPUS) { + printk(BIOS_WARNING, + "CPU id %x too large. Disabling.\n", id); + cpu_disable_dev(cur); + continue; + } + + ci = cpu_info_for_cpu(id); + if (ci->cpu != NULL) { + printk(BIOS_WARNING, + "Duplicate ID %x in device tree.\n", id); + cpu_disable_dev(cur); + } + + ci->cpu = cur; + ci->id = cur->path.cpu.id; + } + + /* Mark current cpu online. */ + cpu_mark_online(cpu_info()); +} + +void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops) +{ + size_t max_cpus; + size_t i; + struct cpu_info *ci; + void (*entry)(void); + struct bus *bus; + + if (cluster->path.type != DEVICE_PATH_CPU_CLUSTER) { + printk(BIOS_ERR, + "CPU init failed. Device is not a CPU_CLUSTER: %s\n", + dev_path(cluster)); + return; + } + + bus = cluster->link_list; + + /* Check if no children under this device. */ + if (bus == NULL) + return; + + entry = prepare_secondary_cpu_startup(); + + /* Initialize the cpu_info structures. */ + init_cpu_info(bus); + max_cpus = cntrl_ops->total_cpus(); + + if (max_cpus > CONFIG_MAX_CPUS) { + printk(BIOS_WARNING, + "max_cpus (%zu) exceeds CONFIG_MAX_CPUS (%zu).\n", + max_cpus, (size_t)CONFIG_MAX_CPUS); + max_cpus = CONFIG_MAX_CPUS; + } + + for (i = 0; i < max_cpus; i++) { + device_t dev; + struct cpu_action action; + + ci = cpu_info_for_cpu(i); + dev = ci->cpu; + + /* Disregard CPUs not in device tree. */ + if (dev == NULL) + continue; + + /* Skip disabled CPUs. */ + if (!dev->enabled) + continue; + + if (!cpu_online(ci)) { + /* Start the CPU. */ + printk(BIOS_DEBUG, "Starting CPU%x\n", ci->id); + if (cntrl_ops->start_cpu(ci->id, entry)) { + printk(BIOS_ERR, + "Failed to start CPU%x\n", ci->id); + continue; + } + /* Wait for CPU to come online. */ + while (!cpu_online(ci)); + printk(BIOS_DEBUG, "CPU%x online.\n", ci->id); + } + + /* Send it the init action. */ + action.run = init_this_cpu; + action.arg = ci; + arch_run_on_cpu(ci->id, &action); + } +} + +void arch_secondary_cpu_init(void) +{ + /* Mark this CPU online. */ + cpu_mark_online(cpu_info()); + + arch_cpu_wait_for_action(); +} diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 8d071ad..fc31903 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -23,6 +23,7 @@ #define asmlinkage #if !defined(__PRE_RAM__) +#include <arch/barrier.h> #include <device/device.h> enum { @@ -67,6 +68,12 @@ struct cpu_info { struct cpu_info *cpu_info(void); extern struct cpu_info *bsp_cpu_info; +extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; + +static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) +{ + return &cpu_infos[id]; +} /* Ran only by BSP at initial boot strapping. */ static inline void cpu_set_bsp(void) @@ -79,6 +86,16 @@ static inline int cpu_is_bsp(void) return cpu_info() == bsp_cpu_info; } +static inline int cpu_online(struct cpu_info *ci) +{ + return load_acquire(&ci->online) != 0; +} + +static inline void cpu_mark_online(struct cpu_info *ci) +{ + store_release(&ci->online, 1); +} + /* Control routines for starting CPUs. */ struct cpu_control_ops { /* Return the maximum number of CPUs supported. */ @@ -112,6 +129,9 @@ int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); int arch_run_on_all_cpus_async(struct cpu_action *action); int arch_run_on_all_cpus_but_self_async(struct cpu_action *action); +/* Wait for actions to be perfomed. */ +void arch_cpu_wait_for_action(void); + #endif /* !__PRE_RAM__ */ /*

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Patch set updated for coreboot: 89cd035 arm64: fix smc bugs in secmon
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9094 -gerrit commit 89cd03582bf7c5b09c80733f11c75e5c13cca667 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 19 17:08:20 2014 -0500 arm64: fix smc bugs in secmon Two things: 1. Not returning once setting the return state. 2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x)) With these 2 changes arguments and results are being processed correctly. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and brought up SMP using PSCI. Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8 Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218847 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/secmon/smc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/arm64/armv8/secmon/smc.c b/src/arch/arm64/armv8/secmon/smc.c index 3bb52f0..8aa6d41 100644 --- a/src/arch/arm64/armv8/secmon/smc.c +++ b/src/arch/arm64/armv8/secmon/smc.c @@ -84,7 +84,7 @@ int smc_register_range(uint32_t min, uint32_t max, int (*h)(struct smc_call *)) static int smc_cleanup(struct exc_state *state, struct smc_call *smc, int ret) { - memcpy(&state->regs.x, &smc->results, ARRAY_SIZE(smc->results)); + memcpy(&state->regs.x, &smc->results, sizeof(smc->results)); return ret; } @@ -103,15 +103,15 @@ static int smc_handler(struct exc_state *state, uint64_t vector_id) uint32_t esr; struct smc_range *r; - memcpy(&smc->args, &state->regs.x, ARRAY_SIZE(smc->args)); - memcpy(&smc->results, &state->regs.x, ARRAY_SIZE(smc->results)); + memcpy(&smc->args, &state->regs.x, sizeof(smc->args)); + memcpy(&smc->results, &state->regs.x, sizeof(smc->results)); esr = raw_read_esr_el3(); exception_class = (esr >> 26) & 0x3f; /* No support for 32-bit SMC calls. */ if (exception_class == EC_SMC32) - smc_return_with_error(state, smc); + return smc_return_with_error(state, smc); /* Check to ensure this is an SMC from aarch64. */ if (exception_class != EC_SMC64) @@ -119,7 +119,7 @@ static int smc_handler(struct exc_state *state, uint64_t vector_id) /* Ensure immediate value is 0. */ if ((esr & 0xffff) != 0) - smc_return_with_error(state, smc); + return smc_return_with_error(state, smc); r = smc_handler_by_function(smc_function_id(smc));

1 0

Patch set updated for coreboot: 609b295 Ryu: Move I2C6 init to ramstage
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9095 -gerrit commit 609b295dce93d65a8c41fdf58f3e8faeaedbd371 Author: Tom Warren <twarren(a)nvidia.com> Date: Thu Sep 18 15:23:10 2014 -0700 Ryu: Move I2C6 init to ramstage BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639 Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218950 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rush_ryu/mainboard.c | 7 +++++++ src/mainboard/google/rush_ryu/romstage.c | 5 ----- src/soc/nvidia/tegra132/Makefile.inc | 3 ++- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 3b291c8..ffa3234 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -27,6 +27,7 @@ #include <soc/funitcfg.h> #include <soc/padconfig.h> #include <soc/nvidia/tegra132/clk_rst.h> +#include <soc/nvidia/tegra/i2c.h> static const struct pad_config mmcpads[] = { /* MMC4 (eMMC) */ @@ -45,6 +46,8 @@ static const struct pad_config mmcpads[] = { static const struct funit_cfg funits[] = { /* MMC on SDMMC4 controller at 48MHz. */ FUNIT_CFG(SDMMC4, PLLP, 48000, mmcpads, ARRAY_SIZE(mmcpads)), + /* I2C6 for audio, temp sensor, etc. */ + FUNIT_CFG(I2C6, PLLP, 400, NULL, 0), FUNIT_CFG_USB(USBD), }; @@ -60,6 +63,10 @@ static void mainboard_init(device_t dev) if (disp_clk != req_disp_clk) printk(BIOS_DEBUG, "display clock: %u vs %u (r)\n", disp_clk, req_disp_clk); + + /* I2C6 bus (audio, etc.) */ + soc_configure_i2c6pad(); + i2c_init(I2C6_BUS); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index ab5b2a8..d4e38a8 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -57,8 +57,6 @@ static const struct funit_cfg funits[] = { FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)), /* EC on I2C2 - pulled to 3.3V @ 100kHz */ FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)), - /* I2C6 for audio, temp sensor, etc. */ - FUNIT_CFG(I2C6, PLLP, 400, NULL, 0), }; static void lte_modem_init(void) @@ -92,14 +90,11 @@ void romstage_mainboard_init(void) /* Bring up controller interfaces for ramstage loading. */ soc_configure_funits(funits, ARRAY_SIZE(funits)); soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs)); - soc_configure_i2c6pad(); /* TPM */ i2c_init(I2C3_BUS); /* EC */ i2c_init(I2C2_BUS); - /* I2C6 bus (audio, etc.) */ - i2c_init(I2C6_BUS); lte_modem_init(); } diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index e656b80..7603c70 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -32,7 +32,6 @@ romstage-y += cpu.c romstage-y += reset.c romstage-y += spi.c romstage-y += i2c.c -romstage-y += i2c6.c romstage-y += dma.c romstage-y += monotonic_timer.c romstage-y += padconfig.c @@ -58,6 +57,8 @@ ramstage-y += clock.c ramstage-y += soc.c ramstage-y += spi.c ramstage-y += i2c.c +ramstage-y += i2c6.c +ramstage-y += power.c ramstage-y += dma.c ramstage-y += gic.c ramstage-y += monotonic_timer.c

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coreboot-gerrit March 2015