coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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2443 discussions

New patch to review for coreboot: c4003fc storm: make sure board ID is calculated only once
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9119 -gerrit commit c4003fc30d6af0f8408ecf8f13aeafa210006d2f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 8 14:04:08 2014 -0700 storm: make sure board ID is calculated only once Figuring out board_id on storm requires reading tertiary gpios, which takes time. Let's calculate it once and reuse it when necessary. BUG=none TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2 respectively. Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1 Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217086 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/boardid.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 6d7a918..683b5f4 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -37,7 +37,9 @@ * revision. */ -uint8_t board_id(void) +static int board_id_value = -1; + +static uint8_t get_board_id(void) { uint8_t bid; gpio_t hw_rev_gpios[] = {29, 30, 68}; @@ -50,3 +52,11 @@ uint8_t board_id(void) return bid; } + +uint8_t board_id(void) +{ + if (board_id_value < 0) + board_id_value = get_board_id(); + + return board_id_value; +}

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New patch to review for coreboot: d74be0e storm: reset TPM properly on proto0
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9118 -gerrit commit d74be0e53f7f4c2ffda2a52e746b2c6a428132ac Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Aug 7 15:20:21 2014 -0700 storm: reset TPM properly on proto0 The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22 pin instead of the system reset. This causes all kind of TPM behavior problems and requires frequent power cycles. Adding explicit TPM reset makes all those problems go away. BUG=chrome-os-partner:30705, chrome-os-partner:30829 TEST=tried resetting proto0 at different moments during boot up - the TPM does not fail anymore. Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6 Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211497 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 442e9e9..268ed46 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -18,10 +18,12 @@ */ #include <arch/cache.h> +#include <boardid.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <device/device.h> #include <delay.h> +#include <device/device.h> +#include <gpiolib.h> #include <string.h> #include <soc/qualcomm/ipq806x/include/clock.h> @@ -71,10 +73,29 @@ static void setup_mmu(void) dcache_mmu_enable(); } +#define TPM_RESET_GPIO 22 +static void setup_tpm(void) +{ + if (board_id() != 0) + return; /* Only proto0 have TPM reset connected to GPIO22 */ + + gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, + GPIO_4MA, GPIO_ENABLE); + /* + * Generate a reset pulse. The spec calls for 80 us minimum, let's + * make it twice as long. If the output was driven low originally, the + * reset pulse will be even longer. + */ + gpio_set_out_value(TPM_RESET_GPIO, 0); + udelay(160); + gpio_set_out_value(TPM_RESET_GPIO, 1); +} + static void mainboard_init(device_t dev) { setup_mmu(); setup_usb(); + setup_tpm(); } static void mainboard_enable(device_t dev)

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New patch to review for coreboot: b69d8d2 storm: supply vboot GPIO settings in coreboot table
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9117 -gerrit commit b69d8d27e225c0a1b51844971396b93964854de2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Aug 1 17:36:45 2014 -0700 storm: supply vboot GPIO settings in coreboot table Storm provides three real and two fake gpios. To keep things simple, define them all as active low and provide appropriate values for the fake ones. BUG=chrome-os-partner:30705 TEST=with the appropriate depthcharge change booted proto0, observed appropriate behavior following the dev switch setting Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210922 --- src/mainboard/google/storm/mainboard.c | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 94f3a92..442e9e9 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -19,7 +19,11 @@ #include <arch/cache.h> #include <boot/coreboot_tables.h> +#include <console/console.h> #include <device/device.h> +#include <delay.h> +#include <string.h> + #include <soc/qualcomm/ipq806x/include/clock.h> #include <soc/qualcomm/ipq806x/include/gpio.h> #include <soc/qualcomm/ipq806x/include/usb.h> @@ -93,3 +97,51 @@ void lb_board(struct lb_header *header) dma->range_start = CONFIG_DRAM_DMA_START; dma->range_size = CONFIG_DRAM_DMA_SIZE; } + +#define FAKE_GPIO_NUM -1 + +struct gpio_desc { + gpio_t gpio_num; + const char *gpio_name; + uint32_t fake_value; +}; + +static const struct gpio_desc descriptors[] = { + { 15, "developer" }, + { 16, "recovery" }, + { 17, "write protect" }, + { FAKE_GPIO_NUM, "power", 1 }, /* Power never pressed. */ + { FAKE_GPIO_NUM, "lid", 0 } /* Lid always open. */ +}; + +static void fill_lb_gpio(struct lb_gpio *pgpio, const struct gpio_desc *pdesc) +{ + gpio_t gpio_num = pdesc->gpio_num; + + pgpio->port = gpio_num; + if (gpio_num == FAKE_GPIO_NUM) { + pgpio->value = pdesc->fake_value; + } else { + gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); + udelay(10); /* Should be enough to settle. */ + pgpio->value = gpio_get_in_value(gpio_num); + } + pgpio->polarity = ACTIVE_LOW; + strncpy((char *)pgpio->name, pdesc->gpio_name, sizeof(pgpio->name)); + + printk(BIOS_INFO, "%s: %s: port %d value %d\n", + __func__, pgpio->name, pgpio->port, pgpio->value); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(descriptors); i++) + fill_lb_gpio(gpios->gpios + i, descriptors + i); + + + gpios->size = sizeof(*gpios) + sizeof(struct lb_gpio) * i; + gpios->count = i; +}

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New patch to review for coreboot: 1fcb6ac blaze: update EMC BCT table
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9116 -gerrit commit 1fcb6aceb217b8580bcbb2273641a5ed289c53fe Author: Neil Chen <neilc(a)nvidia.com> Date: Mon Jul 28 18:00:29 2014 +0800 blaze: update EMC BCT table This change updated the EMC tables with emc_reg_tool 5.0.18, for below memory SKUs: - Hynix H5TC4G63AFR-PBR 2GB, ramcode = 0 - Micron MT41K256M16HA-125 2GB, ramcode = 1 - Samsung K4B4G1646Q-HYK0 2GB, ramcode = 2 - Hynix H5TC8G63AFR-PBR 4GB, ramcode = 8 - Micron MT41K512M16TNA-125 4GB, ramcode = 9 - Samsung K4B8G1646Q-MYKO 4GB, ramcode = 10 BUG=chrome-os-partner:30963 BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Change-Id: Iee329ff09e35cddd3c868c0460a38ef56b2ac5bb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 158872ff7c0dd5274cfa8d63ec17b4423a4592ce Original-Change-Id: I44adfdb5b433e37e2d25095acdcce3d9c14eb897 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210024 Original-Tested-by: Ken Chang <kenc(a)nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> --- .../google/nyan_blaze/bct/sdram-hynix-2GB-792.inc | 20 ++++---- .../google/nyan_blaze/bct/sdram-hynix-4GB-792.inc | 18 ++++---- .../google/nyan_blaze/bct/sdram-micron-2GB-792.inc | 20 ++++---- .../google/nyan_blaze/bct/sdram-micron-4GB-792.inc | 12 ++--- .../nyan_blaze/bct/sdram-samsung-2GB-792.inc | 20 ++++---- .../nyan_blaze/bct/sdram-samsung-4GB-792.inc | 54 +++++++++++----------- 6 files changed, 72 insertions(+), 72 deletions(-) diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-792.inc index ec0b7f1..3d79a5e 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from Hynix_2GB_H5TC4G63AFR_PBA_792MHz_0318_Modify.cfg; do not edit. */ +{ /* generated from Hynix_2GB_H5TC4G63AFR_PBA_792MHz_0703_PVT_Modify.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -241,15 +241,15 @@ .EmcXm2VttGenPadCtrl3 = 0x016eeeee, .EmcAcpdControl = 0x00000000, .EmcSwizzleRank0ByteCfg = 0x00003120, - .EmcSwizzleRank0Byte0 = 0x25143067, - .EmcSwizzleRank0Byte1 = 0x45367102, - .EmcSwizzleRank0Byte2 = 0x47106253, - .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, .EmcSwizzleRank1ByteCfg = 0x00003120, - .EmcSwizzleRank1Byte0 = 0x71546032, - .EmcSwizzleRank1Byte1 = 0x35104276, - .EmcSwizzleRank1Byte2 = 0x27043615, - .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, .EmcDsrVttgenDrv = 0x0606003f, .EmcTxdsrvttgen = 0x00000000, .EmcBgbiasCtl0 = 0x00000000, @@ -301,7 +301,7 @@ .EmcCaTrainingEnable = 0x00000000, .EmcCaTrainingTimingCntl1 = 0x1f7df7df, .EmcCaTrainingTimingCntl2 = 0x0000001f, - .SwizzleRankByteEncode = 0x0000006f, + .SwizzleRankByteEncode = 0x0000000b, .BootRomPatchControl = 0x00000000, .BootRomPatchData = 0x00000000, .McMtsCarveoutBom = 0xfff00000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc index 6afd3b7..057d93b 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from Hynix_4GB_H5TC8G63AFR_PBA_792MHz_release.cfg; do not edit. */ +{ /* generated from Hynix_4GB_H5TC8G63AFR_PBA_792MHz_0714.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -24,7 +24,7 @@ .EmcBctSpare11 = 0x00000000, .EmcClockSource = 0x80000000, .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430404, + .EmcAutoCalConfig = 0xa1430808, .EmcAutoCalConfig2 = 0x00000000, .EmcAutoCalConfig3 = 0x00000000, .EmcAutoCalWait = 0x00000190, @@ -123,18 +123,18 @@ .EmcDllXformDqs1 = 0x00000008, .EmcDllXformDqs2 = 0x00000008, .EmcDllXformDqs3 = 0x00000008, - .EmcDllXformDqs4 = 0x00000006, - .EmcDllXformDqs5 = 0x00000006, + .EmcDllXformDqs4 = 0x00008004, + .EmcDllXformDqs5 = 0x00004006, .EmcDllXformDqs6 = 0x00000006, - .EmcDllXformDqs7 = 0x007F8008, + .EmcDllXformDqs7 = 0x00008004, .EmcDllXformDqs8 = 0x00000008, .EmcDllXformDqs9 = 0x00000008, .EmcDllXformDqs10 = 0x00000008, .EmcDllXformDqs11 = 0x00000008, - .EmcDllXformDqs12 = 0x00000006, - .EmcDllXformDqs13 = 0x00000006, + .EmcDllXformDqs12 = 0x00008004, + .EmcDllXformDqs13 = 0x00004006, .EmcDllXformDqs14 = 0x00000006, - .EmcDllXformDqs15 = 0x007F8008, + .EmcDllXformDqs15 = 0x00008004, .EmcDllXformQUse0 = 0x00000000, .EmcDllXformQUse1 = 0x00000000, .EmcDllXformQUse2 = 0x00000000, @@ -229,7 +229,7 @@ .EmcXm2DqsPadCtrl3 = 0x69A69A20, .EmcXm2DqsPadCtrl4 = 0x00514514, .EmcXm2DqsPadCtrl5 = 0x00514510, - .EmcXm2DqsPadCtrl6 = 0x69A69A00, + .EmcXm2DqsPadCtrl6 = 0x69865A00, .EmcXm2DqPadCtrl = 0x770c2990, .EmcXm2DqPadCtrl2 = 0x00000000, .EmcXm2DqPadCtrl3 = 0x00000000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-micron-2GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-micron-2GB-792.inc index 1b52f0c..c24242e 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-micron-2GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-micron-2GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from Micron_2GB_MT41K256M16HA_792MHz_0408.cfg; do not edit. */ +{ /* generated from Micron_2GB_MT41K256M16HA_792MHz_0623.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -241,15 +241,15 @@ .EmcXm2VttGenPadCtrl3 = 0x016eeeee, .EmcAcpdControl = 0x00000000, .EmcSwizzleRank0ByteCfg = 0x00003120, - .EmcSwizzleRank0Byte0 = 0x25143067, - .EmcSwizzleRank0Byte1 = 0x45367102, - .EmcSwizzleRank0Byte2 = 0x47106253, - .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, .EmcSwizzleRank1ByteCfg = 0x00003120, - .EmcSwizzleRank1Byte0 = 0x71546032, - .EmcSwizzleRank1Byte1 = 0x35104276, - .EmcSwizzleRank1Byte2 = 0x27043615, - .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, .EmcDsrVttgenDrv = 0x0606003f, .EmcTxdsrvttgen = 0x00000000, .EmcBgbiasCtl0 = 0x00000000, @@ -301,7 +301,7 @@ .EmcCaTrainingEnable = 0x00000000, .EmcCaTrainingTimingCntl1 = 0x1f7df7df, .EmcCaTrainingTimingCntl2 = 0x0000001f, - .SwizzleRankByteEncode = 0x0000006f, + .SwizzleRankByteEncode = 0x0000000b, .BootRomPatchControl = 0x00000000, .BootRomPatchData = 0x00000000, .McMtsCarveoutBom = 0xfff00000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc index 5a7b6be..e872653 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from Micron_4GB_MT41K512M16TNA-125_792MHz.cfg; do not edit. */ +{ /* generated from Micron_4GB_MT41K512M16TNA-125_792MHz_0707.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -120,7 +120,7 @@ .EmcDevSelect = 0x00000000, .EmcSelDpdCtrl = 0x00040000, .EmcDllXformDqs0 = 0x00000008, - .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs1 = 0x00004008, .EmcDllXformDqs2 = 0x00000008, .EmcDllXformDqs3 = 0x00000008, .EmcDllXformDqs4 = 0x00000008, @@ -174,12 +174,12 @@ .EmcDliTrimTxDqs14 = 0x0000000a, .EmcDliTrimTxDqs15 = 0x0000000a, .EmcDllXformDq0 = 0x0000000e, - .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq1 = 0x007F800E, .EmcDllXformDq2 = 0x0000000e, .EmcDllXformDq3 = 0x0000000e, .EmcDllXformDq4 = 0x0000000e, .EmcDllXformDq5 = 0x0000000e, - .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq6 = 0x0007F80E, .EmcDllXformDq7 = 0x0000000e, .WarmBootWait = 0x00000002, .EmcCttTermCtrl = 0x00000802, @@ -227,8 +227,8 @@ .EmcXm2DqsPadCtrl = 0x770c1414, .EmcXm2DqsPadCtrl2 = 0x0120113d, .EmcXm2DqsPadCtrl3 = 0x61861820, - .EmcXm2DqsPadCtrl4 = 0x00514514, - .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl4 = 0x00555555, + .EmcXm2DqsPadCtrl5 = 0x00555555, .EmcXm2DqsPadCtrl6 = 0x61861800, .EmcXm2DqPadCtrl = 0x770c2990, .EmcXm2DqPadCtrl2 = 0x00000000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-samsung-2GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-2GB-792.inc index a1728f2..9d180cc 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-samsung-2GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-2GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from Samsung_2GB_K4B4G1646Q_HYK0_792MHz_0502.cfg; do not edit. */ +{ /* generated from Samsung_2GB_K4B4G1646Q_HYK0_792MHz_0623_merged.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -241,15 +241,15 @@ .EmcXm2VttGenPadCtrl3 = 0x016eeeee, .EmcAcpdControl = 0x00000000, .EmcSwizzleRank0ByteCfg = 0x00003120, - .EmcSwizzleRank0Byte0 = 0x25143067, - .EmcSwizzleRank0Byte1 = 0x45367102, - .EmcSwizzleRank0Byte2 = 0x47106253, - .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, .EmcSwizzleRank1ByteCfg = 0x00003120, - .EmcSwizzleRank1Byte0 = 0x71546032, - .EmcSwizzleRank1Byte1 = 0x35104276, - .EmcSwizzleRank1Byte2 = 0x27043615, - .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, .EmcDsrVttgenDrv = 0x0606003f, .EmcTxdsrvttgen = 0x00000000, .EmcBgbiasCtl0 = 0x00000000, @@ -301,7 +301,7 @@ .EmcCaTrainingEnable = 0x00000000, .EmcCaTrainingTimingCntl1 = 0x1f7df7df, .EmcCaTrainingTimingCntl2 = 0x0000001f, - .SwizzleRankByteEncode = 0x0000006f, + .SwizzleRankByteEncode = 0x0000000b, .BootRomPatchControl = 0x00000000, .BootRomPatchData = 0x00000000, .McMtsCarveoutBom = 0xfff00000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc index f8c3a5f..a668570 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from Samsung_4GB_K4B8G1646Q_792MHz_release.cfg; do not edit. */ +{ /* generated from Samsung_4GB_K4B8G1646Q_792MHz_0703.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -24,7 +24,7 @@ .EmcBctSpare11 = 0x00000000, .EmcClockSource = 0x80000000, .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430707, + .EmcAutoCalConfig = 0xa1430F0F, .EmcAutoCalConfig2 = 0x00000000, .EmcAutoCalConfig3 = 0x00000000, .EmcAutoCalWait = 0x00000190, @@ -120,21 +120,21 @@ .EmcDevSelect = 0x00000000, .EmcSelDpdCtrl = 0x00040000, .EmcDllXformDqs0 = 0x00000009, - .EmcDllXformDqs1 = 0x0000000a, - .EmcDllXformDqs2 = 0x00000009, - .EmcDllXformDqs3 = 0x0000000a, - .EmcDllXformDqs4 = 0x0000000b, - .EmcDllXformDqs5 = 0x0000000a, - .EmcDllXformDqs6 = 0x0000000b, - .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs1 = 0x00000009, + .EmcDllXformDqs2 = 0x00008004, + .EmcDllXformDqs3 = 0x00000009, + .EmcDllXformDqs4 = 0x00000009, + .EmcDllXformDqs5 = 0x007f400c, + .EmcDllXformDqs6 = 0x007f800b, + .EmcDllXformDqs7 = 0x00000007, .EmcDllXformDqs8 = 0x00000009, - .EmcDllXformDqs9 = 0x0000000a, - .EmcDllXformDqs10 = 0x00000009, - .EmcDllXformDqs11 = 0x0000000a, - .EmcDllXformDqs12 = 0x0000000b, - .EmcDllXformDqs13 = 0x0000000a, - .EmcDllXformDqs14 = 0x0000000b, - .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformDqs9 = 0x00000009, + .EmcDllXformDqs10 = 0x00008004, + .EmcDllXformDqs11 = 0x00000009, + .EmcDllXformDqs12 = 0x00000009, + .EmcDllXformDqs13 = 0x007f400c, + .EmcDllXformDqs14 = 0x007f800b, + .EmcDllXformDqs15 = 0x00000007, .EmcDllXformQUse0 = 0x00000000, .EmcDllXformQUse1 = 0x00000000, .EmcDllXformQUse2 = 0x00000000, @@ -159,20 +159,20 @@ .EmcDllXformQUse15 = 0x00000000, .EmcDliTrimTxDqs0 = 0x00000008, .EmcDliTrimTxDqs1 = 0x00000008, - .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs2 = 0x00000008, .EmcDliTrimTxDqs3 = 0x00000008, - .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs4 = 0x00000008, .EmcDliTrimTxDqs5 = 0x00000008, - .EmcDliTrimTxDqs6 = 0x0000000a, - .EmcDliTrimTxDqs7 = 0x0000000a, + .EmcDliTrimTxDqs6 = 0x00000008, + .EmcDliTrimTxDqs7 = 0x00000008, .EmcDliTrimTxDqs8 = 0x00000008, .EmcDliTrimTxDqs9 = 0x00000008, - .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs10 = 0x00000008, .EmcDliTrimTxDqs11 = 0x00000008, - .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs12 = 0x00000008, .EmcDliTrimTxDqs13 = 0x00000008, - .EmcDliTrimTxDqs14 = 0x0000000a, - .EmcDliTrimTxDqs15 = 0x0000000a, + .EmcDliTrimTxDqs14 = 0x00000008, + .EmcDliTrimTxDqs15 = 0x00000008, .EmcDllXformDq0 = 0x0000000c, .EmcDllXformDq1 = 0x0000000c, .EmcDllXformDq2 = 0x0000000c, @@ -226,10 +226,10 @@ .EmcXm2CmdPadCtrl5 = 0x00111111, .EmcXm2DqsPadCtrl = 0x770c1414, .EmcXm2DqsPadCtrl2 = 0x0120113d, - .EmcXm2DqsPadCtrl3 = 0x61869a20, + .EmcXm2DqsPadCtrl3 = 0x69a69c20, .EmcXm2DqsPadCtrl4 = 0x00596596, - .EmcXm2DqsPadCtrl5 = 0x00596596, - .EmcXm2DqsPadCtrl6 = 0x69969900, + .EmcXm2DqsPadCtrl5 = 0x00618618, + .EmcXm2DqsPadCtrl6 = 0x69969a00, .EmcXm2DqPadCtrl = 0x770c2990, .EmcXm2DqPadCtrl2 = 0x00000000, .EmcXm2DqPadCtrl3 = 0x00000000,

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Patch merged into coreboot/master: b337c1d northbridge/amd/amdfam10: Properly implement SLIT generation
by gerrit＠coreboot.org 27 Mar '15

27 Mar '15

the following patch was just integrated into master: commit b337c1d1f5a2baef4445a221ad0534bf047f25fc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 21 15:11:58 2015 -0500 northbridge/amd/amdfam10: Properly implement SLIT generation Change-Id: I973abf2224762bf7a53d71177544ade15db50cba Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8856 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/8856 for details. -gerrit

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New patch to review for coreboot: a0ff48f x86/smm: Move SMM configuration out of generic Makefile
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9115 -gerrit commit a0ff48f189501052c2b539e5d79c4c69e2e65541 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 15:32:49 2015 +0100 x86/smm: Move SMM configuration out of generic Makefile It's x86 specific. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Iacb91b47c89041435dd27c2c9ad34a231adf21d2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- Makefile.inc | 10 ---------- src/cpu/x86/smm/Makefile.inc | 4 ++++ 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 59ddf7e..c0125a8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -134,16 +134,6 @@ endif bootblock-generic-ccopts += -D__BOOT_BLOCK__ -D__PRE_RAM__ -smmstub-generic-ccopts += -D__SMM__ -smm-generic-ccopts += -D__SMM__ - -# SMM TSEG base is dynamic -ifneq ($(CONFIG_SMM_MODULES),y) -ifeq ($(CONFIG_SMM_TSEG),y) -smm-c-ccopts += -fpic -endif -endif - ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) verstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 971eacf..3fb92a2 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -27,6 +27,9 @@ $(eval $(call create_class_compiler,smm,x86_64)) $(eval $(call create_class_compiler,smmstub,x86_64)) endif +smmstub-generic-ccopts += -D__SMM__ +smm-generic-ccopts += -D__SMM__ + $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --start-group $(smm-objs) $(COMPILER_RT_smm) --end-group @@ -101,6 +104,7 @@ endif # Use TSEG specific entry point and linker script ifeq ($(CONFIG_SMM_TSEG),y) smm-y += smmhandler_tseg.S +smm-c-ccopts += -fpic SMM_LDFLAGS := -pie SMM_LDSCRIPT := smm_tseg.ld else

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New patch to review for coreboot: d789a5c build system: provide generic compiler flag variables
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9114 -gerrit commit d789a5cdca49c354ee6ab26d5e6ab5f65c663ae5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 15:27:21 2015 +0100 build system: provide generic compiler flag variables Introduce generic-$(type)-ccopts and $(class)-generic-ccopts to declare compiler flags that apply to all files of a certain type or of a certain class. Then use them. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I655688e82a0cc5bad89b6f55dc217b9f66b64604 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- Makefile | 1 + Makefile.inc | 12 ++++-------- src/arch/arm64/armv8/secmon/Makefile.inc | 5 +++-- src/vendorcode/google/chromeos/Makefile.inc | 3 +-- 4 files changed, 9 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index 8b5d61b..0cc9b6a 100644 --- a/Makefile +++ b/Makefile @@ -235,6 +235,7 @@ endef filetypes-of-class=$(subst .,,$(sort $(suffix $($(1)-srcs)))) $(foreach class,$(classes), \ $(foreach type,$(call filetypes-of-class,$(class)), \ + $(eval $(class)-$(type)-ccopts += $(generic-$(type)-ccopts) $($(class)-generic-ccopts)) \ $(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-ccopts),$($(class)-$(type)-deps))))) foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file)))))) diff --git a/Makefile.inc b/Makefile.inc index 838a680..59ddf7e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -116,8 +116,7 @@ ramstage-postprocess=$(foreach d,$(sort $(dir $(1))), \ $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD_ramstage) -o $$@ -r $$^ ) \ $(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(call files-in-dir,$(d),$(1)),$(ramstage-objs)))) -romstage-c-ccopts:=-D__PRE_RAM__ -romstage-S-ccopts:=-D__PRE_RAM__ +romstage-generic-ccopts += -D__PRE_RAM__ ifeq ($(CONFIG_TRACE),y) ramstage-c-ccopts:= -finstrument-functions endif @@ -133,13 +132,10 @@ ifeq ($(CONFIG_USE_BLOBS),y) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty)) endif -bootblock-c-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ -bootblock-S-ccopts:=-D__BOOT_BLOCK__ -D__PRE_RAM__ +bootblock-generic-ccopts += -D__BOOT_BLOCK__ -D__PRE_RAM__ -smmstub-c-ccopts:=-D__SMM__ -smmstub-S-ccopts:=-D__SMM__ -smm-c-ccopts:=-D__SMM__ -smm-S-ccopts:=-D__SMM__ +smmstub-generic-ccopts += -D__SMM__ +smm-generic-ccopts += -D__SMM__ # SMM TSEG base is dynamic ifneq ($(CONFIG_SMM_MODULES),y) diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc index a8d42b0..c61e876 100644 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ b/src/arch/arm64/armv8/secmon/Makefile.inc @@ -28,8 +28,9 @@ SECMON_ELF=$(SECMON_DIR)/secmon.elf SECMON_RMOD=$(SECMON_DIR)/secmon.elf.rmod SECMON_RAMSTAGE=$(SECMON_DIR)/secmon.ramstage.o -secmon-c-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__ -secmon-S-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h -D__SECMON__ +secmon-generic-ccopts += -D__SECMON__ +secmon-c-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h +secmon-S-ccopts += -I$(src)/arch/arm64/include/armv8/ -include $(src)/include/kconfig.h secmon-y += secmon_init.c secmon-y += psci.c diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index d8c57fb..8cf84fe 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -96,8 +96,7 @@ VB_SOURCE := vboot_reference INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include INCLUDES += -I$(VB_SOURCE)/firmware/include -verstage-c-ccopts += -D__PRE_RAM__ -D__VER_STAGE__ -verstage-S-ccopts += -D__PRE_RAM__ -D__VER_STAGE__ +verstage-generic-ccopts += -D__PRE_RAM__ -D__VER_STAGE__ ifeq ($(CONFIG_RETURN_FROM_VERSTAGE),y) bootblock-y += verstub.c chromeos.c

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New patch to review for coreboot: 8d7e5b9 armv8/secmon: SECMON_SRC is really SECMON_BIN
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9113 -gerrit commit 8d7e5b92ecedf0087bd7017dbe9338cf3794da1b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:24:11 2015 +0100 armv8/secmon: SECMON_SRC is really SECMON_BIN It points to a binary. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I164d7f717a9523d187e2c215083e176b59fd5acc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/arch/arm64/armv8/secmon/Makefile.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc index 1c7a696..a8d42b0 100644 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ b/src/arch/arm64/armv8/secmon/Makefile.inc @@ -22,7 +22,7 @@ $(eval $(call create_class_compiler,secmon,arm64)) SECMON_DIR=$(obj)/arch/arm64/armv8/secmon -SECMON_SRC=$(SECMON_DIR)/secmon +SECMON_BIN=$(SECMON_DIR)/secmon SECMON_OBJ=$(SECMON_DIR)/secmon.o SECMON_ELF=$(SECMON_DIR)/secmon.elf SECMON_RMOD=$(SECMON_DIR)/secmon.elf.rmod @@ -39,16 +39,16 @@ secmon-y += ../exception.c secmon-y += ../../cpu.c secmon-y += ../../transition_asm.S ../../transition.c -ramstage-srcs += $(SECMON_SRC) +ramstage-srcs += $(SECMON_BIN) $(SECMON_OBJ): $$(secmon-objs) $(CC_secmon) $(LDFLAGS) -nostdlib -r -o $@ $^ $(eval $(call rmodule_link,$(SECMON_ELF), $(SECMON_OBJ), 0,arm64)) -$(SECMON_SRC): $(SECMON_RMOD) +$(SECMON_BIN): $(SECMON_RMOD) $(OBJCOPY_secmon) -O binary $< $@ -$(SECMON_RAMSTAGE): $(SECMON_SRC) +$(SECMON_RAMSTAGE): $(SECMON_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY_secmon) -I binary $(notdir $<) -O elf64-littleaarch64 -B aarch64 $(notdir $@)

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New patch to review for coreboot: b710ffa arch/arm64: Drop extra comment
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9112 -gerrit commit b710ffac0a1a40d2ca7982bd9bb4beb936a20747 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:29:36 2015 +0100 arch/arm64: Drop extra comment This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I362e2f6a978de23e72e6fc9c83bc99457cd76d9c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/arch/arm64/romstage.ld | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld index 9e08464..c56d5ad 100644 --- a/src/arch/arm64/romstage.ld +++ b/src/arch/arm64/romstage.ld @@ -20,11 +20,6 @@ */ /* We use ELF as output format. So that we can debug the code in some form. */ -/* - INCLUDE ldoptions - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) INCLUDE ldoptions

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New patch to review for coreboot: 9d50500 arch/arm: drop extra comment
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9111 -gerrit commit 9d505004d03f1e8fdec9d8576ff03813d123f2ac Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Mar 27 14:19:35 2015 +0100 arch/arm: drop extra comment This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I8a5dc66d8c0dc4ccdb6dc3d66b8cdbf50dc976ca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 --- src/arch/arm/romstage.ld | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld index 34e9eaa..873b8e0 100644 --- a/src/arch/arm/romstage.ld +++ b/src/arch/arm/romstage.ld @@ -20,8 +20,6 @@ */ /* We use ELF as output format. So that we can debug the code in some form. */ - -/* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) INCLUDE ldoptions

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coreboot-gerrit March 2015