coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a656a6f storm: deassert SW_RESET signal at startup
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9120 -gerrit commit a656a6f9b301cbe35a65285d0c75b95f3fab143c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 8 14:34:09 2014 -0700 storm: deassert SW_RESET signal at startup The proto0.2 hardware connects gpio26 (sw reset) to the ethernet switch reset pit. The output stays low (or high-z) after power up, which holds the switch in reset. Deassert the signal at startup on hardware rev 1 and later. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154 Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217087 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index ded423a..ebe2849 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -91,10 +91,24 @@ static void setup_tpm(void) gpio_set_out_value(TPM_RESET_GPIO, 1); } +#define SW_RESET_GPIO 26 +static void deassert_sw_reset(void) +{ + if (board_id() == 0) + return; + + /* only proto0.2 and later care about this. */ + gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, + GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); + + gpio_set_out_value(SW_RESET_GPIO, 1); +} + static void mainboard_init(device_t dev) { setup_mmu(); setup_usb(); + deassert_sw_reset(); setup_tpm(); }

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Patch set updated for coreboot: 5b079c9 storm: fix SW_RESET signal polarity
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9121 -gerrit commit 5b079c9d8ca23fbb450a70be15ee7853eccdc740 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 9 20:41:33 2014 -0700 storm: fix SW_RESET signal polarity The actual level required to take the ethernet switch out of reset is low, not high. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353 Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217416 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index ebe2849..3da6f90 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -97,11 +97,16 @@ static void deassert_sw_reset(void) if (board_id() == 0) return; - /* only proto0.2 and later care about this. */ + /* + * only proto0.2 and later care about this. This signal is eventually + * driving the ehernet switch reset input, which is active low. But + * since this signal gets inverted along the way, the GPIO needs to be + * driven low to take the switch out of reset. + */ gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); - gpio_set_out_value(SW_RESET_GPIO, 1); + gpio_set_out_value(SW_RESET_GPIO, 0); } static void mainboard_init(device_t dev)

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Patch set updated for coreboot: cdb0881 storm: need larger CBFS cache
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9122 -gerrit commit cdb08815c2cee83c84ecf42d13dd013d38cef498 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 23 14:15:29 2014 -0700 storm: need larger CBFS cache With VPD blob of certain format, CBFS cache on storm proves to be not large enough. This patch makes it bigger, it is still well above the area preserved for the NSS. BUG=chrome-os-partner:32152 TEST=the system now boots with the VPD it used to fail booting. Change-Id: Iee1214b218ee3f8aca28797841501c227549affb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6f19ca8cb9a2efa1d295f038730ed06ec9ceb8c4 Original-Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 395c329..fc78ecc 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -65,11 +65,11 @@ config STACK_BOTTOM config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" - default 0x405e6000 + default 0x405cc000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x00016000 + default 0x00030000 config TTB_BUFFER hex "memory address for page tables"

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Patch set updated for coreboot: 45fee78 storm: make sure board ID is calculated only once
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9119 -gerrit commit 45fee7814d97729cd674a08dbc535fc143b18677 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 8 14:04:08 2014 -0700 storm: make sure board ID is calculated only once Figuring out board_id on storm requires reading tertiary gpios, which takes time. Let's calculate it once and reuse it when necessary. BUG=none TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2 respectively. Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1 Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217086 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/boardid.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 6d7a918..683b5f4 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -37,7 +37,9 @@ * revision. */ -uint8_t board_id(void) +static int board_id_value = -1; + +static uint8_t get_board_id(void) { uint8_t bid; gpio_t hw_rev_gpios[] = {29, 30, 68}; @@ -50,3 +52,11 @@ uint8_t board_id(void) return bid; } + +uint8_t board_id(void) +{ + if (board_id_value < 0) + board_id_value = get_board_id(); + + return board_id_value; +}

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Patch set updated for coreboot: 8068cb6 storm: reset TPM properly on proto0
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9118 -gerrit commit 8068cb62c218ae1dca7b699b50436934c0905866 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Aug 7 15:20:21 2014 -0700 storm: reset TPM properly on proto0 The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22 pin instead of the system reset. This causes all kind of TPM behavior problems and requires frequent power cycles. Adding explicit TPM reset makes all those problems go away. BUG=chrome-os-partner:30705, chrome-os-partner:30829 TEST=tried resetting proto0 at different moments during boot up - the TPM does not fail anymore. Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6 Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211497 Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 8982f91..ded423a 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -18,10 +18,12 @@ */ #include <arch/cache.h> +#include <boardid.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <device/device.h> #include <delay.h> +#include <device/device.h> +#include <gpiolib.h> #include <string.h> #include <soc/qualcomm/ipq806x/include/clock.h> @@ -71,10 +73,29 @@ static void setup_mmu(void) dcache_mmu_enable(); } +#define TPM_RESET_GPIO 22 +static void setup_tpm(void) +{ + if (board_id() != 0) + return; /* Only proto0 have TPM reset connected to GPIO22 */ + + gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, + GPIO_4MA, GPIO_ENABLE); + /* + * Generate a reset pulse. The spec calls for 80 us minimum, let's + * make it twice as long. If the output was driven low originally, the + * reset pulse will be even longer. + */ + gpio_set_out_value(TPM_RESET_GPIO, 0); + udelay(160); + gpio_set_out_value(TPM_RESET_GPIO, 1); +} + static void mainboard_init(device_t dev) { setup_mmu(); setup_usb(); + setup_tpm(); } static void mainboard_enable(device_t dev)

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Patch set updated for coreboot: 0d19fe4 storm: supply vboot GPIO settings in coreboot table
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9117 -gerrit commit 0d19fe411466b857b7ee18925099734f95426317 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Aug 1 17:36:45 2014 -0700 storm: supply vboot GPIO settings in coreboot table Storm provides three real and two fake gpios. To keep things simple, define them all as active low and provide appropriate values for the fake ones. BUG=chrome-os-partner:30705 TEST=with the appropriate depthcharge change booted proto0, observed appropriate behavior following the dev switch setting Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210922 --- src/mainboard/google/storm/mainboard.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 94f3a92..8982f91 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -19,7 +19,11 @@ #include <arch/cache.h> #include <boot/coreboot_tables.h> +#include <console/console.h> #include <device/device.h> +#include <delay.h> +#include <string.h> + #include <soc/qualcomm/ipq806x/include/clock.h> #include <soc/qualcomm/ipq806x/include/gpio.h> #include <soc/qualcomm/ipq806x/include/usb.h> @@ -93,3 +97,27 @@ void lb_board(struct lb_header *header) dma->range_start = CONFIG_DRAM_DMA_START; dma->range_size = CONFIG_DRAM_DMA_SIZE; } + +static int read_gpio(gpio_t gpio_num) +{ + gpio_tlmm_config_set(gpio_num, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); + udelay(10); /* Should be enough to settle. */ + return gpio_get_in_value(gpio_num); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + const int GPIO_COUNT = 5; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, 15, ACTIVE_LOW, "developer", read_gpio(15)); + fill_lb_gpio(gpio++, 16, ACTIVE_LOW, "recovery", read_gpio(16)); + fill_lb_gpio(gpio++, 17, ACTIVE_LOW, "write protect", read_gpio(17)); + fill_lb_gpio(gpio++, -1, ACTIVE_LOW, "power", 1); + fill_lb_gpio(gpio++, -1, ACTIVE_LOW, "lid", 0); +}

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Patch set updated for coreboot: 0a3f936 cbfs/rmodule: add architecture specific operations at stage load
by Aaron Durbin 27 Mar '15

27 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8837 -gerrit commit 0a3f9364b061b96bc388c426fb46b19176b91b8e Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jan 9 13:14:20 2015 +0000 cbfs/rmodule: add architecture specific operations at stage load Two weak functions were added so that architecture specific operations on each segment of payload or stage can be performed. Each architecture must define its own operations, otherwise the behavior will default to do-nothing functions. This patch has been updated by to fit more in line with how program loading is currently being done. The API is the same as the original, but all call sites to stages/payloads have been updated. This is known to break any archs that use rmodule loading that needs cache maintenance. That will be fixed in a forthcoming patch. Also, the vboot paths are left as is for easier upstreaming of the rest of the vboot patches. Original-Change-Id: Ie29e7f9027dd430c8b4dde9848fa3413c5dbfbfa Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239881 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit c82c21ce87a4c02bd9219548a4226a58e77beef0) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ifcee5cd9ac5dbca991556296eb5e170b47b77af7 --- src/include/program_loading.h | 7 +++++++ src/lib/Makefile.inc | 4 ++++ src/lib/arch_ops.c | 33 +++++++++++++++++++++++++++++++++ src/lib/cbfs.c | 3 +++ src/lib/rmodule.c | 6 ++++-- src/lib/selfboot.c | 14 ++++++++++++++ 6 files changed, 65 insertions(+), 2 deletions(-) diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 32f80e1..21d2c1e 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2015 Google Inc. + * Copyright (C) 2014 Imagination Technologies * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,12 @@ #include <stdint.h> #include <stddef.h> +/* For each segment of a program loaded this function is called*/ +void arch_program_segment_loaded(uintptr_t start, size_t size); + +/* Upon completion of loading a program this function is called */ +void arch_program_loaded(void); + /************************ * ROMSTAGE LOADING * ************************/ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index beb3abe..3d92617 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -18,6 +18,7 @@ # subdirs-y += loaders +bootblock-y += arch_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c @@ -25,6 +26,7 @@ bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c +verstage-y += arch_ops.c verstage-y += delay.c verstage-y += cbfs.c verstage-y += memcmp.c @@ -33,6 +35,7 @@ verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c verstage-y += tlcl.c verstage-$(CONFIG_GENERIC_UDELAY) += timer.c +romstage-y += arch_ops.c romstage-y += memchr.c romstage-y += memcmp.c $(foreach arch,$(ARCH_SUPPORTED),\ @@ -57,6 +60,7 @@ romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += gcc.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += gcc.c endif +ramstage-y += arch_ops.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c ramstage-y += coreboot_table.c diff --git a/src/lib/arch_ops.c b/src/lib/arch_ops.c new file mode 100644 index 0000000..f02b342 --- /dev/null +++ b/src/lib/arch_ops.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <program_loading.h> + +/* For each segment of a program loaded this function is called*/ +__attribute__ ((weak)) void arch_program_segment_loaded(uintptr_t start, + size_t size) +{ + /* do nothing */ +} + +/* Upon completion of loading a program this function is called */ +__attribute__ ((weak)) void arch_program_loaded(void) +{ + /* do nothing */ +} diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9771412..c0a61b4 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -19,6 +19,7 @@ */ +#include <program_loading.h> #include "cbfs_core.h" #ifndef __SMM__ @@ -111,6 +112,8 @@ void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset) media->unmap(media, data); } + arch_program_segment_loaded(stage.load, stage.memlen); + arch_program_loaded(); DEBUG("stage loaded\n"); return (void *)(uintptr_t)stage.entry; diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 8d96e8d..c2bf33c 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -22,8 +22,8 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> -#include <arch/cache.h> #include <console/console.h> +#include <program_loading.h> #include <rmodule.h> /* Change this define to get more verbose debugging for module loading. */ @@ -200,7 +200,9 @@ int rmodule_load(void *base, struct rmodule *module) return -1; rmodule_clear_bss(module); - cache_sync_instructions(); + arch_program_segment_loaded((uintptr_t)module->location, + rmodule_memory_size(module)); + arch_program_loaded(); return 0; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 4c5fbad..fe73c0c 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -437,8 +437,22 @@ static int load_self_segments( memcpy((char*)to, (char*)from, amount); } } + + /* + * Each architecture can perform additonal operations + * on the loaded segment + */ + arch_program_segment_loaded((uintptr_t)dest, + ptr->s_memsz); } } + + /* + * Each architecture can perform additonal operations once the entire + * program is loaded + */ + arch_program_loaded(); + return 1; }

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New patch to review for coreboot: 501d25c storm: need larger CBFS cache
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9122 -gerrit commit 501d25cf254e4be05be8dee18a1f64ff9d501941 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 23 14:15:29 2014 -0700 storm: need larger CBFS cache With VPD blob of certain format, CBFS cache on storm proves to be not large enough. This patch makes it bigger, it is still well above the area preserved for the NSS. BUG=chrome-os-partner:32152 TEST=the system now boots with the VPD it used to fail booting. Change-Id: Iee1214b218ee3f8aca28797841501c227549affb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6f19ca8cb9a2efa1d295f038730ed06ec9ceb8c4 Original-Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 395c329..fc78ecc 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -65,11 +65,11 @@ config STACK_BOTTOM config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" - default 0x405e6000 + default 0x405cc000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x00016000 + default 0x00030000 config TTB_BUFFER hex "memory address for page tables"

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New patch to review for coreboot: 0bf0ca9 storm: fix SW_RESET signal polarity
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9121 -gerrit commit 0bf0ca9cd2477288042842f46bfc5cf0e6c61c9b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Sep 9 20:41:33 2014 -0700 storm: fix SW_RESET signal polarity The actual level required to take the ethernet switch out of reset is low, not high. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353 Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217416 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0482af0..b089967 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -97,11 +97,16 @@ static void deassert_sw_reset(void) if (board_id() == 0) return; - /* only proto0.2 and later care about this. */ + /* + * only proto0.2 and later care about this. This signal is eventually + * driving the ehernet switch reset input, which is active low. But + * since this signal gets inverted along the way, the GPIO needs to be + * driven low to take the switch out of reset. + */ gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); - gpio_set_out_value(SW_RESET_GPIO, 1); + gpio_set_out_value(SW_RESET_GPIO, 0); } static void mainboard_init(device_t dev)

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New patch to review for coreboot: 6c671b6 storm: deassert SW_RESET signal at startup
by Patrick Georgi 27 Mar '15

27 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9120 -gerrit commit 6c671b69fe42095f736adee0f4c85eba0a98d80f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Sep 8 14:34:09 2014 -0700 storm: deassert SW_RESET signal at startup The proto0.2 hardware connects gpio26 (sw reset) to the ethernet switch reset pit. The output stays low (or high-z) after power up, which holds the switch in reset. Deassert the signal at startup on hardware rev 1 and later. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154 Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217087 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/storm/mainboard.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 268ed46..0482af0 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -91,10 +91,24 @@ static void setup_tpm(void) gpio_set_out_value(TPM_RESET_GPIO, 1); } +#define SW_RESET_GPIO 26 +static void deassert_sw_reset(void) +{ + if (board_id() == 0) + return; + + /* only proto0.2 and later care about this. */ + gpio_tlmm_config_set(SW_RESET_GPIO, FUNC_SEL_GPIO, + GPIO_PULL_UP, GPIO_4MA, GPIO_ENABLE); + + gpio_set_out_value(SW_RESET_GPIO, 1); +} + static void mainboard_init(device_t dev) { setup_mmu(); setup_usb(); + deassert_sw_reset(); setup_tpm(); }

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coreboot-gerrit March 2015