coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/common/firmware: Add option to configure SPI for EM100
by Martin Roth 03 Dec '15

03 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12637 -gerrit commit d665252687efaa2fda3e8c97ee5c9d974e1fbee5 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:27:45 2015 -0700 intel/common/firmware: Add option to configure SPI for EM100 Add a Kconfig option to set the firmware descriptor to allow EM100 use. Change-Id: If5d7cd6ad671f0328ee5be0b5e660dbc837fcac3 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/southbridge/intel/common/firmware/Kconfig | 6 ++++++ src/southbridge/intel/common/firmware/Makefile.inc | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 316ade4..62b9a31 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -34,6 +34,12 @@ config IFD_BIN_PATH default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD +config EM100 + bool "Configure IFD for EM100 usage" + depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD + help + Set SPI frequency to 20MHz and disable Dual Output Fast Read Support + config HAVE_ME_BIN bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 49a4434..3cf2159 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -71,6 +71,12 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif +ifeq ($(CONFIG_EM100),y) + printf " IFDTOOL Setting EM100 mode\n" + $(objutil)/ifdtool/ifdtool -e $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif + PHONY+=add_intel_firmware endif

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New patch to review for coreboot: southbridge/intel/fspi89xx: Don't include common/firmware makefile
by Martin Roth 03 Dec '15

03 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12636 -gerrit commit 393d550f726466c1c64cf491f52d3c06fea46d1d Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:29:33 2015 -0700 southbridge/intel/fspi89xx: Don't include common/firmware makefile The folder southbridge/intel/common/firmware is already being included so does not need to be added a second time here. Change-Id: I60d795a60c772547278a5a5e0c9a023a93f90417 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/southbridge/intel/fsp_i89xx/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/southbridge/intel/fsp_i89xx/Makefile.inc b/src/southbridge/intel/fsp_i89xx/Makefile.inc index b93d941..42a44e7 100644 --- a/src/southbridge/intel/fsp_i89xx/Makefile.inc +++ b/src/southbridge/intel/fsp_i89xx/Makefile.inc @@ -20,8 +20,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX),y) -subdirs-y += ../common/firmware - ramstage-y += pch.c ramstage-y += lpc.c ramstage-y += sata.c

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New patch to review for coreboot: intel/littleplains: Update with recent changes to mohonpeak
by Martin Roth 03 Dec '15

03 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12635 -gerrit commit 9d85a0d4707ed1b2db15a89b5d34b4a0fa725550 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 14:02:16 2015 -0700 intel/littleplains: Update with recent changes to mohonpeak - Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/Kconfig | 12 ++++-------- src/mainboard/intel/littleplains/config_seabios | 5 +++++ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig index 2fc5cb1..55a4757 100644 --- a/src/mainboard/intel/littleplains/Kconfig +++ b/src/mainboard/intel/littleplains/Kconfig @@ -58,16 +58,12 @@ config UART_FOR_CONSOLE help The Little Plains board uses COM2 (2f8) for the serial console. -config SEABIOS_MALLOC_UPPERMEMORY - bool - default n - help + config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" + help The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment. -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff60040 - endif # BOARD_INTEL_LITTLEPLAINS diff --git a/src/mainboard/intel/littleplains/config_seabios b/src/mainboard/intel/littleplains/config_seabios new file mode 100644 index 0000000..f688f2b --- /dev/null +++ b/src/mainboard/intel/littleplains/config_seabios @@ -0,0 +1,5 @@ +# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 +# segment. This means that USB/SATA devices will not work in SeaBIOS unless +# we put the SeaBIOS buffer area down in the 0x9000 segment. + +# CONFIG_MALLOC_UPPERMEMORY is not set

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Patch merged into coreboot/master: SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY option
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 6e1192019eec85f3d8166970d2bf130c82471dd6 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 16:32:25 2015 -0700 SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY option This has been replaced by the PAYLOAD_CONFIGFILE option, allowing any SeaBIOS config option to be set by a platform. Change-Id: I584c4c481266740840158baba76581d68e69b448 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12570 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/12570 for details. -gerrit

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Patch merged into coreboot/master: intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit c6a8d2ca7b80dc82f9a119379bff2106bcb6e405 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 16:30:40 2015 -0700 intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12569 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/12569 for details. -gerrit

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Patch merged into coreboot/master: payloads/external/SeaBIOS: Add option for saved SeaBIOS .config
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 99d05c74b6f32aa667364d5dd4b10b9e512acbb7 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 15:44:34 2015 -0700 payloads/external/SeaBIOS: Add option for saved SeaBIOS .config Instead of adding various SeaBIOS options into the coreboot Kconfig, just add a way to use saved SeaBIOS .config files. These files can contain full SeaBIOS .configs, but is really intended for individual options. The coreboot Kconfig options take precedence over the settings in the saved .config. Change-Id: Ia7f9c76555b8e290777207b3f637c94c4d67a782 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12568 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/12568 for details. -gerrit

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New patch to review for coreboot: xcompile: Don't warn on missing power8 compiler
by Martin Roth 03 Dec '15

03 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12634 -gerrit commit b1f80ca41b1cb8b10be47a157e26f50bf1888e7f Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 3 12:38:27 2015 -0700 xcompile: Don't warn on missing power8 compiler Until there's a reason to, don't print a warning about the missing power8 compiler. Change-Id: I47c60e0a16892f0fa228e1439e0424926bca00a4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 7f44df6..635bcd6 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -351,7 +351,7 @@ test_architecture() { CLANG="clang -target ${clang_arch}-${TABI} -ccc-gcc-name ${GCC}" fi - if [ -z "$GCC" -a -z "$CLANG" ]; then + if [ -z "$GCC" -a -z "$CLANG" -a "power8" != "$architecture" ]; then echo "Warning: no suitable compiler for $architecture." >&2 return 1 fi

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New patch to review for coreboot: cbfs: Fix typo in cbfs_prog_stage_load()
by Julius Werner 03 Dec '15

03 Dec '15

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12633 -gerrit commit ba72a9406cacacce1c4296cf0b75e343464e84c7 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Dec 3 11:29:12 2015 -0800 cbfs: Fix typo in cbfs_prog_stage_load() The proper return value to signal an error from cbfs_prog_stage_load() is -1, not 0. Change-Id: Ie53b0359c7c036e3f809d1f941dab53f090b84ab Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/lib/cbfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 57b64dd..c782818 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -202,7 +202,7 @@ int cbfs_prog_stage_load(struct prog *pstage) const struct region_device *fh = prog_rdev(pstage); if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) - return 0; + return -1; fsize = region_device_sz(fh); fsize -= sizeof(stage);

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Patch set updated for coreboot: Rangeley: Change A, A, A, A INT routing to A, A, A, B
by Martin Roth 03 Dec '15

03 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12630 -gerrit commit 63a403565cd7ab25bd694cbf989d587df8d2ea8e Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 2 16:24:00 2015 -0700 Rangeley: Change A, A, A, A INT routing to A, A, A, B Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/irqroute.h | 6 +++--- src/mainboard/intel/mohonpeak/irqroute.h | 8 +++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/littleplains/irqroute.h b/src/mainboard/intel/littleplains/irqroute.h index 2f18345..5f0794a 100644 --- a/src/mainboard/intel/littleplains/irqroute.h +++ b/src/mainboard/intel/littleplains/irqroute.h @@ -41,12 +41,12 @@ PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* @@ -66,4 +66,4 @@ PIRQ_PIC(G, 14), \ PIRQ_PIC(H, 15) -#endif /* IRQROUTE_H */ \ No newline at end of file +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h index 2f18345..913ae52 100644 --- a/src/mainboard/intel/mohonpeak/irqroute.h +++ b/src/mainboard/intel/mohonpeak/irqroute.h @@ -34,6 +34,8 @@ * IR13h SATA3.0 INT(A) - PIRQ A * IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + + /* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ @@ -41,12 +43,12 @@ PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* @@ -66,4 +68,4 @@ PIRQ_PIC(G, 14), \ PIRQ_PIC(H, 15) -#endif /* IRQROUTE_H */ \ No newline at end of file +#endif /* IRQROUTE_H */

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Patch merged into coreboot/master: add support for power8 to xcompile script
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit b135baa0dbcd8a3f1a1fa0a156c17406149bd8d9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Dec 2 20:24:15 2015 +0000 add support for power8 to xcompile script power8 is set up by ibm as a powerpc subset, so we follow that rule here: we call it a powerpc but require -mcpu=power8 Change-Id: Ib5212be22db9584b0dc0eeed5c06ec1924347067 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://review.coreboot.org/12624 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12624 for details. -gerrit

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coreboot-gerrit December 2015