coreboot-gerrit December 2015

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Patch set updated for coreboot: MAINTAINERS: define all subsystems and their files
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10530 -gerrit commit e97ce9e89bfaf11e63ad83eeafa15bd52c89f323 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 12 15:30:59 2015 -0700 MAINTAINERS: define all subsystems and their files Initial list of subsystems and the files that belong to that subsystem, so we can define maintainers for them. Change-Id: Icde0f387b486bea1bb63f9bbdf6330fa0a3ebcfa Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 155 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index bb589c7..94bae6a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -123,6 +123,7 @@ RISC-V ARCHITECTURE M: Ronald Minnich <rminnich(a)gmail.com> S: Maintained F: src/arch/riscv/ +F: src/soc/ucb/ F: src/mainboard/emulation/qemu-riscv/ GOOGLE PANTHER MAINBOARD @@ -148,12 +149,84 @@ F: src/vendorcode/intel/fsp1_0/ ATI MACH64 Driver S: Orphan -F: drivers/ati/mach64/ +F: src/drivers/ati/mach64/ + +ABUILD +M: Patrick Georgi <patrick(a)georgi-clan.de> +S: Supported +F: util/abuild/ + +ACPI +F: src/acpi/ +F: src/arch/x86/acpi/ +F: util/acpi/ + +ARM ARCHITECTURE +F: src/arch/arm/ +F: src/arch/arm64 +F: src/cpu/allwinner/ +F: src/cpu/armltd/ +F: src/cpu/samsung/ +F: src/cpu/ti/ +F: src/soc/broadcom/ +F: src/soc/marvell/ +F: src/soc/nvidia/ +F: src/soc/qualcomm/ +F: src/soc/rockchip/ +F: src/soc/samsung/ +F: util/arm_boot_tools/ +F: util/broadcom/ +F: util/exynos/ +F: util/ipqheader/ +F: util/nvidia/ +F: util/rockchip/ + +MIPS ARCHITECTURE +F: src/arch/mips/ +F: src/cpu/mips/ +F: src/soc/imgtec/ +F: util/bimgtool/ + +X86 ARCHITECTURE +F: src/arch/x86/ +F: src/cpu/x86/ +F: src/drivers/pc80/ +F: src/include/pc80/ +F: src/include/cpu/x86/ + +INTEL SUPPORT +F: src/vendorcode/intel/ +F: src/cpu/intel/ +F: src/northbridge/intel/ +F: src/southbridge/intel/ +F: src/soc/intel/ +F: src/drivers/intel/ +F: src/include/cpu/intel/ + +AMD SUPPORT +F: src/vendorcode/amd/ +F: src/cpu/amd/ +F: src/northbridge/amd/ +F: src/southbridge/amd/ +F: src/include/cpu/amd/ + +VIA SUPPORT +F: src/cpu/via/ +F: src/northbridge/via/ +F: src/southbridge/via/ LINT SCRIPTS M: Patrick Georgi <patrick(a)georgi-clan.de> S: Supported F: util/lint/ +INTELTOOL +M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> +F: util/inteltool/ + +IFDTOOL +M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> +F: util/ifdtool/ +F: util/ifdfake/ BUILD SYSTEM M: Patrick Georgi <patrick(a)georgi-clan.de> @@ -161,9 +234,89 @@ M: Martin Roth <gaumless(a)gmail.com> S: Supported F: Makefile F: *.inc +F: src/include/kconfig.h F: util/kconfig/ F: util/sconfig/ +BOARD STATUS +F: util/board_status/ + +BINARY OBJECTS +F: 3rdparty/blobs/ + +VERIFIED BOOT +F: 3rdparty/vboot/ +F: src/vendorcode/google/chromeos/ +F: src/include/tpm.h +F: src/include/tpm_lite/ + +RESOURCE ALLOCATOR +F: src/device/* +F: src/include/device/ +F: src/include/cpu/cpu.h + +OPTION ROM EXECUTION & X86EMU +F: src/device/oprom/ + +CBFS +F: src/include/cbfs.h +F: src/include/cbfs_serialized.h +F: util/cbfstool/ + +CBMEM +F: src/include/cbmem.h +F: src/include/cbmem_id.h +F: util/cbmem/ + +CONSOLE +F: src/console/ +F: src/include/console/ +F: src/drivers/uart/ + +NVRAM +F: util/nvramtool/ +F: util/optionlist/ +F: payloads/nvramcui/ + +LIBPAYLOAD +F: payloads/libpayload/ + +BAYOU PAYLOAD +F: payloads/bayou/ + +COREINFO PAYLOAD +F: payloads/coreinfo/ + +EXTERNAL PAYLOADS INTEGRATION +M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> +F: payloads/external + +VERIFIED BOOT 2 +M: Aaron Durbin <adurbin(a)chromium.org> +F: src/vendorcode/google/chromeos/vboot2/ + +MISSING: TIMERS / DELAYS + +MISSING: TIMESTAMPS + +MISSING: MEMLAYOUT + +MISSING: FMAP + +MISSING: GPIO + +MISSING: SMP + +MISSING: SUPERIOS + +MISSING: DMP / QEMU-X86 + +MISSING: ELOG + +MISSING: GENERIC DRAM (should drop) + +MISSING: SPI + THE REST M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> L: coreboot(a)coreboot.org

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Patch set updated for coreboot: braswell/skylake: Add FspUpdVpd.h to fix compilation
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12467 -gerrit commit f41978669a8bf36a94b260dba17ffd8476b37696 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:32:27 2015 -0800 braswell/skylake: Add FspUpdVpd.h to fix compilation Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/braswell/Makefile.inc | 1 + src/soc/intel/skylake/Makefile.inc | 1 + .../intel/fsp/fsp1_1/braswell/FspUpdVpd.h | 507 ++++++++++++++ .../intel/fsp/fsp1_1/skylake/FspUpdVpd.h | 740 +++++++++++++++++++++ 4 files changed, 1249 insertions(+) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 426f359..54b9c6a 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -54,6 +54,7 @@ smm-y += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 682f90d..e824f2a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -73,6 +73,7 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h new file mode 100644 index 0000000..9b9df0e --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h @@ -0,0 +1,507 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(push, 1) + + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT32 VendorDeviceId; + UINT16 SubSystemId; + UINT8 RevisionId; /// 0xFF applies to all steppings + UINT8 FrontPanelSupport; + UINT16 NumberOfRearJacks; + UINT16 NumberOfFrontJacks; +} BL_PCH_AZALIA_VERB_TABLE_HEADER; + +typedef struct { + BL_PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 *VerbTableData; +} BL_PCH_AZALIA_VERB_TABLE; + +typedef struct { + UINT8 Pme : 1; /// 0: Disable; 1: Enable + UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported + UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached + UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable + UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 3; + UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform + BL_PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) + UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds +} BL_PCH_AZALIA_CONFIG; + +typedef struct { + UINT32 Confg; + UINT32 ConfgChanges; + UINT32 Misc; + UINT32 MmioAddr; + CHAR16 *Name; +} BL_GPIO_FAMILY_INIT; + +typedef struct { + UINT32 Confg0; + UINT32 Confg0Changes; + UINT32 Confg1; + UINT32 Confg1Changes; + UINT32 Community; + UINT32 MmioAddr; + CHAR16 *Name; + UINT32 Misc; +} BL_GPIO_PAD_INIT; + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + UINT8 ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT8 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + + +typedef struct { +/** Offset 0x0020 +**/ + UINT64 Signature; +/** Offset 0x0028 +**/ + UINT8 Revision; +/** Offset 0x0029 +**/ + UINT8 UnusedUpdSpace2[7]; +/** Offset 0x0030 + Tseg Size + Size of SMRAM memory reserved. +**/ + UINT16 PcdMrcInitTsegSize; +/** Offset 0x0032 + MMIO Size + Size of memory address space reserved for MMIO (Memory Mapped I/O). +**/ + UINT16 PcdMrcInitMmioSize; +/** Offset 0x0034 + DIMM 0 SPD SMBus Address + SPD Address of DIMM. +**/ + UINT8 PcdMrcInitSpdAddr1; +/** Offset 0x0035 + DIMM 1 SPD SMBus Address + SPD Address of DIMM. +**/ + UINT8 PcdMrcInitSpdAddr2; +/** Offset 0x0036 +**/ + UINT8 PcdMemChannel0Config; +/** Offset 0x0037 +**/ + UINT8 PcdMemChannel1Config; +/** Offset 0x0038 +**/ + UINT32 PcdMemorySpdPtr; +/** Offset 0x003C + Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics +**/ + UINT8 PcdIgdDvmt50PreAlloc; +/** Offset 0x003D + Aperture Size + Select the Aperture Size. +**/ + UINT8 PcdApertureSize; +/** Offset 0x003E + GTT Size + Select the GTT Size. +**/ + UINT8 PcdGttSize; +/** Offset 0x003F + Enable Legacy E/F segments decoding to ROM + If disabled, E0000h-FFFFFh decoding will be routed to DRAM. +**/ + UINT8 PcdLegacySegDecode; +/** Offset 0x0040 + Enable DVFS + Enable/disable DVFS. +**/ + UINT8 PcdDvfsEnable; +/** Offset 0x0041 + MemoryType + To Configure Memory Type +**/ + UINT8 PcdMemoryTypeEnable; +/** Offset 0x0042 +**/ + UINT8 ReservedMemoryInitUpd[190]; +} MEMORY_INIT_UPD; + +typedef struct { +/** Offset 0x0100 +**/ + UINT64 Signature; +/** Offset 0x0108 +**/ + UINT8 Revision; +/** Offset 0x0109 +**/ + UINT8 UnusedUpdSpace3[7]; +/** Offset 0x0110 + SD Card Mode + SD Card Mode +**/ + UINT8 PcdSdcardMode; +/** Offset 0x0111 + Enable HSUART0 + Enable/disable HSUART0. +**/ + UINT8 PcdEnableHsuart0; +/** Offset 0x0112 + Enable HSUART1 + Enable/disable HSUART1. +**/ + UINT8 PcdEnableHsuart1; +/** Offset 0x0113 + Enable Azalia + Enable/disable Azalia controller. +**/ + UINT8 PcdEnableAzalia; +/** Offset 0x0114 +**/ + BL_PCH_AZALIA_CONFIG *AzaliaConfigPtr; +/** Offset 0x0118 + Enable SATA + Enable/disable SATA controller. +**/ + UINT8 PcdEnableSata; +/** Offset 0x0119 + Enable XHCI + Enable/disable XHCI controller. +**/ + UINT8 PcdEnableXhci; +/** Offset 0x011A + Enable LPE + Choose LPE Mode. +**/ + UINT8 PcdEnableLpe; +/** Offset 0x011B + Enable DMA0 + Enable/disable DMA0. +**/ + UINT8 PcdEnableDma0; +/** Offset 0x011C + Enable DMA1 + Enable/disable DMA1. +**/ + UINT8 PcdEnableDma1; +/** Offset 0x011D + Enable I2C0 + Enable/disable I2C0. +**/ + UINT8 PcdEnableI2C0; +/** Offset 0x011E + Enable I2C1 + Enable/disable I2C1. +**/ + UINT8 PcdEnableI2C1; +/** Offset 0x011F + Enable I2C2 + Enable/disable I2C2. +**/ + UINT8 PcdEnableI2C2; +/** Offset 0x0120 + Enable I2C3 + Enable/disable I2C3. +**/ + UINT8 PcdEnableI2C3; +/** Offset 0x0121 + Enable I2C4 + Enable/disable I2C4. +**/ + UINT8 PcdEnableI2C4; +/** Offset 0x0122 + Enable I2C5 + Enable/disable I2C5. +**/ + UINT8 PcdEnableI2C5; +/** Offset 0x0123 + Enable I2C6 + Enable/disable I2C6. +**/ + UINT8 PcdEnableI2C6; +/** Offset 0x0124 +**/ + UINT32 GraphicsConfigPtr; +/** Offset 0x0128 +**/ + BL_GPIO_FAMILY_INIT *GpioFamilyInitTablePtr; +/** Offset 0x012C +**/ + BL_GPIO_PAD_INIT *GpioPadInitTablePtr; +/** Offset 0x0130 +**/ + UINT8 PunitPwrConfigDisable; +/** Offset 0x0131 +**/ + UINT8 ChvSvidConfig; +/** Offset 0x0132 +**/ + UINT8 DptfDisable; +/** Offset 0x0133 + eMMC Mode + EMMC Mode +**/ + UINT8 PcdEmmcMode; +/** Offset 0x0134 +**/ + UINT8 PcdUsb3ClkSsc; +/** Offset 0x0135 +**/ + UINT8 PcdDispClkSsc; +/** Offset 0x0136 +**/ + UINT8 PcdSataClkSsc; +/** Offset 0x0137 +**/ + UINT8 Usb2Port0PerPortPeTxiSet; +/** Offset 0x0138 +**/ + UINT8 Usb2Port0PerPortTxiSet; +/** Offset 0x0139 +**/ + UINT8 Usb2Port0IUsbTxEmphasisEn; +/** Offset 0x013A +**/ + UINT8 Usb2Port0PerPortTxPeHalf; +/** Offset 0x013B +**/ + UINT8 Usb2Port1PerPortPeTxiSet; +/** Offset 0x013C +**/ + UINT8 Usb2Port1PerPortTxiSet; +/** Offset 0x013D +**/ + UINT8 Usb2Port1IUsbTxEmphasisEn; +/** Offset 0x013E +**/ + UINT8 Usb2Port1PerPortTxPeHalf; +/** Offset 0x013F +**/ + UINT8 Usb2Port2PerPortPeTxiSet; +/** Offset 0x0140 +**/ + UINT8 Usb2Port2PerPortTxiSet; +/** Offset 0x0141 +**/ + UINT8 Usb2Port2IUsbTxEmphasisEn; +/** Offset 0x0142 +**/ + UINT8 Usb2Port2PerPortTxPeHalf; +/** Offset 0x0143 +**/ + UINT8 Usb2Port3PerPortPeTxiSet; +/** Offset 0x0144 +**/ + UINT8 Usb2Port3PerPortTxiSet; +/** Offset 0x0145 +**/ + UINT8 Usb2Port3IUsbTxEmphasisEn; +/** Offset 0x0146 +**/ + UINT8 Usb2Port3PerPortTxPeHalf; +/** Offset 0x0147 +**/ + UINT8 Usb2Port4PerPortPeTxiSet; +/** Offset 0x0148 +**/ + UINT8 Usb2Port4PerPortTxiSet; +/** Offset 0x0149 +**/ + UINT8 Usb2Port4IUsbTxEmphasisEn; +/** Offset 0x014A +**/ + UINT8 Usb2Port4PerPortTxPeHalf; +/** Offset 0x014B +**/ + UINT8 Usb3Lane0Ow2tapgen2deemph3p5; +/** Offset 0x014C +**/ + UINT8 Usb3Lane1Ow2tapgen2deemph3p5; +/** Offset 0x014D +**/ + UINT8 Usb3Lane2Ow2tapgen2deemph3p5; +/** Offset 0x014E +**/ + UINT8 Usb3Lane3Ow2tapgen2deemph3p5; +/** Offset 0x014F + SATA Interface Speed + Select SATA controller Interface Speed. +**/ + UINT8 PcdSataInterfaceSpeed; +/** Offset 0x0150 +**/ + UINT8 PcdPchUsbSsicPort; +/** Offset 0x0151 +**/ + UINT8 PcdPchUsbHsicPort; +/** Offset 0x0152 +**/ + UINT8 PcdPcieRootPortSpeed; +/** Offset 0x0153 +**/ + UINT8 PcdPchSsicEnable; +/** Offset 0x0154 +**/ + UINT32 PcdLogoPtr; +/** Offset 0x0158 +**/ + UINT32 PcdLogoSize; +/** Offset 0x015C +**/ + UINT8 PcdRtcLock; +/** Offset 0x015D + PMIC I2c Bus Number + I2c Bus Number to communicate with PMIC +**/ + UINT8 PMIC_I2CBus; +/** Offset 0x015E + Enable ISP + Enable/disable ISP. +**/ + UINT8 ISPEnable; +/** Offset 0x015F + Select ISP Device Number + Select ISP PCI Device Configuration +**/ + UINT8 ISPPciDevConfig; +/** Offset 0x0160 + Processor Turbo Mode + Enable/disable Processor Turbo Mode. +**/ + UINT8 PcdTurboMode; +/** Offset 0x0161 +**/ + UINT8 ReservedSiliconInitUpd[413]; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +typedef struct _UPD_DATA_REGION { +/** Offset 0x0000 +**/ + UINT64 Signature; +/** Offset 0x0008 +**/ + UINT8 Revision; +/** Offset 0x0009 +**/ + UINT8 UnusedUpdSpace0[7]; +/** Offset 0x0010 +**/ + UINT32 MemoryInitUpdOffset; +/** Offset 0x0014 +**/ + UINT32 SiliconInitUpdOffset; +/** Offset 0x0018 +**/ + UINT64 UnusedUpdSpace1; +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; +/** Offset 0x0100 +**/ + SILICON_INIT_UPD SiliconInitUpd; +/** Offset 0x02FE +**/ + UINT16 PcdRegionTerminator; +/** Offset 0x0300 +**/ + UINT8 UnusedUpdSpace4[2123]; +/** Offset 0x0B4B +**/ + UINT8 PcdPaddingSpace; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ +#define FSP_IMAGE_REV 0x01010100 + +typedef struct _VPD_DATA_REGION { +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; +/** Offset 0x0008 + PcdImageRevision +**/ + UINT32 PcdImageRevision; +/** Offset 0x000C +**/ + UINT32 PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[20]; +/** Offset 0x0024 +**/ + UINT8 PcdEnableSecureBoot; +} VPD_DATA_REGION; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h new file mode 100644 index 0000000..be1f2f8 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h @@ -0,0 +1,740 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(push, 1) + + +#define MRC_MAX_RCOMP 3 +#define MRC_MAX_RCOMP_TARGETS 5 +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT16 RcompResistor[MRC_MAX_RCOMP]; ///< Offset 0: Reference RCOMP resistors on motherboard + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +} MEMORY_RCOMP; + + +typedef struct { + UINT32 VendorDeviceId; /* Vendor ID/Device ID */ + UINT16 SubSystemId; /* SubSystem ID */ + UINT8 RevisionId; /* Revision ID. 0xFF applies to all steppings */ + UINT8 FrontPanelSupport; /* Front panel support (1=yes, 2=no) */ + UINT16 NumberOfRearJacks; /* Number of Rear Jacks */ + UINT16 NumberOfFrontJacks; /* Number of Front Jacks */ +} SA_HDA_HEADER; + +typedef struct { + UINT16 VendorId; /* Codec Vendor ID */ + UINT16 DeviceId; /* Codec Device ID */ + UINT8 RevisionId; /* Revision ID of the codec. 0xFF matches any revision. */ + UINT8 SdiNo; /* SDI number, 0xFF matches any SDI. */ + UINT16 DataDwords; /* Number of data DWORDs pointed by the codec data buffer. */ + UINT32 Reserved; /* Reserved for future use. Must be set to 0. */ +} AZALIA_HEADER; + +typedef struct { + AZALIA_HEADER Header; /* AZALIA PCH header */ + UINT32 *Data; /* Pointer to the data buffer. Its length is specified in the header */ +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + + +/** UPD data structure for FspMemoryInitApi +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT64 Signature; + +/** Offset 0x0028 - Revision + Revision version of the MemoryInitUpd Region +**/ + UINT8 Revision; + +/** Offset 0x0029 +**/ + UINT8 UnusedUpdSpace0[7]; + +/** Offset 0x0030 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE + 0x400000 : 0x400000 +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0038 - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x003C - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0040 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0044 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data in Memory. Default: 0 for empty channel +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0056 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x0062 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x006A - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x0072 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x0078 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0082 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0083 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x0084 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x0085 - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0086 +**/ + UINT16 UnusedUpdSpace1; + +/** Offset 0x0088 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x008C - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0090 - MMIO Size + Size of memory address space reserved for MMIO (Memory Mapped I/O) in MB. + 0x0600 : 0x0600 +**/ + UINT16 MmioSize; + +/** Offset 0x0092 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x0093 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 EnableLan; + +/** Offset 0x0094 +**/ + UINT16 UnusedUpdSpace2; + +/** Offset 0x0096 - Enable Trace Hub + Enable/disable Trace Hub function. + $EN_DIS +**/ + UINT8 EnableTraceHub; + +/** Offset 0x0097 - Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpEnable[20]; + +/** Offset 0x00AB - Enable PCIE RP CLKREQ Support + Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpClkReqSupport[20]; + +/** Offset 0x00BF - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + UINT8 PcieRpClkReqNumber[20]; + +/** Offset 0x00D3 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0 MB, 0x01:32 MB, 0x02:64 MB, 0x03:128 MB, 0x04:256 MB, 0x05:512 MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x00D4 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x00D5 - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 2:512 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x00D6 - SA GV + System Agent dynamic frequency support and when enabled memory will be training at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, 2=FixedHigh, and 3=Enabled. + 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x00D7 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x00D8 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x00DA - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x00DB +**/ + UINT8 UnusedUpdSpace3[105]; + +/** Offset 0x0144 - MMA Test Content Pointer + Pointer to MMA Test Content in Memory +**/ + UINT32 MmaTestContentPtr; + +/** Offset 0x0148 - MMA Test Content Size + Size of MMA Test Content in Memory +**/ + UINT32 MmaTestContentSize; + +/** Offset 0x014C - MMA Test Config Pointer + Pointer to MMA Test Config in Memory +**/ + UINT32 MmaTestConfigPtr; + +/** Offset 0x0150 - MMA Test Config Size + Size of MMA Test Config in Memory +**/ + UINT32 MmaTestConfigSize; + +/** Offset 0x0154 - Enable CIO2 Controller + Enable/disable SKYCAM CIO2 Controller. + $EN_DIS +**/ + UINT8 Cio2Enable; + +/** Offset 0x0155 +**/ + UINT8 ReservedMemoryInitUpd[171]; +} MEMORY_INIT_UPD; + +/** UPD data structure for FspSiliconInitApi +**/ +typedef struct { + +/** Offset 0x0200 +**/ + UINT64 Signature; + +/** Offset 0x0208 - Revision + Revision version of the SiliconInitUpd Region +**/ + UINT8 Revision; + +/** Offset 0x0209 +**/ + UINT8 UnusedUpdSpace4[7]; + +/** Offset 0x0210 - Logo Pointer + Points to PEI Display Logo Image + 0 : 0 +**/ + UINT32 LogoPtr; + +/** Offset 0x0214 - Logo Size + Size of PEI Display Logo Image + 0 : 0 +**/ + UINT32 LogoSize; + +/** Offset 0x0218 - Graphics Configuration Ptr + Points to VBT + 0 : 0 +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x021C - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x021D - Enable Azalia + Enable/disable Azalia controller. + $EN_DIS +**/ + UINT8 EnableAzalia; + +/** Offset 0x021E - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 DspEnable; + +/** Offset 0x021F - Select HDAudio IoBuffer Ownership + Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers. + 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports +**/ + UINT8 IoBufferOwnership; + +/** Offset 0x0220 +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x0221 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + UINT8 ScsEmmcEnabled; + +/** Offset 0x0222 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcHs400Enabled; + +/** Offset 0x0223 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + UINT8 ScsSdCardEnabled; + +/** Offset 0x0224 - Enable ISH Controller + Enable/disable ISH Controller. + $EN_DIS +**/ + UINT8 IshEnable; + +/** Offset 0x0225 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + UINT8 ShowSpiController; + +/** Offset 0x0226 - HSIO HECI Messaging + Enable/Disable. 0: Disable, prevent the HSIO version check and HSIO init messages from being sent, 1: enable + $EN_DIS +**/ + UINT8 HsioMessaging; + +/** Offset 0x0227 - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x0228 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x022C - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0230 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0231 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0232 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x023A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x0242 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0252 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x025C - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x025D - Enable XHCI SSIC Eanble + Enable/disable XHCI SSIC port. + $EN_DIS +**/ + UINT8 SsicPortEnable; + +/** Offset 0x025E - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x025F - Enable SerialIo Device Mode + 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + UINT8 SerialIoDevMode[11]; + +/** Offset 0x026A - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x026E - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x026F - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x0277 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. + 0 : 0xFF +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x0278 - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. + 0 : 0xFF +**/ + UINT8 SciIrqSelect; + +/** Offset 0x0279 - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. + 0 : 0xFF +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x027A - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x027B - AzaliaVerbTableNumEntries + Number of Entries in Azalia Verb Table +**/ + UINT8 AzaliaVerbTableNumEntries; + +/** Offset 0x027C - AzaliaVerbTablePtr + Pointer to Array of pointers to Codec Table. +**/ + UINT32 AzaliaVerbTablePtr; + +/** Offset 0x0280 - RTC CMOS RAM LOCK + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 RtcLock; + +/** Offset 0x0281 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 EnableSata; + +/** Offset 0x0282 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0283 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2AfePetxiset[16]; + +/** Offset 0x0293 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2AfeTxiset[16]; + +/** Offset 0x02A3 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2AfePredeemp[16]; + +/** Offset 0x02B3 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. +**/ + UINT8 Usb2AfePehalfbit[16]; + +/** Offset 0x02C3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x02CD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x02D7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x02E1 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x02EB +**/ + UINT8 ReservedSiliconInitUpd[271]; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 Signature; + +/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +**/ + UINT8 Revision; + +/** Offset 0x0009 +**/ + UINT8 ReservedUpd0[7]; + +/** Offset 0x0010 - MemoryInitUpdOffset + This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 MemoryInitUpdOffset; + +/** Offset 0x0014 - SiliconInitUpdOffset + This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 SiliconInitUpdOffset; + +/** Offset 0x0018 +**/ + UINT64 ReservedUpd1; + +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; + +/** Offset 0x0200 +**/ + SILICON_INIT_UPD SiliconInitUpd; + +/** Offset 0x03FA - RegionTerminator + This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +**/ + UINT16 RegionTerminator; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */ +#define FSP_IMAGE_REV 0x01070000 + +/** VPD data structure +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; + +/** Offset 0x0008 - PcdImageRevision + This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +**/ + UINT32 PcdImageRevision; + +/** Offset 0x000C - PcdUpdRegionOffset + This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +**/ + UINT32 PcdUpdRegionOffset; + +/** Offset 0x0010 +**/ + UINT8 UnusedVpdSpace0[32]; + +/** Offset 0x0030 - PcdSerialIoUartDebugEnable + Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +**/ + UINT8 PcdSerialIoUartDebugEnable; + +/** Offset 0x0031 - PcdSerialIoUartNumber + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 PcdSerialIoUartNumber; + +/** Offset 0x0032 +**/ + UINT32 PcdSerialIoUartInputClock; +} VPD_DATA_REGION; + +#pragma pack(pop) + +#endif

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Patch merged into coreboot/master: mainboard/biostar/am1ml: Force basic SPI read mode
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit cd920bf1c07b35d497e4f16656cfcebe45aaf132 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Tue Dec 1 18:53:54 2015 +0300 mainboard/biostar/am1ml: Force basic SPI read mode This patch force AGESA to use basic SPI read mode. Without it board hangs during spi configure if W25Q32 chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> Reviewed-on: https://review.coreboot.org/12580 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12580 for details. -gerrit

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New patch to review for coreboot: build system: add dependencies for GRUB2 and FILO
by Patrick Georgi 04 Dec '15

04 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12641 -gerrit commit 34cff1861590d87ee177db73384e2f345a838e0a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Dec 4 16:52:18 2015 +0100 build system: add dependencies for GRUB2 and FILO Make sure the build system knows how to start building the various integrated payloads we support. Change-Id: I2128d09c78795e0a41b055975e9f7052e3d951ee Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/external/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index bfc24f1..344cbec 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -67,6 +67,7 @@ filo: CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) +payloads/external/FILO/filo/build/filo.elf: filo grub2: $(MAKE) -C payloads/external/GRUB2 -f Makefile.inc \ @@ -74,3 +75,5 @@ grub2: CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \ CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER) + +payloads/external/GRUB2/grub2/build/default_payload.elf: grub2

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Patch set updated for coreboot: mainboard/biostar/am1ml: Force basic SPI read mode
by Sergej Ivanov 04 Dec '15

04 Dec '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12580 -gerrit commit 4ed1074848fa0793ce1423daac3e1a1386bb1b35 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Tue Dec 1 18:53:54 2015 +0300 mainboard/biostar/am1ml: Force basic SPI read mode This patch force AGESA to use basic SPI read mode. Without it board hangs during spi configure if W25Q32 chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/mainboard/biostar/am1ml/BiosCallOuts.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index c87f465..318d9ba 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -118,6 +118,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.SataEnable = 1; FchParams_reset->FchReset.IdeEnable = 0; + FchParams_reset->Mode = 6; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

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Patch set updated for coreboot: esd/atom15: import esd atom15 board
by Michael Tasche 04 Dec '15

04 Dec '15

Michael Tasche (michael.tasche(a)esd.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12632 -gerrit commit e31a6754fa979f22521a2fd2f2fbab7ceb1ef454 Author: Michael Tasche <michael.tasche(a)esd.eu> Date: Thu Dec 3 17:07:01 2015 +0100 esd/atom15: import esd atom15 board This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche(a)esd.eu> --- src/mainboard/esd/Kconfig | 16 ++ src/mainboard/esd/Kconfig.name | 2 + src/mainboard/esd/atom15/Kconfig | 70 +++++++++ src/mainboard/esd/atom15/Kconfig.name | 2 + src/mainboard/esd/atom15/Makefile.inc | 17 ++ src/mainboard/esd/atom15/acpi/ec.asl | 0 src/mainboard/esd/atom15/acpi/mainboard.asl | 20 +++ src/mainboard/esd/atom15/acpi/superio.asl | 0 src/mainboard/esd/atom15/acpi_tables.c | 56 +++++++ src/mainboard/esd/atom15/board_info.txt | 4 + src/mainboard/esd/atom15/cmos.layout | 116 ++++++++++++++ src/mainboard/esd/atom15/devicetree.cb | 93 +++++++++++ src/mainboard/esd/atom15/dsdt.asl | 53 +++++++ src/mainboard/esd/atom15/fadt.c | 32 ++++ src/mainboard/esd/atom15/gpio.c | 231 ++++++++++++++++++++++++++++ src/mainboard/esd/atom15/irqroute.c | 18 +++ src/mainboard/esd/atom15/irqroute.h | 82 ++++++++++ src/mainboard/esd/atom15/mainboard.c | 41 +++++ src/mainboard/esd/atom15/romstage.c | 78 ++++++++++ 19 files changed, 931 insertions(+) diff --git a/src/mainboard/esd/Kconfig b/src/mainboard/esd/Kconfig new file mode 100644 index 0000000..3b9eb58 --- /dev/null +++ b/src/mainboard/esd/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ESD + +choice + prompt "Mainboard model" + +source "src/mainboard/esd/*/Kconfig.name" + +endchoice + +source "src/mainboard/esd/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "esd" + +endif # VENDOR_ESD diff --git a/src/mainboard/esd/Kconfig.name b/src/mainboard/esd/Kconfig.name new file mode 100644 index 0000000..a44d854 --- /dev/null +++ b/src/mainboard/esd/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ESD + bool "electronic system design" diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig new file mode 100644 index 0000000..3f4b76b --- /dev/null +++ b/src/mainboard/esd/atom15/Kconfig @@ -0,0 +1,70 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ESD_ATOM15 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select TSC_MONOTONIC_TIMER + select HAVE_ACPI_RESUME + +config MAINBOARD_DIR + string + default "esd/atom15" + +config MAINBOARD_PART_NUMBER + string + default "esd atom15" + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_FILE + string + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + +config CBFS_SIZE + hex + default 0x00300000 + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default y if FSP_PACKAGE_DEFAULT + +endif # BOARD_ESD_ATOM15 diff --git a/src/mainboard/esd/atom15/Kconfig.name b/src/mainboard/esd/atom15/Kconfig.name new file mode 100644 index 0000000..cab7e86 --- /dev/null +++ b/src/mainboard/esd/atom15/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ESD_ATOM15 + bool "Atom15" diff --git a/src/mainboard/esd/atom15/Makefile.inc b/src/mainboard/esd/atom15/Makefile.inc new file mode 100644 index 0000000..3074df2 --- /dev/null +++ b/src/mainboard/esd/atom15/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +ramstage-y += irqroute.c diff --git a/src/mainboard/esd/atom15/acpi/ec.asl b/src/mainboard/esd/atom15/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/esd/atom15/acpi/mainboard.asl b/src/mainboard/esd/atom15/acpi/mainboard.asl new file mode 100644 index 0000000..b032ee1 --- /dev/null +++ b/src/mainboard/esd/atom15/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/esd/atom15/acpi/superio.asl b/src/mainboard/esd/atom15/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/esd/atom15/acpi_tables.c b/src/mainboard/esd/atom15/acpi_tables.c new file mode 100644 index 0000000..48991f5 --- /dev/null +++ b/src/mainboard/esd/atom15/acpi_tables.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> // hexdump +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> +#include <baytrail/iomap.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* No TPM Present */ + gnvs->tpmp = 0; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/esd/atom15/board_info.txt b/src/mainboard/esd/atom15/board_info.txt new file mode 100644 index 0000000..b5099b3 --- /dev/null +++ b/src/mainboard/esd/atom15/board_info.txt @@ -0,0 +1,4 @@ +Category: sbc +ROM protocol: SPI +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout new file mode 100644 index 0000000..8aaa522 --- /dev/null +++ b/src/mainboard/esd/atom15/cmos.layout @@ -0,0 +1,116 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1719 64 h 0 timestamp_value1 +1783 64 h 0 timestamp_value2 +1847 64 h 0 timestamp_value3 +1911 64 h 0 timestamp_value4 +1975 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/esd/atom15/devicetree.cb b/src/mainboard/esd/atom15/devicetree.cb new file mode 100644 index 0000000..769a687 --- /dev/null +++ b/src/mainboard/esd/atom15/devicetree.cb @@ -0,0 +1,93 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/fsp_baytrail + + #### ACPI Register Settings #### + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + #### FSP register settings #### + register "PcdSataMode" = "SATA_MODE_AHCI" + register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" + register "PcdGttSize" = "GTT_SIZE_DEFAULT" + register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_4G_BIT" + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "8" + register "DIMMtRPtRCD" = "8" + register "DIMMtWR" = "8" + register "DIMMtWTR" = "4" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "4" + register "DIMMtFAW" = "27" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router - + device pci 02.0 off end # 8086 0F31 - GFX - + device pci 03.0 off end # 8086 0F38 - MIPI - + + device pci 10.0 off end # 8086 0F14 - EMMC Port - + device pci 11.0 off end # 8086 0F15 - SDIO Port - + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 off end # 8086 0F23 - SATA AHCI - + device pci 14.0 off end # 8086 0F35 - USB XHCI - + device pci 15.0 off end # 8086 0F28 - LP Engine Audio - + device pci 17.0 off end # 8086 0F50 - MMC Port - + device pci 18.0 on end # 8086 0F40 - SIO - DMA - + device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) - + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - + device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) - + device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) - + device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) - + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) EEPROM + device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) - + device pci 1a.0 off end # 8086 0F18 - TXE - + device pci 1b.0 off end # 8086 0F04 - HD Audio - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI - + device pci 1e.0 on end # 8086 0F06 - SIO - DMA - + device pci 1e.1 on end # 8086 0F08 - PWM 1 - + device pci 1e.2 on end # 8086 0F09 - PWM 2 - + device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart + device pci 1e.4 off end # 8086 0F0C - HSUART 2 - + device pci 1e.5 off end # 8086 0F0E - SPI - + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl new file mode 100644 index 0000000..63b9d03 --- /dev/null +++ b/src/mainboard/esd/atom15/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/esd/atom15/fadt.c b/src/mainboard/esd/atom15/fadt.c new file mode 100644 index 0000000..38b9bfd --- /dev/null +++ b/src/mainboard/esd/atom15/fadt.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baytrail/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt,facs,dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c new file mode 100644 index 0000000..f617de4 --- /dev/null +++ b/src/mainboard/esd/atom15/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ + GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ + GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ + GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ + GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ + GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ + GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ + GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ + GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ + GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ + GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ + GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ + GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ + GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ + GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ + GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ + GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ + GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ + GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ + GPIO_FUNC1, /* GPIO_S0_SC[040] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[041] - /SD3_PWREN */ + GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ + GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ + GPIO_NC, /* GPIO_S0_SC[055] - No Connect */ + GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ + GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ + GPIO_NC, /* GPIO_S0_SC[058] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[059] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[060] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ + GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ + GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ + GPIO_NC, /* GPIO_S0_SC[072] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[073] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[074] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[075] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[080] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[081] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[088] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[089] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ + GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ + GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ + GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_NC, /* GPIO_S5[00] - No Connect */ + GPIO_FUNC6, /* GPIO_S5[01] - PMC_WAKE_PCIE[1] */ + GPIO_FUNC6, /* GPIO_S5[02] - PMC_WAKE_PCIE[2] */ + GPIO_FUNC6, /* GPIO_S5[03] - PMC_WAKE_PCIE[3] */ + GPIO_NC, /* GPIO_S5[04] - No Connect */ + GPIO_NC, /* GPIO_S5[05] - No Connect */ + GPIO_NC, /* GPIO_S5[06] - No Connect */ + GPIO_NC, /* GPIO_S5[07] - No Connect */ + GPIO_NC, /* GPIO_S5[08] - No Connect */ + GPIO_NC, /* GPIO_S5[09] - No Connect */ + GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK */ + GPIO_NC, /* GPIO_S5[12] - No Connect */ + GPIO_NC, /* GPIO_S5[13] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ + GPIO_FUNC0, /* GPIO_S5[15] - PMC_WAKE_PCIE[0] */ + GPIO_FUNC(1, PULL_UP, 2K), /* GPIO_S5[16] - No Connect */ + GPIO_NC, /* GPIO_S5[17] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[18] - T360 */ + GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ + GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ + GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ + GPIO_NC, /* GPIO_S5[22] - No Connect */ + GPIO_NC, /* GPIO_S5[23] - No Connect */ + GPIO_NC, /* GPIO_S5[24] - No Connect */ + GPIO_NC, /* GPIO_S5[25] - No Connect */ + GPIO_NC, /* GPIO_S5[26] - No Connect */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - SW450-1 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - SW450-2 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - SW450-3 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - SW450-4 */ + GPIO_NC, /* GPIO_S5[31] - No Connect */ + GPIO_NC, /* GPIO_S5[32] - No Connect */ + GPIO_NC, /* GPIO_S5[33] - No Connect */ + GPIO_NC, /* GPIO_S5[34] - No Connect */ + GPIO_NC, /* GPIO_S5[35] - No Connect */ + GPIO_NC, /* GPIO_S5[36] - No Connect */ + GPIO_NC, /* GPIO_S5[37] - No Connect */ + GPIO_NC, /* GPIO_S5[38] - No Connect */ + GPIO_NC, /* GPIO_S5[39] - No Connect */ + GPIO_NC, /* GPIO_S5[40] - No Connect */ + GPIO_NC, /* GPIO_S5[41] - No Connect */ + GPIO_NC, /* GPIO_S5[42] - No Connect */ + GPIO_NC, /* GPIO_S5[43] - No Connect */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/esd/atom15/irqroute.c b/src/mainboard/esd/atom15/irqroute.c new file mode 100644 index 0000000..db8c512 --- /dev/null +++ b/src/mainboard/esd/atom15/irqroute.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/esd/atom15/irqroute.h b/src/mainboard/esd/atom15/irqroute.h new file mode 100644 index 0000000..f866069 --- /dev/null +++ b/src/mainboard/esd/atom15/irqroute.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 3), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/esd/atom15/mainboard.c b/src/mainboard/esd/atom15/mainboard.c new file mode 100644 index 0000000..70f96fc --- /dev/null +++ b/src/mainboard/esd/atom15/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c new file mode 100644 index 0000000..89fc9de --- /dev/null +++ b/src/mainboard/esd/atom15/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baytrail/romstage.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <baytrail/gpio.h> +#include "chip.h" + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry() +{ + +} + +/** + * Get function disables - most of these will be done automatically + * @param fd_mask + * @param fd2_mask + */ +void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +{ + +} + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ +void late_mainboard_romstage_entry() +{ + + configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + + printk(0, "SW450: %d %d %d %d\n", + read_ssus_gpio(27), + read_ssus_gpio(28), + read_ssus_gpio(29), + read_ssus_gpio(30) ); + +} + +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + u8 use_xhci = UpdData->PcdEnableXhci; + + /* Update XHCI UPD value if required */ + get_option(&use_xhci, "use_xhci_over_ehci"); + if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { + UpdData->PcdEnableXhci = use_xhci; + printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", + UpdData->PcdEnableXhci?"Enabled":"Disabled"); + } + + return; +}

1 0

Patch set updated for coreboot: device: Resolve hang when a PCI device requests 4GB or more of MMIO space
by Ben Frisch 04 Dec '15

04 Dec '15

Ben Frisch (bfrisch(a)xes-inc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12575 -gerrit commit 577c9756918b0ef0f346c8bf4c60d49ceb9e39f1 Author: Benjamin Frisch <bfrisch(a)xes-inc.com> Date: Mon Nov 30 12:23:31 2015 -0600 device: Resolve hang when a PCI device requests 4GB or more of MMIO space When a PCI device's BAR requests 4GB or more MMIO space coreboot assigns the device address 0. This results in the device overlapping DRAM and the boot hangs with no feedback explaining the issue. Resolve this hang by first detecting the exhaustion that available MMIO space under 4GB. Next, selectively ignore PCI device resource requests based on the algorithm that UEFI Firmware based on tianocore.org code does to accomplish the same. This also meets requirements of the PCI Firmware Specification 3.1 and Firmware Allocation of PCI Device Resources in Windows document which states that firmware shall not allocate resources to devices that cannot fit in available 32-bit MMIO space. Modern 64-bit Linux and 64-bit Windows since Windows Vista will rebalance, allocate, and assign resources above the 4GB boundry to 64-bit PCI device MMIO BARs resources as necessary as long 64-bit MMIO space is defined in the ACPI _CRS method and the pci=realloc kernel argument is provided in Linux. The determination of which large 64-bit PCI MMIO resource requests to ignore is based on how the exhaustion of available MMIO resources is handled by the tianocore.org UEFI Firmware implemenation. If a PCI MMIO resource request cannot be satisified, MMIO PCI resource requests of devices that are not on bus 0 are skipped in the following order to attempt to make room to satisfy the remaining PCI device MMIO space requests while keeping boot criticial devices enabled: 1) Resource requests of the current PCI device with the largest 64-bit MMIO resource request (without OPROMs) 2) Resource requests of the current PCI device with the largest 32-bit MMIO resource request (without OPROMs) 3) Resource requests of the current PCI device with the largest MMIO resource request (with OPROMs) TEST=Tested on internal coreboot port based on older upstream with device presenting 128 GB BAR with latest Linux kernel, additional testing help and feedback is appreciated. Builds locally. Change-Id: I0217d627ca77431075df5e24d49d6406c35893b7 Signed-off-by: Ben Frisch <bfrisch(a)xes-inc.com> --- src/device/Kconfig | 46 ++++++++++++++++ src/device/device.c | 124 ++++++++++++++++++++++++++++++++------------ src/device/device_util.c | 109 ++++++++++++++++++++++++++++++++++++++ src/device/pci_device.c | 64 ++++++++++++++++------- src/include/device/device.h | 4 ++ 5 files changed, 295 insertions(+), 52 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 0113545..b9a734d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -389,6 +389,52 @@ config SOFTWARE_I2C I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +choice SET_MAX_MEM_BAR_SIZE + prompt "Set Maximum memory BAR size to try to allocate " + optional + help + Select the maximum size PCI device memory BAR that coreboot will try + to allocate. If a BAR is found with a values above this size, coreboot + will disable the device and will not try to allocate any BARs. + + If unsure, leave this disabled, and coreboot will find and disable any + devices that are too large to be allocated by itself. The + disadvantage is a slight boot time increase if a device has to be + disabled. + +config MAX_BAR_SIZE_256MB + bool "256 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 256 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_512MB + bool "512 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 512 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_1GB + bool "1 GB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 1 GB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +endchoice + +config MAX_MEM_BAR_SIZE_TO_ALLOCATE + hex + default 0x10000000 if MAX_BAR_SIZE_256MB + default 0x20000000 if MAX_BAR_SIZE_512MB + default 0x40000000 if MAX_BAR_SIZE_1GB + default 0 + endmenu menu "Display" diff --git a/src/device/device.c b/src/device/device.c index e23c9de..dc39dfc 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -690,7 +690,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } -static void avoid_fixed_resources(struct device *dev) +static u8 avoid_fixed_resources(struct device *dev) { struct constraints limits; struct resource *res; @@ -743,9 +743,60 @@ static void avoid_fixed_resources(struct device *dev) if (res->flags & IORESOURCE_MEM) res->base = resource_max(res); + if (res->base < lim->base) { + /* This usually happens at the domain level, usually + * caused by a device having a BAR which is too big. + * Error out so we can retry. + */ + printk(BIOS_WARNING, + "ERROR: Resource Base was lower than its limit!\n\t"); + printk(BIOS_WARNING, + "%s@%02lx: base value 0x%08llx, lower limit 0x%08llx\n", + dev_path(dev), res->index, res->base, lim->base); + return 1; + } + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); } + + return 0; +} + +static u8 avoid_all_fixed_resources(struct device *root) +{ + struct device *child; + + /* For all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_DOMAIN) { + if (avoid_fixed_resources(child)) { + printk( + BIOS_SPEW, + "Error trying to avoid fixed resources."); + + /* Now find the device which is the largest + * and disable it. + */ + struct device *largest = find_pci_dev_max_mem(); + + printk(BIOS_SPEW, "\tDisabling Device %s\n", + dev_path(largest)); + if (largest) + largest->enabled = 0; + + /* Clear out all devices on all domains, ready + * for re-scanning. + */ + printk(BIOS_SPEW, + "\tClearing old resource computations.\n"); + clear_computed_resources(); + return 1; + } + } + } + + return 0; } device_t vga_pri = 0; @@ -1022,45 +1073,54 @@ void dev_configure(void) root = &dev_root; - /* - * Each domain should create resources which contain the entire address - * space for IO, MEM, and PREFMEM resources in the domain. The - * allocation of device resources will be done from this address space. - */ + do { + /* + * Each domain should create resources which contain the entire + * address space for IO, MEM, and PREFMEM resources in the + * domain. The allocation of device resources will be done from + * this address space. + */ - /* Read the resources for the entire tree. */ + /* Read the resources for the entire tree. */ - printk(BIOS_INFO, "Reading resources...\n"); - read_resources(root->link_list); - printk(BIOS_INFO, "Done reading resources.\n"); + printk(BIOS_INFO, "Reading resources...\n"); + read_resources(root->link_list); + printk(BIOS_INFO, "Done reading resources.\n"); - print_resource_tree(root, BIOS_SPEW, "After reading."); + print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + /* Compute resources for all domains. */ + for (child = root->link_list->children; + child; + child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources( + child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + continue; + } } } - } - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); + /* Attempt to avoid all fixed resources, if this process + * succeeds then we can carry on, otherwise we should re-try. + */ + } while (avoid_all_fixed_resources(root)); /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); diff --git a/src/device/device_util.c b/src/device/device_util.c index ac18538..5d0ba50 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -921,3 +921,112 @@ int dev_count_cpu(void) return count; } + +enum allocation_passes { + PASS_1_CHECK_64_BIT_BARS = 0, + PASS_2_CHECK_32_BIT_BARS = 1, + PASS_3_CHECK_DEVS_WITH_OPROMS = 2, + MAX_PASS = PASS_3_CHECK_DEVS_WITH_OPROMS +}; + +/** @brief finds the enabled, non root-bus, pci device using the most memory. + * + * @return pointer to the device + */ +struct device *find_pci_dev_max_mem(void) +{ + struct device *dev; + struct device *largest_dev = NULL; + struct resource *res; + uint64_t memory_used = 0; + uint64_t most_memory_used = 0; + uint8_t pass; + + for (pass = PASS_1_CHECK_64_BIT_BARS; pass <= MAX_PASS; pass++) { + + /* + * Loop through all pci devices that are not on bus 0, + * skipping them if they're disabled, checking to see + * which uses the most memory. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + /* Skip disabled, root bus, and non-pci devices */ + if ((!(dev->path.type == DEVICE_PATH_PCI)) || + (dev->bus->secondary == 0) || + (dev->enabled == 0)) + continue; + + /* Total the memory used by the device */ + memory_used = 0; + for (res = dev->resource_list; res; res = res->next) { + + /* don't check 32-bit bars on the first pass */ + if (pass == PASS_1_CHECK_64_BIT_BARS && + ((res->flags & IORESOURCE_PCI64) == 0)) + continue; + + /* skip devices with option roms until last */ + if ((pass < PASS_3_CHECK_DEVS_WITH_OPROMS) + && (res->index == PCI_ROM_ADDRESS)) { + memory_used = 0; + break; + } + + if (res->flags & IORESOURCE_MEM) + memory_used += res->size; + } + + /* Save the largest device found so far */ + if (memory_used > most_memory_used) { + most_memory_used = memory_used; + largest_dev = dev; + } + } + + /* break out of the pass loop when we find a device */ + if (largest_dev != NULL) + break; + } + + return largest_dev; +} + +/** @brief clear all resources for a specified device. Leave index and next. + * + */ +void clear_device_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + res->align = 0; + res->base = 0; + res->flags = 0; + res->gran = 0; + res->limit = 0; + res->size = 0; + } +} + +/** @brief clear all non-pnp resources. + * + */ +void clear_computed_resources(void) +{ + struct device *dev; + + /* + * Loop through all non-pnp devices, clearing everything except index + * and the pointer to the next resource. This keeps them from having + * to be re-allocated. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + //skip pnp devices - their resources are set early + if (dev->path.type == DEVICE_PATH_PNP) + continue; + + clear_device_resources(dev); + } +} diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..dfc290b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -248,27 +248,49 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) resource->limit = 0xffff; } else { /* A Memory mapped base address. */ - attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; - resource->flags |= IORESOURCE_MEM; - if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) - resource->flags |= IORESOURCE_PREFETCH; - attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; - if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { - /* 32bit limit. */ - resource->limit = 0xffffffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { - /* 1MB limit. */ - resource->limit = 0x000fffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { - /* 64bit limit. */ - resource->limit = 0xffffffffffffffffULL; - resource->flags |= IORESOURCE_PCI64; + if (CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE && + (resource->size > CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE)) { + /* Disable devices that attempt to allocate a BAR beyond + the max configured size. */ + printk(BIOS_WARNING, + "Device at %s requested a 0x%llx byte BAR ", + dev_path(dev), + (unsigned long long)resource->size); + printk(BIOS_WARNING, + "for register 0x%02lx.\n", + index); + printk(BIOS_WARNING, + "The device exceeded largest allowed size of 0x%lx. ", + (unsigned long) + CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE); + printk(BIOS_WARNING, "Device disabled.\n"); + dev->enabled = 0; + clear_device_resources(dev); } else { - /* Invalid value. */ - printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); - printk(BIOS_ERR, " on dev %s at index %02lx\n", - dev_path(dev), index); - resource->flags = 0; + attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; + resource->flags |= IORESOURCE_MEM; + if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) + resource->flags |= IORESOURCE_PREFETCH; + attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; + if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { + /* 32bit limit. */ + resource->limit = 0xffffffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { + /* 1MB limit. */ + resource->limit = 0x000fffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { + /* 64bit limit. */ + resource->limit = 0xffffffffffffffffULL; + resource->flags |= IORESOURCE_PCI64; + } else { + /* Invalid value. */ + printk(BIOS_ERR, + "Broken BAR with value %lx\n", + attr); + printk(BIOS_ERR, " on dev %s at index %02lx\n", + dev_path(dev), index); + resource->flags = 0; + } } } @@ -344,6 +366,8 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); + if (dev->enabled == 0) + return; index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 62460ae..c857dd2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void scan_smbus(device_t bus); void scan_lpc_bus(device_t bus); +struct device *find_pci_dev_max_mem(void); +void clear_computed_resources(void); +void clear_device_resources(struct device *dev); + /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. */

1 0

Patch set updated for coreboot: device: Resolve hang when a PCI device requests 4GB or more of MMIO space
by Ben Frisch 04 Dec '15

04 Dec '15

Ben Frisch (bfrisch(a)xes-inc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12575 -gerrit commit e3431755b234d8c95b461a60824bf0e9716f5036 Author: Benjamin Frisch <bfrisch(a)xes-inc.com> Date: Mon Nov 30 12:23:31 2015 -0600 device: Resolve hang when a PCI device requests 4GB or more of MMIO space When a PCI device's BAR requests 4GB or more MMIO space coreboot assigns the device address 0. This results in the device overlapping DRAM and the boot hangs with no feedback explaining the issue. Resolve this hang by first detecting the exhaustion that available MMIO space under 4GB. Next, selectively ignore PCI device resource requests based on the algorithm that UEFI Firmware based on tianocore.org code does to accomplish the same. This also meets requirements of the PCI Firmware Specification 3.1 and Firmware Allocation of PCI Device Resources in Windows document which states that firmware shall not allocate resources to devices that cannot fit in available 32-bit MMIO space. Modern 64-bit Linux and 64-bit Windows since Windows Vista will rebalance, allocate, and assign resources above the 4GB boundry to 64-bit PCI device MMIO BARs resources as necessary as long 64-bit MMIO space is defined in the ACPI _CRS method and the pci=realloc kernel argument is provided in Linux. The determination of which large 64-bit PCI MMIO resource requests to ignore is based on how available MMIO space resouce exhaustion is handled by the tianocore.org UEFI Firmware implemenation. If a PCI MMIO resource request cannot be satisified, MMIO PCI resource requests of devices that are not on bus 0 are skipped in the following order to attempt to make room to satisfy the remaining PCI device MMIO space requests while keeping boot criticial devices enabled: 1) Resource requests of the current PCI device with the largest 64-bit MMIO resource request (without OPROMs) 2) Resource requests of the current PCI device with the largest 32-bit MMIO resource request (without OPROMs) 3) Resource requests of the current PCI device with the largest MMIO resource request (with OPROMs) TEST=Tested on internal coreboot port based on older upstream with device presenting 128 GB BAR with latest Linux kernel, additional testing help and feedback is appreciated. Builds locally. Change-Id: I0217d627ca77431075df5e24d49d6406c35893b7 Signed-off-by: Ben Frisch <bfrisch(a)xes-inc.com> --- src/device/Kconfig | 46 ++++++++++++++++ src/device/device.c | 124 ++++++++++++++++++++++++++++++++------------ src/device/device_util.c | 109 ++++++++++++++++++++++++++++++++++++++ src/device/pci_device.c | 64 ++++++++++++++++------- src/include/device/device.h | 4 ++ 5 files changed, 295 insertions(+), 52 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 0113545..b9a734d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -389,6 +389,52 @@ config SOFTWARE_I2C I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +choice SET_MAX_MEM_BAR_SIZE + prompt "Set Maximum memory BAR size to try to allocate " + optional + help + Select the maximum size PCI device memory BAR that coreboot will try + to allocate. If a BAR is found with a values above this size, coreboot + will disable the device and will not try to allocate any BARs. + + If unsure, leave this disabled, and coreboot will find and disable any + devices that are too large to be allocated by itself. The + disadvantage is a slight boot time increase if a device has to be + disabled. + +config MAX_BAR_SIZE_256MB + bool "256 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 256 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_512MB + bool "512 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 512 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_1GB + bool "1 GB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 1 GB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +endchoice + +config MAX_MEM_BAR_SIZE_TO_ALLOCATE + hex + default 0x10000000 if MAX_BAR_SIZE_256MB + default 0x20000000 if MAX_BAR_SIZE_512MB + default 0x40000000 if MAX_BAR_SIZE_1GB + default 0 + endmenu menu "Display" diff --git a/src/device/device.c b/src/device/device.c index e23c9de..dc39dfc 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -690,7 +690,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } -static void avoid_fixed_resources(struct device *dev) +static u8 avoid_fixed_resources(struct device *dev) { struct constraints limits; struct resource *res; @@ -743,9 +743,60 @@ static void avoid_fixed_resources(struct device *dev) if (res->flags & IORESOURCE_MEM) res->base = resource_max(res); + if (res->base < lim->base) { + /* This usually happens at the domain level, usually + * caused by a device having a BAR which is too big. + * Error out so we can retry. + */ + printk(BIOS_WARNING, + "ERROR: Resource Base was lower than its limit!\n\t"); + printk(BIOS_WARNING, + "%s@%02lx: base value 0x%08llx, lower limit 0x%08llx\n", + dev_path(dev), res->index, res->base, lim->base); + return 1; + } + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); } + + return 0; +} + +static u8 avoid_all_fixed_resources(struct device *root) +{ + struct device *child; + + /* For all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_DOMAIN) { + if (avoid_fixed_resources(child)) { + printk( + BIOS_SPEW, + "Error trying to avoid fixed resources."); + + /* Now find the device which is the largest + * and disable it. + */ + struct device *largest = find_pci_dev_max_mem(); + + printk(BIOS_SPEW, "\tDisabling Device %s\n", + dev_path(largest)); + if (largest) + largest->enabled = 0; + + /* Clear out all devices on all domains, ready + * for re-scanning. + */ + printk(BIOS_SPEW, + "\tClearing old resource computations.\n"); + clear_computed_resources(); + return 1; + } + } + } + + return 0; } device_t vga_pri = 0; @@ -1022,45 +1073,54 @@ void dev_configure(void) root = &dev_root; - /* - * Each domain should create resources which contain the entire address - * space for IO, MEM, and PREFMEM resources in the domain. The - * allocation of device resources will be done from this address space. - */ + do { + /* + * Each domain should create resources which contain the entire + * address space for IO, MEM, and PREFMEM resources in the + * domain. The allocation of device resources will be done from + * this address space. + */ - /* Read the resources for the entire tree. */ + /* Read the resources for the entire tree. */ - printk(BIOS_INFO, "Reading resources...\n"); - read_resources(root->link_list); - printk(BIOS_INFO, "Done reading resources.\n"); + printk(BIOS_INFO, "Reading resources...\n"); + read_resources(root->link_list); + printk(BIOS_INFO, "Done reading resources.\n"); - print_resource_tree(root, BIOS_SPEW, "After reading."); + print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + /* Compute resources for all domains. */ + for (child = root->link_list->children; + child; + child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources( + child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + continue; + } } } - } - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); + /* Attempt to avoid all fixed resources, if this process + * succeeds then we can carry on, otherwise we should re-try. + */ + } while (avoid_all_fixed_resources(root)); /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); diff --git a/src/device/device_util.c b/src/device/device_util.c index ac18538..5d0ba50 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -921,3 +921,112 @@ int dev_count_cpu(void) return count; } + +enum allocation_passes { + PASS_1_CHECK_64_BIT_BARS = 0, + PASS_2_CHECK_32_BIT_BARS = 1, + PASS_3_CHECK_DEVS_WITH_OPROMS = 2, + MAX_PASS = PASS_3_CHECK_DEVS_WITH_OPROMS +}; + +/** @brief finds the enabled, non root-bus, pci device using the most memory. + * + * @return pointer to the device + */ +struct device *find_pci_dev_max_mem(void) +{ + struct device *dev; + struct device *largest_dev = NULL; + struct resource *res; + uint64_t memory_used = 0; + uint64_t most_memory_used = 0; + uint8_t pass; + + for (pass = PASS_1_CHECK_64_BIT_BARS; pass <= MAX_PASS; pass++) { + + /* + * Loop through all pci devices that are not on bus 0, + * skipping them if they're disabled, checking to see + * which uses the most memory. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + /* Skip disabled, root bus, and non-pci devices */ + if ((!(dev->path.type == DEVICE_PATH_PCI)) || + (dev->bus->secondary == 0) || + (dev->enabled == 0)) + continue; + + /* Total the memory used by the device */ + memory_used = 0; + for (res = dev->resource_list; res; res = res->next) { + + /* don't check 32-bit bars on the first pass */ + if (pass == PASS_1_CHECK_64_BIT_BARS && + ((res->flags & IORESOURCE_PCI64) == 0)) + continue; + + /* skip devices with option roms until last */ + if ((pass < PASS_3_CHECK_DEVS_WITH_OPROMS) + && (res->index == PCI_ROM_ADDRESS)) { + memory_used = 0; + break; + } + + if (res->flags & IORESOURCE_MEM) + memory_used += res->size; + } + + /* Save the largest device found so far */ + if (memory_used > most_memory_used) { + most_memory_used = memory_used; + largest_dev = dev; + } + } + + /* break out of the pass loop when we find a device */ + if (largest_dev != NULL) + break; + } + + return largest_dev; +} + +/** @brief clear all resources for a specified device. Leave index and next. + * + */ +void clear_device_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + res->align = 0; + res->base = 0; + res->flags = 0; + res->gran = 0; + res->limit = 0; + res->size = 0; + } +} + +/** @brief clear all non-pnp resources. + * + */ +void clear_computed_resources(void) +{ + struct device *dev; + + /* + * Loop through all non-pnp devices, clearing everything except index + * and the pointer to the next resource. This keeps them from having + * to be re-allocated. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + //skip pnp devices - their resources are set early + if (dev->path.type == DEVICE_PATH_PNP) + continue; + + clear_device_resources(dev); + } +} diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..dfc290b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -248,27 +248,49 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) resource->limit = 0xffff; } else { /* A Memory mapped base address. */ - attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; - resource->flags |= IORESOURCE_MEM; - if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) - resource->flags |= IORESOURCE_PREFETCH; - attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; - if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { - /* 32bit limit. */ - resource->limit = 0xffffffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { - /* 1MB limit. */ - resource->limit = 0x000fffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { - /* 64bit limit. */ - resource->limit = 0xffffffffffffffffULL; - resource->flags |= IORESOURCE_PCI64; + if (CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE && + (resource->size > CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE)) { + /* Disable devices that attempt to allocate a BAR beyond + the max configured size. */ + printk(BIOS_WARNING, + "Device at %s requested a 0x%llx byte BAR ", + dev_path(dev), + (unsigned long long)resource->size); + printk(BIOS_WARNING, + "for register 0x%02lx.\n", + index); + printk(BIOS_WARNING, + "The device exceeded largest allowed size of 0x%lx. ", + (unsigned long) + CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE); + printk(BIOS_WARNING, "Device disabled.\n"); + dev->enabled = 0; + clear_device_resources(dev); } else { - /* Invalid value. */ - printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); - printk(BIOS_ERR, " on dev %s at index %02lx\n", - dev_path(dev), index); - resource->flags = 0; + attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; + resource->flags |= IORESOURCE_MEM; + if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) + resource->flags |= IORESOURCE_PREFETCH; + attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; + if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { + /* 32bit limit. */ + resource->limit = 0xffffffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { + /* 1MB limit. */ + resource->limit = 0x000fffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { + /* 64bit limit. */ + resource->limit = 0xffffffffffffffffULL; + resource->flags |= IORESOURCE_PCI64; + } else { + /* Invalid value. */ + printk(BIOS_ERR, + "Broken BAR with value %lx\n", + attr); + printk(BIOS_ERR, " on dev %s at index %02lx\n", + dev_path(dev), index); + resource->flags = 0; + } } } @@ -344,6 +366,8 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); + if (dev->enabled == 0) + return; index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 62460ae..c857dd2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void scan_smbus(device_t bus); void scan_lpc_bus(device_t bus); +struct device *find_pci_dev_max_mem(void); +void clear_computed_resources(void); +void clear_device_resources(struct device *dev); + /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. */

1 0

Patch set updated for coreboot: device: Resolve hang when a PCI device requests 4GB or more of MMIO space
by Ben Frisch 03 Dec '15

03 Dec '15

Ben Frisch (bfrisch(a)xes-inc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12575 -gerrit commit 2bc20d1cf15c61e8e4b31d585402d6cafa8d8a1e Author: Benjamin Frisch <bfrisch(a)xes-inc.com> Date: Mon Nov 30 12:23:31 2015 -0600 device: Resolve hang when a PCI device requests 4GB or more of MMIO space When a PCI device's BAR requests 4GB or more MMIO space coreboot assigns the device address 0. This results in the device overlapping DRAM and the boot hangs with no feedback explaining the issue. Resolve this hang by first detecting the exhaustion that available MMIO space under 4GB. Next, selectively ignore PCI device resource requests based on the algorithm that UEFI Firmware based on tianocore.org code does to accomplish the same. This also meets requirements of the PCI Firmware Specification 3.1 and Firmware Allocation of PCI Device Resources in Windows document which states that firmware shall not allocate resources to devices that cannot fit in available 32-bit MMIO space. Modern 64-bit Linux and 64-bit Windows since Windows Vista will rebalance, allocate, and assign resources above the 4GB boundry to 64-bit PCI device MMIO BARs resources as necessary as long 64-bit MMIO space is defined in the ACPI _CRS method and the pci=realloc kernel argument is provided in Linux. The determination of which large 64-bit PCI MMIO resource requests to ignore is based on how available MMIO space resouce exhaustion is handled by the tianocore.org UEFI Firmware implemenation. If a PCI MMIO resource request cannot be satisified, MMIO PCI resource requests of devices that are not on bus 0 are skipped in the following order to attempt to make room to satisfy the remaining PCI device MMIO space requests while keeping boot criticial devices enabled: 1) Resource requests of the current PCI device with the largest 64-bit MMIO resource request (without OPROMs) 2) Resource requests of the current PCI device with the largest 32-bit MMIO resource request (without OPROMs) 3) Resource requests of the current PCI device with the largest MMIO resource request (with OPROMs) TEST=Tested on internal coreboot port based on older upstream with device presenting 128 GB BAR with latest Linux kernel, additional testing help and feedback is appreciated. Change-Id: I0217d627ca77431075df5e24d49d6406c35893b7 Signed-off-by: Ben Frisch <bfrisch(a)xes-inc.com> --- src/device/Kconfig | 46 ++++++++++++++++ src/device/device.c | 124 ++++++++++++++++++++++++++++++++------------ src/device/device_util.c | 109 ++++++++++++++++++++++++++++++++++++++ src/device/pci_device.c | 64 ++++++++++++++++------- src/include/device/device.h | 4 ++ 5 files changed, 295 insertions(+), 52 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 0113545..b9a734d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -389,6 +389,52 @@ config SOFTWARE_I2C I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +choice SET_MAX_MEM_BAR_SIZE + prompt "Set Maximum memory BAR size to try to allocate " + optional + help + Select the maximum size PCI device memory BAR that coreboot will try + to allocate. If a BAR is found with a values above this size, coreboot + will disable the device and will not try to allocate any BARs. + + If unsure, leave this disabled, and coreboot will find and disable any + devices that are too large to be allocated by itself. The + disadvantage is a slight boot time increase if a device has to be + disabled. + +config MAX_BAR_SIZE_256MB + bool "256 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 256 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_512MB + bool "512 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 512 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_1GB + bool "1 GB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 1 GB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +endchoice + +config MAX_MEM_BAR_SIZE_TO_ALLOCATE + hex + default 0x10000000 if MAX_BAR_SIZE_256MB + default 0x20000000 if MAX_BAR_SIZE_512MB + default 0x40000000 if MAX_BAR_SIZE_1GB + default 0 + endmenu menu "Display" diff --git a/src/device/device.c b/src/device/device.c index e23c9de..dc39dfc 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -690,7 +690,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } -static void avoid_fixed_resources(struct device *dev) +static u8 avoid_fixed_resources(struct device *dev) { struct constraints limits; struct resource *res; @@ -743,9 +743,60 @@ static void avoid_fixed_resources(struct device *dev) if (res->flags & IORESOURCE_MEM) res->base = resource_max(res); + if (res->base < lim->base) { + /* This usually happens at the domain level, usually + * caused by a device having a BAR which is too big. + * Error out so we can retry. + */ + printk(BIOS_WARNING, + "ERROR: Resource Base was lower than its limit!\n\t"); + printk(BIOS_WARNING, + "%s@%02lx: base value 0x%08llx, lower limit 0x%08llx\n", + dev_path(dev), res->index, res->base, lim->base); + return 1; + } + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); } + + return 0; +} + +static u8 avoid_all_fixed_resources(struct device *root) +{ + struct device *child; + + /* For all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_DOMAIN) { + if (avoid_fixed_resources(child)) { + printk( + BIOS_SPEW, + "Error trying to avoid fixed resources."); + + /* Now find the device which is the largest + * and disable it. + */ + struct device *largest = find_pci_dev_max_mem(); + + printk(BIOS_SPEW, "\tDisabling Device %s\n", + dev_path(largest)); + if (largest) + largest->enabled = 0; + + /* Clear out all devices on all domains, ready + * for re-scanning. + */ + printk(BIOS_SPEW, + "\tClearing old resource computations.\n"); + clear_computed_resources(); + return 1; + } + } + } + + return 0; } device_t vga_pri = 0; @@ -1022,45 +1073,54 @@ void dev_configure(void) root = &dev_root; - /* - * Each domain should create resources which contain the entire address - * space for IO, MEM, and PREFMEM resources in the domain. The - * allocation of device resources will be done from this address space. - */ + do { + /* + * Each domain should create resources which contain the entire + * address space for IO, MEM, and PREFMEM resources in the + * domain. The allocation of device resources will be done from + * this address space. + */ - /* Read the resources for the entire tree. */ + /* Read the resources for the entire tree. */ - printk(BIOS_INFO, "Reading resources...\n"); - read_resources(root->link_list); - printk(BIOS_INFO, "Done reading resources.\n"); + printk(BIOS_INFO, "Reading resources...\n"); + read_resources(root->link_list); + printk(BIOS_INFO, "Done reading resources.\n"); - print_resource_tree(root, BIOS_SPEW, "After reading."); + print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + /* Compute resources for all domains. */ + for (child = root->link_list->children; + child; + child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources( + child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + continue; + } } } - } - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); + /* Attempt to avoid all fixed resources, if this process + * succeeds then we can carry on, otherwise we should re-try. + */ + } while (avoid_all_fixed_resources(root)); /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); diff --git a/src/device/device_util.c b/src/device/device_util.c index ac18538..f68ca4a 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -921,3 +921,112 @@ int dev_count_cpu(void) return count; } + +enum allocation_passes { + PASS_1_CHECK_64_BIT_BARS = 0, + PASS_2_CHECK_32_BIT_BARS = 1, + PASS_3_CHECK_DEVS_WITH_OPROMS = 2, + MAX_PASS = PASS_3_CHECK_DEVS_WITH_OPROMS +}; + +/** @brief finds the enabled, non root-bus, pci device using the most memory. + * + * @return pointer to the device + */ +struct device *find_pci_dev_max_mem(void) +{ + struct device *dev; + struct device *largest_dev = NULL; + struct resource *res; + uint64_t memory_used = 0; + uint64_t most_memory_used = 0; + uint8_t pass; + + for (pass = PASS_1_CHECK_64_BIT_BARS; pass <= MAX_PASS; pass++) { + + /* + * Loop through all pci devices that are not on bus 0, + * skipping them if they're disabled, checking to see + * which uses the most memory. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + /* Skip disabled, root bus, and non-pci devices */ + if ((!(dev->path.type == DEVICE_PATH_PCI)) || + (dev->bus->secondary == 0) || + (dev->enabled == 0)) + continue; + + /* Total the memory used by the device */ + memory_used = 0; + for (res = dev->resource_list; res; res = res->next) { + + /* don't check 32-bit bars on the first pass */ + if (pass == PASS_1_CHECK_64_BIT_BARS && + ((res->flags & IORESOURCE_PCI64) == 0)) + continue; + + /* skip devices with option roms until last */ + if ((pass < PASS_3_CHECK_DEVS_WITH_OPROMS) + && (res->index == PCI_ROM_ADDRESS)) { + memory_used = 0; + break; + } + + if (res->flags & IORESOURCE_MEM) + memory_used += res->size; + } + + /* Save the largest device found so far */ + if (memory_used > most_memory_used) { + most_memory_used = memory_used; + largest_dev = dev; + } + } + + /* break out of the pass loop when we find a device */ + if (largest_dev != NULL) + break; + } + + return largest_dev; +} + +/** @brief clear all non-pnp resources. + * + */ +void clear_computed_resources(void) +{ + struct device *dev; + + /* + * Loop through all non-pnp devices, clearing everything except index + * and the pointer to the next resource. This keeps them from having + * to be re-allocated. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + //skip pnp devices - their resources are set early + if (dev->path.type == DEVICE_PATH_PNP) + continue; + + clear_device_resources(dev); + } +} + +/** @brief clear all resources for a specified device. Leave index and next. + * + */ +static void clear_device_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + res->align = 0; + res->base = 0; + res->flags = 0; + res->gran = 0; + res->limit = 0; + res->size = 0; + } +} diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..dfc290b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -248,27 +248,49 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) resource->limit = 0xffff; } else { /* A Memory mapped base address. */ - attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; - resource->flags |= IORESOURCE_MEM; - if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) - resource->flags |= IORESOURCE_PREFETCH; - attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; - if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { - /* 32bit limit. */ - resource->limit = 0xffffffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { - /* 1MB limit. */ - resource->limit = 0x000fffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { - /* 64bit limit. */ - resource->limit = 0xffffffffffffffffULL; - resource->flags |= IORESOURCE_PCI64; + if (CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE && + (resource->size > CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE)) { + /* Disable devices that attempt to allocate a BAR beyond + the max configured size. */ + printk(BIOS_WARNING, + "Device at %s requested a 0x%llx byte BAR ", + dev_path(dev), + (unsigned long long)resource->size); + printk(BIOS_WARNING, + "for register 0x%02lx.\n", + index); + printk(BIOS_WARNING, + "The device exceeded largest allowed size of 0x%lx. ", + (unsigned long) + CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE); + printk(BIOS_WARNING, "Device disabled.\n"); + dev->enabled = 0; + clear_device_resources(dev); } else { - /* Invalid value. */ - printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); - printk(BIOS_ERR, " on dev %s at index %02lx\n", - dev_path(dev), index); - resource->flags = 0; + attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; + resource->flags |= IORESOURCE_MEM; + if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) + resource->flags |= IORESOURCE_PREFETCH; + attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; + if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { + /* 32bit limit. */ + resource->limit = 0xffffffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { + /* 1MB limit. */ + resource->limit = 0x000fffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { + /* 64bit limit. */ + resource->limit = 0xffffffffffffffffULL; + resource->flags |= IORESOURCE_PCI64; + } else { + /* Invalid value. */ + printk(BIOS_ERR, + "Broken BAR with value %lx\n", + attr); + printk(BIOS_ERR, " on dev %s at index %02lx\n", + dev_path(dev), index); + resource->flags = 0; + } } } @@ -344,6 +366,8 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); + if (dev->enabled == 0) + return; index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 62460ae..c857dd2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void scan_smbus(device_t bus); void scan_lpc_bus(device_t bus); +struct device *find_pci_dev_max_mem(void); +void clear_computed_resources(void); +void clear_device_resources(struct device *dev); + /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. */

1 0

Patch set updated for coreboot: device: Resolve hang when a PCI device requests 4GB or more of MMIO space
by Ben Frisch 03 Dec '15

03 Dec '15

Ben Frisch (bfrisch(a)xes-inc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12575 -gerrit commit 6e1fcddb363c9e28cd122d17829a9ccfbf228a50 Author: Benjamin Frisch <bfrisch(a)xes-inc.com> Date: Mon Nov 30 12:23:31 2015 -0600 device: Resolve hang when a PCI device requests 4GB or more of MMIO space When a PCI device's BAR requests 4GB or more MMIO space coreboot assigns the device address 0. This results in the device overlapping DRAM and the boot hangs with no feedback explaining the issue. Resolve this hang by first detecting the exhaustion that available MMIO space under 4GB. Next, selectively ignore PCI device resource requests based on the algorithm that UEFI Firmware based on tianocore.org code does to accomplish the same. This also meets requirements of the PCI Firmware Specification 3.1 and Firmware Allocation of PCI Device Resources in Windows document which states that firmware shall not allocate resources to devices that cannot fit in available 32-bit MMIO space. Modern 64-bit Linux and 64-bit Windows since Windows Vista will rebalance, allocate, and assign resources above the 4GB boundry to 64-bit PCI device MMIO BARs resources as necessary as long 64-bit MMIO space is defined in the ACPI _CRS method and the pci=realloc kernel argument is provided in Linux. The determination of which large 64-bit PCI MMIO resource requests to ignore is based on how available MMIO space resouce exhaustion is handled by the tianocore.org UEFI Firmware implemenation. If a PCI MMIO resource request cannot be satisified, MMIO PCI resource requests of devices that are not on bus 0 are skipped in the following order to attempt to make room to satisfy the remaining PCI device MMIO space requests while keeping boot criticial devices enabled: 1) Resource requests of the current PCI device with the largest 64-bit MMIO resource request (without OPROMs) 2) Resource requests of the current PCI device with the largest 32-bit MMIO resource request (without OPROMs) 3) Resource requests of the current PCI device with the largest MMIO resource request (with OPROMs) TEST=Tested on internal coreboot port based on older upstream with device presenting 128 GB BAR with latest Linux kernel, additional testing help and feedback is appreciated. Change-Id: I0217d627ca77431075df5e24d49d6406c35893b7 Signed-off-by: Ben Frisch <bfrisch(a)xes-inc.com> --- src/device/Kconfig | 46 ++++++++++++++++ src/device/device.c | 124 ++++++++++++++++++++++++++++++++------------ src/device/device_util.c | 109 ++++++++++++++++++++++++++++++++++++++ src/device/pci_device.c | 64 ++++++++++++++++------- src/include/device/device.h | 4 ++ 5 files changed, 295 insertions(+), 52 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 0113545..b9a734d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -389,6 +389,52 @@ config SOFTWARE_I2C I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +choice SET_MAX_MEM_BAR_SIZE + prompt "Set Maximum memory BAR size to try to allocate " + optional + help + Select the maximum size PCI device memory BAR that coreboot will try + to allocate. If a BAR is found with a values above this size, coreboot + will disable the device and will not try to allocate any BARs. + + If unsure, leave this disabled, and coreboot will find and disable any + devices that are too large to be allocated by itself. The + disadvantage is a slight boot time increase if a device has to be + disabled. + +config MAX_BAR_SIZE_256MB + bool "256 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 256 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_512MB + bool "512 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 512 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_1GB + bool "1 GB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 1 GB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +endchoice + +config MAX_MEM_BAR_SIZE_TO_ALLOCATE + hex + default 0x10000000 if MAX_BAR_SIZE_256MB + default 0x20000000 if MAX_BAR_SIZE_512MB + default 0x40000000 if MAX_BAR_SIZE_1GB + default 0 + endmenu menu "Display" diff --git a/src/device/device.c b/src/device/device.c index e23c9de..dc39dfc 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -690,7 +690,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } -static void avoid_fixed_resources(struct device *dev) +static u8 avoid_fixed_resources(struct device *dev) { struct constraints limits; struct resource *res; @@ -743,9 +743,60 @@ static void avoid_fixed_resources(struct device *dev) if (res->flags & IORESOURCE_MEM) res->base = resource_max(res); + if (res->base < lim->base) { + /* This usually happens at the domain level, usually + * caused by a device having a BAR which is too big. + * Error out so we can retry. + */ + printk(BIOS_WARNING, + "ERROR: Resource Base was lower than its limit!\n\t"); + printk(BIOS_WARNING, + "%s@%02lx: base value 0x%08llx, lower limit 0x%08llx\n", + dev_path(dev), res->index, res->base, lim->base); + return 1; + } + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); } + + return 0; +} + +static u8 avoid_all_fixed_resources(struct device *root) +{ + struct device *child; + + /* For all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_DOMAIN) { + if (avoid_fixed_resources(child)) { + printk( + BIOS_SPEW, + "Error trying to avoid fixed resources."); + + /* Now find the device which is the largest + * and disable it. + */ + struct device *largest = find_pci_dev_max_mem(); + + printk(BIOS_SPEW, "\tDisabling Device %s\n", + dev_path(largest)); + if (largest) + largest->enabled = 0; + + /* Clear out all devices on all domains, ready + * for re-scanning. + */ + printk(BIOS_SPEW, + "\tClearing old resource computations.\n"); + clear_computed_resources(); + return 1; + } + } + } + + return 0; } device_t vga_pri = 0; @@ -1022,45 +1073,54 @@ void dev_configure(void) root = &dev_root; - /* - * Each domain should create resources which contain the entire address - * space for IO, MEM, and PREFMEM resources in the domain. The - * allocation of device resources will be done from this address space. - */ + do { + /* + * Each domain should create resources which contain the entire + * address space for IO, MEM, and PREFMEM resources in the + * domain. The allocation of device resources will be done from + * this address space. + */ - /* Read the resources for the entire tree. */ + /* Read the resources for the entire tree. */ - printk(BIOS_INFO, "Reading resources...\n"); - read_resources(root->link_list); - printk(BIOS_INFO, "Done reading resources.\n"); + printk(BIOS_INFO, "Reading resources...\n"); + read_resources(root->link_list); + printk(BIOS_INFO, "Done reading resources.\n"); - print_resource_tree(root, BIOS_SPEW, "After reading."); + print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + /* Compute resources for all domains. */ + for (child = root->link_list->children; + child; + child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources( + child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + continue; + } } } - } - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); + /* Attempt to avoid all fixed resources, if this process + * succeeds then we can carry on, otherwise we should re-try. + */ + } while (avoid_all_fixed_resources(root)); /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); diff --git a/src/device/device_util.c b/src/device/device_util.c index ac18538..f68ca4a 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -921,3 +921,112 @@ int dev_count_cpu(void) return count; } + +enum allocation_passes { + PASS_1_CHECK_64_BIT_BARS = 0, + PASS_2_CHECK_32_BIT_BARS = 1, + PASS_3_CHECK_DEVS_WITH_OPROMS = 2, + MAX_PASS = PASS_3_CHECK_DEVS_WITH_OPROMS +}; + +/** @brief finds the enabled, non root-bus, pci device using the most memory. + * + * @return pointer to the device + */ +struct device *find_pci_dev_max_mem(void) +{ + struct device *dev; + struct device *largest_dev = NULL; + struct resource *res; + uint64_t memory_used = 0; + uint64_t most_memory_used = 0; + uint8_t pass; + + for (pass = PASS_1_CHECK_64_BIT_BARS; pass <= MAX_PASS; pass++) { + + /* + * Loop through all pci devices that are not on bus 0, + * skipping them if they're disabled, checking to see + * which uses the most memory. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + /* Skip disabled, root bus, and non-pci devices */ + if ((!(dev->path.type == DEVICE_PATH_PCI)) || + (dev->bus->secondary == 0) || + (dev->enabled == 0)) + continue; + + /* Total the memory used by the device */ + memory_used = 0; + for (res = dev->resource_list; res; res = res->next) { + + /* don't check 32-bit bars on the first pass */ + if (pass == PASS_1_CHECK_64_BIT_BARS && + ((res->flags & IORESOURCE_PCI64) == 0)) + continue; + + /* skip devices with option roms until last */ + if ((pass < PASS_3_CHECK_DEVS_WITH_OPROMS) + && (res->index == PCI_ROM_ADDRESS)) { + memory_used = 0; + break; + } + + if (res->flags & IORESOURCE_MEM) + memory_used += res->size; + } + + /* Save the largest device found so far */ + if (memory_used > most_memory_used) { + most_memory_used = memory_used; + largest_dev = dev; + } + } + + /* break out of the pass loop when we find a device */ + if (largest_dev != NULL) + break; + } + + return largest_dev; +} + +/** @brief clear all non-pnp resources. + * + */ +void clear_computed_resources(void) +{ + struct device *dev; + + /* + * Loop through all non-pnp devices, clearing everything except index + * and the pointer to the next resource. This keeps them from having + * to be re-allocated. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + //skip pnp devices - their resources are set early + if (dev->path.type == DEVICE_PATH_PNP) + continue; + + clear_device_resources(dev); + } +} + +/** @brief clear all resources for a specified device. Leave index and next. + * + */ +static void clear_device_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + res->align = 0; + res->base = 0; + res->flags = 0; + res->gran = 0; + res->limit = 0; + res->size = 0; + } +} diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..dfc290b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -248,27 +248,49 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) resource->limit = 0xffff; } else { /* A Memory mapped base address. */ - attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; - resource->flags |= IORESOURCE_MEM; - if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) - resource->flags |= IORESOURCE_PREFETCH; - attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; - if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { - /* 32bit limit. */ - resource->limit = 0xffffffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { - /* 1MB limit. */ - resource->limit = 0x000fffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { - /* 64bit limit. */ - resource->limit = 0xffffffffffffffffULL; - resource->flags |= IORESOURCE_PCI64; + if (CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE && + (resource->size > CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE)) { + /* Disable devices that attempt to allocate a BAR beyond + the max configured size. */ + printk(BIOS_WARNING, + "Device at %s requested a 0x%llx byte BAR ", + dev_path(dev), + (unsigned long long)resource->size); + printk(BIOS_WARNING, + "for register 0x%02lx.\n", + index); + printk(BIOS_WARNING, + "The device exceeded largest allowed size of 0x%lx. ", + (unsigned long) + CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE); + printk(BIOS_WARNING, "Device disabled.\n"); + dev->enabled = 0; + clear_device_resources(dev); } else { - /* Invalid value. */ - printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); - printk(BIOS_ERR, " on dev %s at index %02lx\n", - dev_path(dev), index); - resource->flags = 0; + attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; + resource->flags |= IORESOURCE_MEM; + if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) + resource->flags |= IORESOURCE_PREFETCH; + attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; + if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { + /* 32bit limit. */ + resource->limit = 0xffffffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { + /* 1MB limit. */ + resource->limit = 0x000fffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { + /* 64bit limit. */ + resource->limit = 0xffffffffffffffffULL; + resource->flags |= IORESOURCE_PCI64; + } else { + /* Invalid value. */ + printk(BIOS_ERR, + "Broken BAR with value %lx\n", + attr); + printk(BIOS_ERR, " on dev %s at index %02lx\n", + dev_path(dev), index); + resource->flags = 0; + } } } @@ -344,6 +366,8 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); + if (dev->enabled == 0) + return; index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 62460ae..c857dd2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void scan_smbus(device_t bus); void scan_lpc_bus(device_t bus); +struct device *find_pci_dev_max_mem(void); +void clear_computed_resources(void); +void clear_device_resources(struct device *dev); + /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. */

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coreboot-gerrit December 2015