coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

Patch merged into coreboot/master: external/Makefile.inc: Update SeaBIOS version file
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit 886f47892502df15d9bb4fd0e4be3a2bde1aa5f6 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 13:23:48 2015 -0700 external/Makefile.inc: Update SeaBIOS version file SeaBIOS updated how versioning is done, and out/version.c no longer exists. The new file with version information is autoversion.h. Change-Id: I10abee73ecc51e52c9ff7a2e7a9099339b1a4b40 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12567 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/12567 for details. -gerrit

1 0

Patch merged into coreboot/master: SeaBIOS: update stable release from 1.8.2 to 1.9.0
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit ac0bc0cd66f25d8cc30d4912949658b4b382bfcf Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Nov 28 18:40:27 2015 +0100 SeaBIOS: update stable release from 1.8.2 to 1.9.0 * The default boot menu key is now the ESC key (instead of F12) * Initial support for Trusted Platform Module (TPM) hardware and BIOS calls * Initial support for chain loading SeaBIOS from Grub (via multiboot support) * Initial support for booting from SD cards on real hardware * virtio 1.0 device support * The build will no longer include the build hostname or build time on "clean" builds. This makes the build binaries more "reproducible". * Basic support for running SeaBIOS on Baytrail Chromebooks * SeaVGABIOS improvements: * Improved support for old versions of x86emu (the "leal" instruction is now emulated) * Several bug fixes and code cleanups Change-Id: Ifbd50f1884959fed4c4f666b87f2ef7b4769c6d3 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/12566 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Kevin O'Connor <kevin(a)koconnor.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12566 for details. -gerrit

1 0

Patch merged into coreboot/master: northbridge/amd/amdht: Reduce excessive romstage array size
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit 69056d945297c995640af3c89a4602fb8e28ae1d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Nov 16 11:48:38 2015 -0600 northbridge/amd/amdht: Reduce excessive romstage array size Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12573 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12573 for details. -gerrit

1 0

Patch merged into coreboot/master: arch/x86/bootblock_normal: Update to use fewer registers
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit 1b304cc23cd4e3a98a42cd72ffb5d1185321afa9 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 30 09:49:21 2015 -0700 arch/x86/bootblock_normal: Update to use fewer registers - Move initialization of entry to later in main. - Make boot_mode an unsigned char - no need to use int. - Remove unnecessary variable filenames. - Only get and try to boot fallback once. Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a Test: compiled. Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12574 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12574 for details. -gerrit

1 0

Patch merged into coreboot/master: cbfs: Fix typo in cbfs_prog_stage_load()
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit b29bd27b065bbe91598b7f373413da54c6b21056 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Dec 3 11:29:12 2015 -0800 cbfs: Fix typo in cbfs_prog_stage_load() The proper return value to signal an error from cbfs_prog_stage_load() is -1, not 0. Change-Id: Ie53b0359c7c036e3f809d1f941dab53f090b84ab Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/12633 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12633 for details. -gerrit

1 0

Patch merged into coreboot/master: braswell/skylake: Add FspUpdVpd.h to fix compilation
by gerrit＠coreboot.org 04 Dec '15

04 Dec '15

the following patch was just integrated into master: commit 1d05731e11d7fb48e940e4c40dfaf1d1a88d7bc8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:32:27 2015 -0800 braswell/skylake: Add FspUpdVpd.h to fix compilation Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams(a)intel.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12467 for details. -gerrit

1 0

New patch to review for coreboot: MAINTAINERS: Designate Intel maintainers for FSP 1.1
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12644 -gerrit commit 8158977f710890c09cb9ebe542dd837a0bfec82e Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 08:36:49 2015 -0700 MAINTAINERS: Designate Intel maintainers for FSP 1.1 After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I1aa135838984973f648dec5dbb35ff73992e9289 Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e811896..2a4a23a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -182,6 +182,14 @@ M: Martin Roth <gaumless(a)gmail.com> S: Supported F: src/drivers/intel/fsp1_0/ +INTEL FSP 1.1 +M: Lee Leahy <leroy.p.leahy(a)intel.com> +M: Andrey Petrov <andrey.petrov(a)intel.com> +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> +S: Supported +F: src/drivers/intel/fsp1_1/ + ATI MACH64 Driver S: Orphan F: src/drivers/ati/mach64/

1 0

New patch to review for coreboot: MAINTAINERS: Designate Intel maintainers for FSP 1.0 Rangeley
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12643 -gerrit commit 5a3b3bfb895ec99ade6b4f0ec48eda595b8e26cc Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 08:33:35 2015 -0700 MAINTAINERS: Designate Intel maintainers for FSP 1.0 Rangeley After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I7af7b37a5e3a233cc29adb20dd5bb8fa07dbdd53 Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8c0f7a0..e811896 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -160,6 +160,21 @@ F: src/vendorcode/intel/fsp1_0/baytrail/ F: src/mainboard/intel/bakersport_fsp/ F: src/mainboard/intel/bayleybay_fsp/ +FSP 1.0 RANGELEY & CRB +M: David Guckian <david.guckian(a)intel.com> +M: Fei Wang <fei.z.wang(a)intel.com> +S: Supported +F: src/cpu/intel/fsp_model_406dx/ +F: src/northbridge/intel/fsp_rangeley/ +F: src/southbridge/intel/fsp_rangeley/ +F: src/vendorcode/intel/fsp1_0/rangeley/ +F: src/mainboard/intel/mohonpeak/ + +INTEL LITTLE PLAINS MAINBOARD +M: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> +S: Supported +F: src/mainboard/intel/littleplains/ + INTEL FSP 1.0 M: Huang Jin <huang.jin(a)intel.com> M: York Yang <york.yang(a)intel.com>

1 0

New patch to review for coreboot: MAINTAINERS: Designate Intel maintainer for FSP 1.0 Ivy Bridge
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12642 -gerrit commit 722d03777ba72923407e124e0c868c9bcc88d733 Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 08:42:36 2015 -0700 MAINTAINERS: Designate Intel maintainer for FSP 1.0 Ivy Bridge After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I33d95db12d9e394360a207c8fbcfbc15723115c6 Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 09f0a38..8c0f7a0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -131,6 +131,18 @@ M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> S: Supported F: src/mainboard/google/panther/ +INTEL FSP IVYBRIDGE/PANTHERPOINT/CAVECREEK & CRBs +M: York Yang <york.yang(a)intel.com> +S: Supported +F: src/cpu/intel/fsp_model_206ax/ +F: src/northbridge/intel/fsp_sandybridge/ +F: src/southbridge/intel/fsp_bd82x6x/ +F: src/southbridge/intel/fsp_i89xx/ +F: src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x +F: src/vendorcode/intel/fsp1_0/ivybridge_i89xx +F: src/mainboard/intel/cougar_canyon2/ +F: src/mainboard/intel/stargo2/ + INTEL MINNOWBOARD MAX MAINBOARD M: Huang Jin <huang.jin(a)intel.com> M: York Yang <york.yang(a)intel.com>

1 0

Patch set updated for coreboot: MAINTAINERS: Designate Intel maintainers for FSP 1.0 Baytrail
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11894 -gerrit commit b0dcc8fc8385875a1c4ba960d70b33c9a89cb635 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 13 17:30:04 2015 -0700 MAINTAINERS: Designate Intel maintainers for FSP 1.0 Baytrail After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I62b2eaec8270ac1fce5bfbee3b3da68aba116b0f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Martin Roth <martinroth(a)google.com> --- MAINTAINERS | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 94bae6a..09f0a38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,20 +132,28 @@ S: Supported F: src/mainboard/google/panther/ INTEL MINNOWBOARD MAX MAINBOARD +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> M: Martin Roth <gaumless(a)gmail.com> -S: Maintained +S: Supported F: src/mainboard/intel/minnowmax/ -INTEL FSP BAYTRAIL CHIP +INTEL FSP BAYTRAIL CHIP & CRBs +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> M: Martin Roth <gaumless(a)gmail.com> -S: Odd Fixes +S: Supported F: src/soc/intel/fsp_baytrail/ +F: src/vendorcode/intel/fsp1_0/baytrail/ +F: src/mainboard/intel/bakersport_fsp/ +F: src/mainboard/intel/bayleybay_fsp/ INTEL FSP 1.0 +M: Huang Jin <huang.jin(a)intel.com> +M: York Yang <york.yang(a)intel.com> M: Martin Roth <gaumless(a)gmail.com> -S: Odd Fixes +S: Supported F: src/drivers/intel/fsp1_0/ -F: src/vendorcode/intel/fsp1_0/ ATI MACH64 Driver S: Orphan

1 0

← Newer
1
...
56
57
58
59
60
61
62
...
76
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2015