coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: SeaBIOS: remove VERSION variable in coreboot Makefile
by gerrit＠coreboot.org 06 Dec '15

06 Dec '15

the following patch was just integrated into master: commit 7b45d07cff5827f1014cd704f746b729edbf5c7b Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Fri Dec 4 18:39:20 2015 +0100 SeaBIOS: remove VERSION variable in coreboot Makefile SeaBIOS dropped support of VERSION variable and is reproducible without it. Change-Id: Iea1dc20e18aa5c274060e3cd55cd9e95086a602d Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/12645 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Kevin O'Connor <kevin(a)koconnor.net> See https://review.coreboot.org/12645 for details. -gerrit

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Patch set updated for coreboot: Switch to fmap based firmware layout
by Patrick Georgi 05 Dec '15

05 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11692 -gerrit commit 252f323262012020935e55fe015c23eec81384fe Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Sep 16 18:10:52 2015 +0200 Switch to fmap based firmware layout We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 90 +++++++++++++++++++++++++++++++++++++++++-- util/cbfstool/default-x86.fmd | 15 ++++++++ util/cbfstool/default.fmd | 18 +++++++++ 3 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6a553fb..217e779 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,10 +619,92 @@ prebuild-files = \ $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create \ - -B $(objcbfs)/bootblock.bin \ - $(CBFSTOOL_PRE1_OPTS) +ifeq ($(CONFIG_FMDFILE),) +# For a description of the flash layout described by these variables, check +# the $(DEFAULT_FLASHMAP) .fmd files. +ifeq ($(CONFIG_ARCH_X86),y) +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd +# entire flash +FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE) +FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE)) +else +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd +# entire flash +FMAP_ROM_ADDR := 0 +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := 0 +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0x20000 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) +FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +endif + +$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) + sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ + $(DEFAULT_FLASHMAP) > $@.tmp + mv $@.tmp $@ +else +$(obj)/fmap.fmd: $(CONFIG_FMDFILE) + cp $< $@ +endif + +# generated at the same time as fmap.fmap +$(obj)/fmap.h: $(obj)/fmap.fmap + +$(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) + $(FMAPTOOL) -h $(obj)/fmap.h $< $@ + +$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap + $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap +ifeq ($(CONFIG_ARCH_X86),y) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) +else + # don't add bootblock to cbfs yet, it's just a waste of space + true $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b 0 + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin + # make space for the CBFS master header pointer. "ptr_" is just + # arbitrary 4 bytes that will be overwritten by add-master-header. + printf "ptr_" > $@.tmp.2 + $(CBFSTOOL) $@.tmp add \ + -f $@.tmp.2 \ + -n "header pointer" \ + -t "cbfs header" \ + -b -4 + rm -f $@.tmp.2 +endif + $(CBFSTOOL) $@.tmp add-master-header $(prebuild-files) true mv $@.tmp $@ else diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd new file mode 100644 index 0000000..f344ab2 --- /dev/null +++ b/util/cbfstool/default-x86.fmd @@ -0,0 +1,15 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd new file mode 100644 index 0000000..32ddfa4 --- /dev/null +++ b/util/cbfstool/default.fmd @@ -0,0 +1,18 @@ +# layout for firmware when flash address space matches used address layout +# +-------------+ <-- 0 +# | unspecified | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + BOOTBLOCK 128K + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +}

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Patch merged into coreboot/master: build system: add dependencies for GRUB2 and FILO
by gerrit＠coreboot.org 05 Dec '15

05 Dec '15

the following patch was just integrated into master: commit 864b48daf053265257e56d44142db2e27b84c873 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Dec 4 16:52:18 2015 +0100 build system: add dependencies for GRUB2 and FILO Make sure the build system knows how to start building the various integrated payloads we support. Change-Id: I2128d09c78795e0a41b055975e9f7052e3d951ee Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: https://review.coreboot.org/12641 Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12641 for details. -gerrit

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Patch merged into coreboot/master: build system: Drop useless variable and dependency
by gerrit＠coreboot.org 05 Dec '15

05 Dec '15

the following patch was just integrated into master: commit ec90adb2e71b9e654cc1007143aa450c3996b4a8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Dec 4 17:45:19 2015 +0100 build system: Drop useless variable and dependency We don't need COREBOOT_ROM_DEPENDENCIES anymore because the dependencies are taken care of by the cbfs-files mechanism. REFCODE_BLOB also doesn't need to be an explicit dependency. Change-Id: I3f32cce79683e57a174724179bc2ac59a8cdda94 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/12648 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/12648 for details. -gerrit

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Patch set updated for coreboot: Switch to fmap based firmware layout
by Patrick Georgi 05 Dec '15

05 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11692 -gerrit commit 2cc08446f643a1b35a86ec8baddd9d7735ae8257 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Sep 16 18:10:52 2015 +0200 Switch to fmap based firmware layout We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 90 +++++++++++++++++++++++++++++++++++++++++-- util/cbfstool/default-x86.fmd | 15 ++++++++ util/cbfstool/default.fmd | 18 +++++++++ 3 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6a553fb..bcca0be 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,10 +619,92 @@ prebuild-files = \ $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create \ - -B $(objcbfs)/bootblock.bin \ - $(CBFSTOOL_PRE1_OPTS) +ifeq ($(CONFIG_FMDFILE),) +# For a description of the flash layout described by these variables, check +# the $(DEFAULT_FLASHMAP) .fmd files. +ifeq ($(CONFIG_ARCH_X86),y) +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd +# entire flash +FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE) +FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE)) +else +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd +# entire flash +FMAP_ROM_ADDR := 0 +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := 0 +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0x10000 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) +FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +endif + +$(obj)/fmap.fmd: + sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ + $(DEFAULT_FLASHMAP) > $@.tmp + mv $@.tmp $@ +else +$(obj)/fmap.fmd: $(CONFIG_FMDFILE) + cp $< $@ +endif + +# generated at the same time as fmap.fmap +$(obj)/fmap.h: $(obj)/fmap.fmap + +$(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) + $(FMAPTOOL) -h $(obj)/fmap.h $< $@ + +$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap + $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap +ifeq ($(CONFIG_ARCH_X86),y) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) +else + # don't add bootblock to cbfs yet, it's just a waste of space + true $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b 0 + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin + # make space for the CBFS master header pointer. "ptr_" is just + # arbitrary 4 bytes that will be overwritten by add-master-header. + printf "ptr_" > $@.tmp.2 + $(CBFSTOOL) $@.tmp add \ + -f $@.tmp.2 \ + -n "header pointer" \ + -t "cbfs header" \ + -b -4 + rm -f $@.tmp.2 +endif + $(CBFSTOOL) $@.tmp add-master-header $(prebuild-files) true mv $@.tmp $@ else diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd new file mode 100644 index 0000000..f344ab2 --- /dev/null +++ b/util/cbfstool/default-x86.fmd @@ -0,0 +1,15 @@ +# layout for firmware residing at top of 4GB address space +# +-------------+ <-- 4GB - ROM_SIZE / start of flash +# | unspecified | +# +-------------+ <-- 4GB - BIOS_SIZE +# | FMAP | +# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE +# | CBFS | +# +-------------+ <-- 4GB / end of flash + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd new file mode 100644 index 0000000..cca1c55 --- /dev/null +++ b/util/cbfstool/default.fmd @@ -0,0 +1,18 @@ +# layout for firmware when flash address space matches used address layout +# +-------------+ <-- 0 +# | unspecified | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 64K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 64K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + BOOTBLOCK 64K + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +}

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New patch to review for coreboot: MAINTAINERS: add myself to lenovo boards + ec
by Alexander Couzens 05 Dec '15

05 Dec '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12650 -gerrit commit d49f598c1cc8e1bb1e9564349cb0d041f048db52 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Dec 5 13:45:27 2015 +0100 MAINTAINERS: add myself to lenovo boards + ec Change-Id: I94835e85046b5d2b63b9b822c0dc670bf939e57e Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bb589c7..3873791 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -125,6 +125,16 @@ S: Maintained F: src/arch/riscv/ F: src/mainboard/emulation/qemu-riscv/ +LENOVO EC +M: Alexander Couzens <lynxis(a)fe80.eu> +S: Maintained +F: src/ec/lenovo/ + +LENOVO MAINBOARDS +M: Alexander Couzens <lynxis(a)fe80.eu> +S: Maintained +F: src/mainboard/lenovo/ + GOOGLE PANTHER MAINBOARD M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> S: Supported

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Patch set updated for coreboot: amdfam10/northbridge: fix amdfam10_scan_chain()
by Jonathan A. Kollasch 05 Dec '15

05 Dec '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10983 -gerrit commit bc9eb5c57dad8b2adfdfea67bbf67caac1601957 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 20 07:43:32 2015 -0500 amdfam10/northbridge: fix amdfam10_scan_chain() Fixes two issues introduced recently: - The subordinate bus limit was reduced from essentially unlimited (0xfc) to 0 additional busses. This caused config space of subordinate busses of a non-primary HT IO chain to become unrouted (and thus invisible) during initial scan. Introduced in I41aeb80121f120641b65759c8502150ce89caa30 and I297de09dcf93511acece4441593ef958a390fddb and reinforced in subsequent related changes. - The HTcap+0x14 register is *not* the same on K8 and 10h. 10h has isochronous HT link buffer controls where K8 had bus numbers. Introduced in I41aeb80121f120641b65759c8502150ce89caa30 These two issues resulted in the non-primary IO chain not having resources allocated to subordinate busses due to the devices being invisible during initial scan, and for MMIO accesses to devices on the base bus of the non-primary chain to stall the whole machine, presumably due to invalid HT buffer allocations. Change-Id: I7a1f51bd91ab3dae6ed1c447209b36003830f3dc Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/northbridge/amd/amdfam10/northbridge.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c8bf8fa..0c061d1 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -160,7 +160,6 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } typedef enum { - HT_ROUTE_CLOSE, HT_ROUTE_SCAN, HT_ROUTE_FINAL, } scan_state; @@ -185,13 +184,7 @@ static void ht_route_link(struct bus *link, scan_state mode) */ busses = pci_read_config32(link->dev, link->cap + 0x14); busses &= ~(0xff << 8); - busses |= parent->secondary & 0xff; - if (mode == HT_ROUTE_CLOSE) - busses |= 0xff << 8; - else if (mode == HT_ROUTE_SCAN) - busses |= ((u32) link->secondary & 0xff) << 8; - else if (mode == HT_ROUTE_FINAL) - busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->secondary & 0xff) << 8; pci_write_config32(link->dev, link->cap + 0x14, busses); if (mode == HT_ROUTE_FINAL) { @@ -251,6 +244,7 @@ static void amd_g34_fixup(struct bus *link, device_t dev) static void amdfam10_scan_chain(struct bus *link) { unsigned int next_unitid; + uint16_t sub; /* See if there is an available configuration space mapping * register in function 1. @@ -266,7 +260,10 @@ static void amdfam10_scan_chain(struct bus *link) ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ + sub = link->subordinate; + link->subordinate = 0xfc; set_config_map_reg(link); + link->subordinate = sub; /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link

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New patch to review for coreboot: toolchain.inc: verify tool variable validity before using it.
by Martin Roth 04 Dec '15

04 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12649 -gerrit commit 4400d3ddb809354725f9accce595fe28fedac722 Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 14:29:37 2015 -0700 toolchain.inc: verify tool variable validity before using it. If the toolchain for a stage/architecture wasn't present, we'd call the shell with '-v', generating an ugly warning: /bin/sh: - : invalid option Usage: /bin/sh [GNU long option] [option] ... /bin/sh [GNU long option] [option] script-file ... GNU long options: ... Change-Id: Icd6d7a00083ee1695591ff96da36b7868be0c2f0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- toolchain.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index 1b73ce9..541dc1a 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -155,10 +155,10 @@ IASLFAIL:=0 ifeq ($(CONFIG_COMPILER_GCC),y) ifneq ($(CONFIG_ANY_TOOLCHAIN),y) $(foreach arch,$(sort $(foreach stage,$(COREBOOT_STANDARD_STAGES),$(ARCH-$(stage)-y))), \ - $(if $(shell $(CC_$(arch)) -v 2>&1 |grep -q "gcc version .*coreboot toolchain" || echo not-coreboot), \ + $(if $(shell if [ -n "$(CC_$(arch))" ]; then "$(CC_$(arch))" -v 2>&1 |grep -q "gcc version .*coreboot toolchain" || echo not-coreboot; else echo not-coreboot; fi), \ $(eval COMPILERFAIL:=1)$(warning Please use the coreboot toolchain for '$(arch)'))) #if iasl doesn't match the current coreboot version, fail the test -$(if $(shell $(IASL) -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot), \ +$(if $(shell if [ -n "$(IASL)" ]; then "$(IASL)" -v 2>&1 | grep -q "$(shell util/crossgcc/buildgcc -s iasl)" || echo not-coreboot; else echo not-coreboot; fi), \ $(eval COMPILERFAIL:=1)$(eval IASLFAIL:=1)$(warning Please use the coreboot toolchain version of iasl - $(shell util/crossgcc/buildgcc -s iasl))) endif endif

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New patch to review for coreboot: build system: Drop useless variable and dependency
by Patrick Georgi 04 Dec '15

04 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12648 -gerrit commit 60113bba517cc20ba8dab6072e57282f841a785a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Dec 4 17:45:19 2015 +0100 build system: Drop useless variable and dependency We don't need COREBOOT_ROM_DEPENDENCIES anymore because the dependencies are taken care of by the cbfs-files mechanism. REFCODE_BLOB also doesn't need to be an explicit dependency. Change-Id: I3f32cce79683e57a174724179bc2ac59a8cdda94 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 4 +--- payloads/external/Makefile.inc | 13 ------------- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 4bccefb..6a553fb 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -599,8 +599,6 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug # Build the final rom image ########################################################################### -COREBOOT_ROM_DEPENDENCIES:= - extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-)))) cbfs-add-cmd = \ @@ -658,7 +656,7 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(call strip_quotes,$$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $(REFCODE_BLOB) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 47a4964..d15c398 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -15,19 +15,6 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_PAYLOAD_ELF),y) -COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) -endif -ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -COREBOOT_ROM_DEPENDENCIES+=seabios -endif -ifeq ($(CONFIG_PAYLOAD_FILO),y) -COREBOOT_ROM_DEPENDENCIES+=filo -endif -ifeq ($(CONFIG_PAYLOAD_GRUB2),y) -COREBOOT_ROM_DEPENDENCIES+=grub2 -endif - ###################################################################### # set up payload config and version files for later inclusion ifeq ($(CONFIG_PAYLOAD_SEABIOS),y)

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Patch set updated for coreboot: Switch to fmap based firmware layout
by Patrick Georgi 04 Dec '15

04 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11692 -gerrit commit ef1444eb0a6334d356b4f454e6b39afba27a53d8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Sep 16 18:10:52 2015 +0200 Switch to fmap based firmware layout We still add a master header for compatibility purposes, and the default layouts don't cover anything non-coreboot (eg. IFD regions) yet. The default layouts can be overridden by specifying an fmd file, from which the fmap is generated. Future work: - map IFD regions to fmap regions - non-x86: build minimalistic trampolines that jump into the first cbfs file, so the bootblock can be part of CBFS instead of reserving a whole 64K for it. - teach coreboot's cbfs code to work without the master header - teach coreboot's cbfs code to work on different fmap regions Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 75 +++++++++++++++++++++++++++++++++++++++++-- util/cbfstool/default-x86.fmd | 15 +++++++++ util/cbfstool/default.fmd | 17 ++++++++++ 3 files changed, 104 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6a553fb..e7b7ace 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -619,10 +619,79 @@ prebuild-files = \ $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) +ifeq ($(CONFIG_ARCH_X86),y) +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd +# entire flash +FMAP_ROM_BASE := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(FMAP_FMAP_SIZE) +FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_FMAP_SIZE)) +else +DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd +# entire flash +FMAP_ROM_BASE := 0 +FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) +# entire "BIOS" region (everything directly of concern to the host system) +# relative to ROM_BASE +FMAP_BIOS_BASE := 0 +FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +# position and size of flashmap, relative to BIOS_BASE +FMAP_FMAP_BASE := 0x10000 +FMAP_FMAP_SIZE := 0x100 +# position and size of CBFS, relative to BIOS_BASE +FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) +FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +endif + $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create \ - -B $(objcbfs)/bootblock.bin \ - $(CBFSTOOL_PRE1_OPTS) +ifeq ($(CONFIG_FMDFILE),) + sed -e "s,##ROM_BASE##,$(FMAP_ROM_BASE)," \ + -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ + $(DEFAULT_FLASHMAP) > $@.tmp.fmd + $(FMAPTOOL) $@.tmp.fmd $@.tmp.fmap +else + $(FMAPTOOL) $(CONFIG_FMDFILE) $@.tmp.fmap +endif + $(CBFSTOOL) $@.tmp create -M $@.tmp.fmap +ifeq ($(CONFIG_ARCH_X86),y) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) +else + # don't add bootblock to cbfs yet, it's just a waste of space + true $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b 0 + $(CBFSTOOL) $@.tmp write -u \ + -r BOOTBLOCK \ + -f $(objcbfs)/bootblock.bin + printf "ptr_" > $@.tmp.2 # 4 characters + $(CBFSTOOL) $@.tmp add \ + -f $@.tmp.2 \ + -n "header pointer" \ + -t "cbfs header" \ + -b -4 + rm -f $@.tmp.2 +endif + $(CBFSTOOL) $@.tmp add-master-header $(prebuild-files) true mv $@.tmp $@ else diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd new file mode 100644 index 0000000..d7d0326 --- /dev/null +++ b/util/cbfstool/default-x86.fmd @@ -0,0 +1,15 @@ +# layout for firmware residing at top of 4GB address space +# 4GB - ROM_SIZE: start of flash +# 4GB - CBFS_SIZE: start of fmap +# + 0x100: start of CBFS +# 4GB end of flash + +# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already +# excludes the fmap size. CONFIG_CBFS_SIZE contains it. + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/util/cbfstool/default.fmd b/util/cbfstool/default.fmd new file mode 100644 index 0000000..21617d5 --- /dev/null +++ b/util/cbfstool/default.fmd @@ -0,0 +1,17 @@ +# layout for firmware when flash address space matches used address layout +# 0: start of flash, start of bootblock region +# 0x10000: start of fmap +# 0x10100: start of cbfs +# CBFS_SIZE end of fmap, end of used flash space +# ROM_SIZE end of flash + +# ##CBFS_SIZE## differs from the CBFS_SIZE specified above in that it already +# excludes the fmap size. CONFIG_CBFS_SIZE contains it. + +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + BOOTBLOCK 64K + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +}

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coreboot-gerrit December 2015