coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Makefile.inc: Add AMDFWTOOL to tools so abuild will stop failing
by Martin Roth 06 Dec '15

06 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12647 -gerrit commit 1bad995dc709419d5959a2cf8207ae8b4d3091fd Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 13:11:35 2015 -0700 Makefile.inc: Add AMDFWTOOL to tools so abuild will stop failing Jenkins keeps failing trying to build AMDFWTOOL because it's being built by multiple platforms at the same time. Putting it into the tools list and having it built ahead of time should fix this problem. Change-Id: I2a8308036135729f0ed19502f3e039aca009b3f3 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 4bccefb..adf52bc 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -549,7 +549,7 @@ crosstools-riscv: clean-for-update crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) ########################################################################### # Common recipes for all stages

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Patch merged into coreboot/master: fsp_model_406dx: use external microcode .h files for rangeley
by gerrit＠coreboot.org 06 Dec '15

06 Dec '15

the following patch was just integrated into master: commit ea7b6366075ef9f3eac5c6b75b58c153f8875581 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 5 09:00:20 2015 -0700 fsp_model_406dx: use external microcode .h files for rangeley The microcode for the Rangeley chip is supplied as .h files in the Rangeley FSP POSTGOLD4 package. When the rangeley microcode gets put into the blobs directory, this can be reverted and the binary file put into the makefile. Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12335 for details. -gerrit

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Patch merged into coreboot/master: intel/eagleheights: Fix IASL warnings
by gerrit＠coreboot.org 06 Dec '15

06 Dec '15

the following patch was just integrated into master: commit c4fa3fdd3ea3f8e05cbbc881d45d1fb1927b525d Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 16:27:53 2015 -0700 intel/eagleheights: Fix IASL warnings The eagleheights platform had 3 warnings: The SIO device needs an _ADR object to specify the address in addition to the operating region. Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. dsdt.aml 341: Device(SIO) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 140: Method (_OSC, 4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 140: Method (_OSC, 4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) - Remove Kconfig default disabling IASL warnings as errors. Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12522 for details. -gerrit

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Patch merged into coreboot/master: Makefile: Individualize help targets & set as non-compile targets
by gerrit＠coreboot.org 06 Dec '15

06 Dec '15

the following patch was just integrated into master: commit c24f3d615a2a8ed7e251f6ac88d305c8345d3ea3 Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 25 12:50:25 2015 -0700 Makefile: Individualize help targets & set as non-compile targets - Including the help targets in the list of NOCOMPILE targets means they can run even if the toolchain is mucked up. Since they contain info on building the toolchin, this is useful. - Separate the three current parts of the help target into individual components: help_coreboot, help_toolchain, and help_kconfig. This is mostly for the help_toolchin target which will be printed out by toolchain.inc. Change-Id: I365d95fd63e22bddd122fb1fede6f04270e03d63 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12542 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12542 for details. -gerrit

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New patch to review for coreboot: google: veyron: Add commercial board names in Kconfig.name
by Denis Carikli 06 Dec '15

06 Dec '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12652 -gerrit commit d3bc98a64b0be2b334e0818d4b12c3384b145742 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Dec 6 11:54:39 2015 +0100 google: veyron: Add commercial board names in Kconfig.name The correspondance between engineering code names and commercial names can be found on chromium.org website at: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-de… The devices for which such information was added are laptops, So SYSTEM_TYPE_LAPTOP was selected for theses. This it to makes the names more relevant: towiki (in util/board_status/to-wiki/towiki.sh) will pick such names, which ends up in the supported board list at: http://www.coreboot.org/Supported_Motherboards Change-Id: I2d705672d7202964fea3f62a5bd61a231d3f14c0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/google/veyron/Kconfig.name | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/veyron/Kconfig.name b/src/mainboard/google/veyron/Kconfig.name index 5c7a44b..c586293 100644 --- a/src/mainboard/google/veyron/Kconfig.name +++ b/src/mainboard/google/veyron/Kconfig.name @@ -3,20 +3,24 @@ config BOARD_GOOGLE_VEYRON_GUS select BOARD_GOOGLE_VEYRON config BOARD_GOOGLE_VEYRON_JAQ - bool "Veyron_Jaq" + bool "Haier Chromebook 11 (Veyron_Jaq)" select BOARD_GOOGLE_VEYRON + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_JERRY - bool "Veyron_Jerry" + bool "Hisense Chromebook 11 (Veyron_Jerry)" select BOARD_GOOGLE_VEYRON + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_MIGHTY - bool "Veyron_Mighty" + bool "Haier Chromebook 11(edu) (Veyron_Mighty)" select BOARD_GOOGLE_VEYRON + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_MINNIE - bool "Veyron_Minnie" + bool "ASUS Chromebook Flip C100 (Veyron_Minnie)" select BOARD_GOOGLE_VEYRON + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_NICKY bool "Veyron_Nicky" @@ -31,8 +35,9 @@ config BOARD_GOOGLE_VEYRON_SHARK select BOARD_GOOGLE_VEYRON config BOARD_GOOGLE_VEYRON_SPEEDY - bool "Veyron_Speedy" + bool "ASUS C201 Chromebook (Veyron_Speedy)" select BOARD_GOOGLE_VEYRON + select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_VEYRON_THEA bool "Veyron_Thea"

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock
by Timothy Pearson 06 Dec '15

06 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12651 -gerrit commit 4d5b3935d68ff166c010dfae970c55c38fb2a663 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Dec 6 00:47:17 2015 -0600 mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yet been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/bootblock.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c index 0289f08..6f2c0a1 100644 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ b/src/mainboard/asus/kgpe-d16/bootblock.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <pc80/mc146818rtc.h> void bootblock_mainboard_init(void) @@ -27,7 +28,10 @@ void bootblock_mainboard_init(void) bootblock_southbridge_init(); /* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */ - recovery_enabled = (!(pci_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); + byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56); + byte |= 0x1 << 4; /* Set GPIO61 to input mode */ + pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte); + recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); if (recovery_enabled) { #if CONFIG_USE_OPTION_TABLE /* Clear NVRAM checksum */ @@ -45,4 +49,4 @@ void bootblock_mainboard_init(void) */ #endif } -} \ No newline at end of file +}

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New patch to review for coreboot: mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock
by Timothy Pearson 06 Dec '15

06 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12651 -gerrit commit 5d5def83b60d11a0a576bfaacdcebbe4dde204b3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Dec 6 00:47:17 2015 -0600 mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yeu been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/bootblock.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c index 0289f08..8cd70d5 100644 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ b/src/mainboard/asus/kgpe-d16/bootblock.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <pc80/mc146818rtc.h> void bootblock_mainboard_init(void) @@ -27,7 +28,10 @@ void bootblock_mainboard_init(void) bootblock_southbridge_init(); /* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */ - recovery_enabled = (!(pci_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); + byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56); + byte |= 0x1 << 4; /* Set GPIO61 to input mode */ + pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte) + recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1)); if (recovery_enabled) { #if CONFIG_USE_OPTION_TABLE /* Clear NVRAM checksum */ @@ -45,4 +49,4 @@ void bootblock_mainboard_init(void) */ #endif } -} \ No newline at end of file +}

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Patch set updated for coreboot: Enable KCONFIG_STRICT mode
by Stefan Reinauer 06 Dec '15

06 Dec '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10978 -gerrit commit f6360f095fdc1ed1913586f6af92eef50418063a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 17:29:19 2015 -0700 Enable KCONFIG_STRICT mode Change-Id: I6aa77db1b12a67472302ea39d7433993a6838af6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 05da7be..92ead87 100644 --- a/Makefile +++ b/Makefile @@ -57,6 +57,7 @@ export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd export KCONFIG_SPLITCONFIG := $(obj)/config export KCONFIG_TRISTATE := $(obj)/tristate.conf export KCONFIG_NEGATIVES := 1 +export KCONFIG_STRICT := 1 # directory containing the toplevel Makefile.inc TOPLEVEL := .

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Patch set updated for coreboot: 3rdparty/blobs: Update for latest Carrizo Blobs
by Stefan Reinauer 06 Dec '15

06 Dec '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12425 -gerrit commit a449f1817be3c3955818e21f1f1b491d63b11595 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:44:49 2015 -0700 3rdparty/blobs: Update for latest Carrizo Blobs Update the 3rdparty/blobs submodule to bring in the latest CarrizoPI binaries. Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078 Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index aab093f..b0eeddd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit aab093f0824b6d26b57a1ce220ba0d577e37ad49 +Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2

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Patch set updated for coreboot: intel/fsp_rangeley: change non-existent config options to #defines
by Stefan Reinauer 06 Dec '15

06 Dec '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12552 -gerrit commit 2690bf5a6ca458a67cd2579b22bf652b20ee2420 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 15:58:12 2015 -0700 intel/fsp_rangeley: change non-existent config options to #defines Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/acpi/mainboard.asl | 3 +++ src/mainboard/intel/littleplains/dsdt.asl | 3 +++ src/mainboard/intel/mohonpeak/acpi/mainboard.asl | 3 +++ src/mainboard/intel/mohonpeak/dsdt.asl | 3 +++ src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 4 ++-- 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/littleplains/acpi/mainboard.asl b/src/mainboard/intel/littleplains/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/littleplains/acpi/mainboard.asl +++ b/src/mainboard/intel/littleplains/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index dbb8b15..ec56e26 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -23,6 +23,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl +++ b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index dbb8b15..ec56e26 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -23,6 +23,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 22edf50..696a81a 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -30,7 +30,7 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_PMIO) +#ifdef ACPI_INCLUDE_PMIO // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) @@ -77,7 +77,7 @@ Scope(\) } #endif -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_GPIO) +#ifdef ACPI_INCLUDE_GPIO // GPIO IO mapped registers (0x1f.0 reg 0x48.l) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve)

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coreboot-gerrit December 2015